diff options
author | Ben Cahill <ben.m.cahill@intel.com> | 2007-11-28 22:09:45 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-01-28 18:05:15 -0500 |
commit | 796083cb1d45d52d40ae2c933afcfc56d91ef427 (patch) | |
tree | c5dc4a5e7d6437a2a073ee15996f3b1e3ff7e657 /drivers/net/wireless/iwlwifi/iwl-3945-hw.h | |
parent | 7762635547ad31ecb045e7073989e76ae13e6c54 (diff) |
iwlwifi: add comments to EEPROM stuff
Add comments to EEPROM stuff.
Signed-off-by: Ben Cahill <ben.m.cahill@intel.com>
Signed-off-by: Zhu Yi <yi.zhu@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-3945-hw.h')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-3945-hw.h | 94 |
1 files changed, 81 insertions, 13 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h index 8bbaa16442a..2c9f884be03 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h +++ b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h | |||
@@ -85,24 +85,48 @@ | |||
85 | #define IWL_RSSI_OFFSET 95 | 85 | #define IWL_RSSI_OFFSET 95 |
86 | 86 | ||
87 | /* | 87 | /* |
88 | * This file defines EEPROM related constants, enums, and inline functions. | 88 | * EEPROM related constants, enums, and structures. |
89 | * | ||
90 | */ | 89 | */ |
91 | 90 | ||
91 | /* | ||
92 | * EEPROM access time values: | ||
93 | * | ||
94 | * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG, | ||
95 | * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit | ||
96 | * CSR_EEPROM_REG_BIT_CMD (0x2). | ||
97 | * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). | ||
98 | * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. | ||
99 | * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. | ||
100 | */ | ||
92 | #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ | 101 | #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ |
93 | #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */ | 102 | #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */ |
103 | |||
94 | /* EEPROM field values */ | 104 | /* EEPROM field values */ |
95 | #define ANTENNA_SWITCH_NORMAL 0 | 105 | #define ANTENNA_SWITCH_NORMAL 0 |
96 | #define ANTENNA_SWITCH_INVERSE 1 | 106 | #define ANTENNA_SWITCH_INVERSE 1 |
97 | 107 | ||
108 | /* | ||
109 | * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags. | ||
110 | * | ||
111 | * IBSS and/or AP operation is allowed *only* on those channels with | ||
112 | * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because | ||
113 | * RADAR detection is not supported by the 3945 driver, but is a | ||
114 | * requirement for establishing a new network for legal operation on channels | ||
115 | * requiring RADAR detection or restricting ACTIVE scanning. | ||
116 | * | ||
117 | * NOTE: "WIDE" flag indicates that 20 MHz channel is supported; | ||
118 | * 3945 does not support FAT 40 MHz-wide channels. | ||
119 | * | ||
120 | * NOTE: Using a channel inappropriately will result in a uCode error! | ||
121 | */ | ||
98 | enum { | 122 | enum { |
99 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ | 123 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ |
100 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ | 124 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ |
101 | /* Bit 2 Reserved */ | 125 | /* Bit 2 Reserved */ |
102 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ | 126 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ |
103 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ | 127 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ |
104 | EEPROM_CHANNEL_WIDE = (1 << 5), | 128 | EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ |
105 | EEPROM_CHANNEL_NARROW = (1 << 6), | 129 | EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel, not used */ |
106 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ | 130 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ |
107 | }; | 131 | }; |
108 | 132 | ||
@@ -147,6 +171,7 @@ struct iwl3945_eeprom_channel { | |||
147 | * long packets in normal operation to provide feedback as to proper output | 171 | * long packets in normal operation to provide feedback as to proper output |
148 | * level. | 172 | * level. |
149 | * Data copied from EEPROM. | 173 | * Data copied from EEPROM. |
174 | * DO NOT ALTER THIS STRUCTURE!!! | ||
150 | */ | 175 | */ |
151 | struct iwl3945_eeprom_txpower_sample { | 176 | struct iwl3945_eeprom_txpower_sample { |
152 | u8 gain_index; /* index into power (gain) setup table ... */ | 177 | u8 gain_index; /* index into power (gain) setup table ... */ |
@@ -163,11 +188,11 @@ struct iwl3945_eeprom_txpower_sample { | |||
163 | * DO NOT ALTER THIS STRUCTURE!!! | 188 | * DO NOT ALTER THIS STRUCTURE!!! |
164 | */ | 189 | */ |
165 | struct iwl3945_eeprom_txpower_group { | 190 | struct iwl3945_eeprom_txpower_group { |
166 | struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ | 191 | struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ |
167 | s32 a, b, c, d, e; /* coefficients for voltage->power | 192 | s32 a, b, c, d, e; /* coefficients for voltage->power |
168 | * formula (signed) */ | 193 | * formula (signed) */ |
169 | s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on | 194 | s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on |
170 | * frequency (signed) */ | 195 | * frequency (signed) */ |
171 | s8 saturation_power; /* highest power possible by h/w in this | 196 | s8 saturation_power; /* highest power possible by h/w in this |
172 | * band */ | 197 | * band */ |
173 | u8 group_channel; /* "representative" channel # in this band */ | 198 | u8 group_channel; /* "representative" channel # in this band */ |
@@ -189,6 +214,9 @@ struct iwl3945_eeprom_temperature_corr { | |||
189 | u32 Te; | 214 | u32 Te; |
190 | } __attribute__ ((packed)); | 215 | } __attribute__ ((packed)); |
191 | 216 | ||
217 | /* | ||
218 | * EEPROM map | ||
219 | */ | ||
192 | struct iwl3945_eeprom { | 220 | struct iwl3945_eeprom { |
193 | u8 reserved0[16]; | 221 | u8 reserved0[16]; |
194 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ | 222 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ |
@@ -229,29 +257,67 @@ struct iwl3945_eeprom { | |||
229 | u8 reserved6[42]; | 257 | u8 reserved6[42]; |
230 | #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ | 258 | #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ |
231 | u8 sku_id[4]; /* abs.ofs: 192 */ | 259 | u8 sku_id[4]; /* abs.ofs: 192 */ |
260 | |||
261 | /* | ||
262 | * Per-channel regulatory data. | ||
263 | * | ||
264 | * Each channel that *might* be supported by 3945 or 4965 has a fixed location | ||
265 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory | ||
266 | * txpower (MSB). | ||
267 | * | ||
268 | * Entries immediately below are for 20 MHz channel width. FAT (40 MHz) | ||
269 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. | ||
270 | * | ||
271 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | ||
272 | */ | ||
232 | #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ | 273 | #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ |
233 | u16 band_1_count; /* abs.ofs: 196 */ | 274 | u16 band_1_count; /* abs.ofs: 196 */ |
234 | #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ | 275 | #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ |
235 | struct iwl3945_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */ | 276 | struct iwl3945_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */ |
277 | |||
278 | /* | ||
279 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, | ||
280 | * 5.0 GHz channels 7, 8, 11, 12, 16 | ||
281 | * (4915-5080MHz) (none of these is ever supported) | ||
282 | */ | ||
236 | #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ | 283 | #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ |
237 | u16 band_2_count; /* abs.ofs: 226 */ | 284 | u16 band_2_count; /* abs.ofs: 226 */ |
238 | #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ | 285 | #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ |
239 | struct iwl3945_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ | 286 | struct iwl3945_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ |
287 | |||
288 | /* | ||
289 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | ||
290 | * (5170-5320MHz) | ||
291 | */ | ||
240 | #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ | 292 | #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ |
241 | u16 band_3_count; /* abs.ofs: 254 */ | 293 | u16 band_3_count; /* abs.ofs: 254 */ |
242 | #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ | 294 | #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ |
243 | struct iwl3945_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ | 295 | struct iwl3945_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ |
296 | |||
297 | /* | ||
298 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | ||
299 | * (5500-5700MHz) | ||
300 | */ | ||
244 | #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ | 301 | #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ |
245 | u16 band_4_count; /* abs.ofs: 280 */ | 302 | u16 band_4_count; /* abs.ofs: 280 */ |
246 | #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ | 303 | #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ |
247 | struct iwl3945_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ | 304 | struct iwl3945_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ |
305 | |||
306 | /* | ||
307 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 | ||
308 | * (5725-5825MHz) | ||
309 | */ | ||
248 | #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ | 310 | #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ |
249 | u16 band_5_count; /* abs.ofs: 304 */ | 311 | u16 band_5_count; /* abs.ofs: 304 */ |
250 | #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ | 312 | #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ |
251 | struct iwl3945_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ | 313 | struct iwl3945_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ |
252 | 314 | ||
253 | u8 reserved9[194]; | 315 | u8 reserved9[194]; |
254 | 316 | ||
317 | |||
318 | /* | ||
319 | * 3945 Txpower calibration data. | ||
320 | */ | ||
255 | #define EEPROM_TXPOWER_CALIB_GROUP0 0x200 | 321 | #define EEPROM_TXPOWER_CALIB_GROUP0 0x200 |
256 | #define EEPROM_TXPOWER_CALIB_GROUP1 0x240 | 322 | #define EEPROM_TXPOWER_CALIB_GROUP1 0x240 |
257 | #define EEPROM_TXPOWER_CALIB_GROUP2 0x280 | 323 | #define EEPROM_TXPOWER_CALIB_GROUP2 0x280 |
@@ -261,12 +327,14 @@ struct iwl3945_eeprom { | |||
261 | struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS]; | 327 | struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS]; |
262 | /* abs.ofs: 512 */ | 328 | /* abs.ofs: 512 */ |
263 | #define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340 | 329 | #define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340 |
264 | struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ | 330 | struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ |
265 | u8 reserved16[172]; /* fill out to full 1024 byte block */ | 331 | u8 reserved16[172]; /* fill out to full 1024 byte block */ |
266 | } __attribute__ ((packed)); | 332 | } __attribute__ ((packed)); |
267 | 333 | ||
268 | #define IWL_EEPROM_IMAGE_SIZE 1024 | 334 | #define IWL_EEPROM_IMAGE_SIZE 1024 |
269 | 335 | ||
336 | /* End of EEPROM */ | ||
337 | |||
270 | 338 | ||
271 | #include "iwl-3945-commands.h" | 339 | #include "iwl-3945-commands.h" |
272 | 340 | ||