Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

Conflicts:

	drivers/infiniband/core/iwcm.c
	drivers/net/chelsio/cxgb2.c
	drivers/net/wireless/bcm43xx/bcm43xx_main.c
	drivers/net/wireless/prism54/islpci_eth.c
	drivers/usb/core/hub.h
	drivers/usb/input/hid-core.c
	net/core/netpoll.c

Fix up merge failures with Linus's head and fix new compilation failures.

Signed-Off-By: David Howells <dhowells@redhat.com>

1 files changed, 21 insertions, 7 deletions

diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_power.c b/drivers/net/wireless/bcm43xx/bcm43xx_power.c
index 6569da3a7a3..7e774f41095 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_power.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_power.c
@@ -153,8 +153,6 @@ int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
         int err, maxfreq;
         struct bcm43xx_coreinfo *old_core;
 
-        if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
-                return 0;
         old_core = bcm->current_core;
         err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
         if (err == -ENODEV)
@@ -162,11 +160,27 @@ int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
         if (err)
                 goto out;
 
-        maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1);
-        bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY,
-                        (maxfreq * 150 + 999999) / 1000000);
-        bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY,
-                        (maxfreq * 15 + 999999) / 1000000);
+        if (bcm->chip_id == 0x4321) {
+                if (bcm->chip_rev == 0)
+                        bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_CTL, 0x03A4);
+                if (bcm->chip_rev == 1)
+                        bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_CTL, 0x00A4);
+        }
+
+        if (bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL) {
+                if (bcm->current_core->rev >= 10) {
+                        /* Set Idle Power clock rate to 1Mhz */
+                        bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL,
+                                       (bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL)
+                                       & 0x0000FFFF) | 0x40000);
+                } else {
+                        maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1);
+                        bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY,
+                                       (maxfreq * 150 + 999999) / 1000000);
+                        bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY,
+                                       (maxfreq * 15 + 999999) / 1000000);
+                }
+        }
 
         err = bcm43xx_switch_core(bcm, old_core);
         assert(err == 0);