diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2010-01-29 18:12:19 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2010-02-01 15:40:05 -0500 |
commit | 28fd7daabfb35b7a0df2f7eaf460221e16dd2608 (patch) | |
tree | e24bf1b67bdc76d8666525014636e35297d2910c /drivers/net/wireless/b43 | |
parent | 991a0987d9e821df1790bbbc368cf36db0c678d3 (diff) |
b43: N-PHY: update general workarounds
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r-- | drivers/net/wireless/b43/phy_n.c | 215 | ||||
-rw-r--r-- | drivers/net/wireless/b43/phy_n.h | 4 |
2 files changed, 115 insertions, 104 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c index 8c39fb126d4..60e730a6f1d 100644 --- a/drivers/net/wireless/b43/phy_n.c +++ b/drivers/net/wireless/b43/phy_n.c | |||
@@ -246,110 +246,6 @@ static void b43_nphy_tables_init(struct b43_wldev *dev) | |||
246 | b43_nphy_rev3plus_tables_init(dev); | 246 | b43_nphy_rev3plus_tables_init(dev); |
247 | } | 247 | } |
248 | 248 | ||
249 | static void b43_nphy_workarounds(struct b43_wldev *dev) | ||
250 | { | ||
251 | struct b43_phy *phy = &dev->phy; | ||
252 | unsigned int i; | ||
253 | |||
254 | b43_phy_set(dev, B43_NPHY_IQFLIP, | ||
255 | B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); | ||
256 | if (1 /* FIXME band is 2.4GHz */) { | ||
257 | b43_phy_set(dev, B43_NPHY_CLASSCTL, | ||
258 | B43_NPHY_CLASSCTL_CCKEN); | ||
259 | } else { | ||
260 | b43_phy_mask(dev, B43_NPHY_CLASSCTL, | ||
261 | ~B43_NPHY_CLASSCTL_CCKEN); | ||
262 | } | ||
263 | b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); | ||
264 | b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8); | ||
265 | |||
266 | /* Fixup some tables */ | ||
267 | b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA); | ||
268 | b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA); | ||
269 | b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); | ||
270 | b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); | ||
271 | b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0); | ||
272 | b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0); | ||
273 | b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); | ||
274 | b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); | ||
275 | b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800); | ||
276 | b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800); | ||
277 | |||
278 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); | ||
279 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); | ||
280 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | ||
281 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | ||
282 | |||
283 | //TODO set RF sequence | ||
284 | |||
285 | /* Set narrowband clip threshold */ | ||
286 | b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66); | ||
287 | b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66); | ||
288 | |||
289 | /* Set wideband clip 2 threshold */ | ||
290 | b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, | ||
291 | ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, | ||
292 | 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT); | ||
293 | b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, | ||
294 | ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, | ||
295 | 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT); | ||
296 | |||
297 | /* Set Clip 2 detect */ | ||
298 | b43_phy_set(dev, B43_NPHY_C1_CGAINI, | ||
299 | B43_NPHY_C1_CGAINI_CL2DETECT); | ||
300 | b43_phy_set(dev, B43_NPHY_C2_CGAINI, | ||
301 | B43_NPHY_C2_CGAINI_CL2DETECT); | ||
302 | |||
303 | if (0 /*FIXME*/) { | ||
304 | /* Set dwell lengths */ | ||
305 | b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43); | ||
306 | b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43); | ||
307 | b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9); | ||
308 | b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9); | ||
309 | |||
310 | /* Set gain backoff */ | ||
311 | b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, | ||
312 | ~B43_NPHY_C1_CGAINI_GAINBKOFF, | ||
313 | 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT); | ||
314 | b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, | ||
315 | ~B43_NPHY_C2_CGAINI_GAINBKOFF, | ||
316 | 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT); | ||
317 | |||
318 | /* Set HPVGA2 index */ | ||
319 | b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, | ||
320 | ~B43_NPHY_C1_INITGAIN_HPVGA2, | ||
321 | 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); | ||
322 | b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, | ||
323 | ~B43_NPHY_C2_INITGAIN_HPVGA2, | ||
324 | 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); | ||
325 | |||
326 | //FIXME verify that the specs really mean to use autoinc here. | ||
327 | for (i = 0; i < 3; i++) | ||
328 | b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673); | ||
329 | } | ||
330 | |||
331 | /* Set minimum gain value */ | ||
332 | b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, | ||
333 | ~B43_NPHY_C1_MINGAIN, | ||
334 | 23 << B43_NPHY_C1_MINGAIN_SHIFT); | ||
335 | b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, | ||
336 | ~B43_NPHY_C2_MINGAIN, | ||
337 | 23 << B43_NPHY_C2_MINGAIN_SHIFT); | ||
338 | |||
339 | if (phy->rev < 2) { | ||
340 | b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, | ||
341 | ~B43_NPHY_SCRAM_SIGCTL_SCM); | ||
342 | } | ||
343 | |||
344 | /* Set phase track alpha and beta */ | ||
345 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); | ||
346 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); | ||
347 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); | ||
348 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); | ||
349 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); | ||
350 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); | ||
351 | } | ||
352 | |||
353 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ | 249 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ |
354 | static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) | 250 | static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) |
355 | { | 251 | { |
@@ -816,6 +712,117 @@ static void b43_nphy_stop_playback(struct b43_wldev *dev) | |||
816 | b43_nphy_stay_in_carrier_search(dev, 0); | 712 | b43_nphy_stay_in_carrier_search(dev, 0); |
817 | } | 713 | } |
818 | 714 | ||
715 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ | ||
716 | static void b43_nphy_workarounds(struct b43_wldev *dev) | ||
717 | { | ||
718 | struct ssb_bus *bus = dev->dev->bus; | ||
719 | struct b43_phy *phy = &dev->phy; | ||
720 | struct b43_phy_n *nphy = phy->n; | ||
721 | |||
722 | u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; | ||
723 | u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; | ||
724 | |||
725 | u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; | ||
726 | u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; | ||
727 | |||
728 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | ||
729 | b43_nphy_classifier(dev, 1, 0); | ||
730 | else | ||
731 | b43_nphy_classifier(dev, 1, 1); | ||
732 | |||
733 | if (nphy->hang_avoid) | ||
734 | b43_nphy_stay_in_carrier_search(dev, 1); | ||
735 | |||
736 | b43_phy_set(dev, B43_NPHY_IQFLIP, | ||
737 | B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); | ||
738 | |||
739 | if (dev->phy.rev >= 3) { | ||
740 | /* TODO */ | ||
741 | } else { | ||
742 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && | ||
743 | nphy->band5g_pwrgain) { | ||
744 | b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); | ||
745 | b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); | ||
746 | } else { | ||
747 | b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); | ||
748 | b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); | ||
749 | } | ||
750 | |||
751 | /* TODO: convert to b43_ntab_write? */ | ||
752 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000); | ||
753 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); | ||
754 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010); | ||
755 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); | ||
756 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002); | ||
757 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); | ||
758 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012); | ||
759 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); | ||
760 | |||
761 | if (dev->phy.rev < 2) { | ||
762 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008); | ||
763 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); | ||
764 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018); | ||
765 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); | ||
766 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007); | ||
767 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); | ||
768 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017); | ||
769 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); | ||
770 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006); | ||
771 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); | ||
772 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016); | ||
773 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); | ||
774 | } | ||
775 | |||
776 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); | ||
777 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); | ||
778 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | ||
779 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | ||
780 | |||
781 | if (bus->sprom.boardflags2_lo & 0x100 && | ||
782 | bus->boardinfo.type == 0x8B) { | ||
783 | delays1[0] = 0x1; | ||
784 | delays1[5] = 0x14; | ||
785 | } | ||
786 | /*TODO:b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);*/ | ||
787 | /*TODO:b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);*/ | ||
788 | |||
789 | /*TODO:b43_nphy_gain_crtl_workarounds(dev);*/ | ||
790 | |||
791 | if (dev->phy.rev < 2) { | ||
792 | if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) | ||
793 | ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/ | ||
794 | } else if (dev->phy.rev == 2) { | ||
795 | b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); | ||
796 | b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); | ||
797 | } | ||
798 | |||
799 | if (dev->phy.rev < 2) | ||
800 | b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, | ||
801 | ~B43_NPHY_SCRAM_SIGCTL_SCM); | ||
802 | |||
803 | /* Set phase track alpha and beta */ | ||
804 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); | ||
805 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); | ||
806 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); | ||
807 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); | ||
808 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); | ||
809 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); | ||
810 | |||
811 | b43_phy_mask(dev, B43_NPHY_PIL_DW1, | ||
812 | (u16)~B43_NPHY_PIL_DW_64QAM); | ||
813 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); | ||
814 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); | ||
815 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); | ||
816 | |||
817 | if (dev->phy.rev == 2) | ||
818 | b43_phy_set(dev, B43_NPHY_FINERX2_CGC, | ||
819 | B43_NPHY_FINERX2_CGC_DECGC); | ||
820 | } | ||
821 | |||
822 | if (nphy->hang_avoid) | ||
823 | b43_nphy_stay_in_carrier_search(dev, 0); | ||
824 | } | ||
825 | |||
819 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ | 826 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ |
820 | static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, | 827 | static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, |
821 | bool test) | 828 | bool test) |
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h index f5a27661f65..ae82f0fc209 100644 --- a/drivers/net/wireless/b43/phy_n.h +++ b/drivers/net/wireless/b43/phy_n.h | |||
@@ -976,6 +976,10 @@ struct b43_phy_n { | |||
976 | s32 preamble_override; | 976 | s32 preamble_override; |
977 | u32 bb_mult_save; | 977 | u32 bb_mult_save; |
978 | 978 | ||
979 | bool gain_boost; | ||
980 | bool elna_gain_config; | ||
981 | bool band5g_pwrgain; | ||
982 | |||
979 | u8 mphase_cal_phase_id; | 983 | u8 mphase_cal_phase_id; |
980 | u16 mphase_txcal_cmdidx; | 984 | u16 mphase_txcal_cmdidx; |
981 | u16 mphase_txcal_numcmds; | 985 | u16 mphase_txcal_numcmds; |