diff options
author | Sujith <Sujith.Manoharan@atheros.com> | 2009-03-30 05:58:25 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-04-22 16:54:30 -0400 |
commit | d8baa9392666d1c50ef42e9f6fbbb0cf536327b9 (patch) | |
tree | a70f7ef031e128defc2bc46dedb3ce1f15432d2a /drivers/net/wireless/ath9k/mac.c | |
parent | 6ed6a05e5c8061cdcd69a418c90c5f11979ce650 (diff) |
ath9k: Cleanup debug messages
Clean debug messages to use appropriate levels,
remove useless messages, and trim the number of
debug levels.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/mac.c')
-rw-r--r-- | drivers/net/wireless/ath9k/mac.c | 63 |
1 files changed, 37 insertions, 26 deletions
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c index e0a6dee4583..8ae4ec21667 100644 --- a/drivers/net/wireless/ath9k/mac.c +++ b/drivers/net/wireless/ath9k/mac.c | |||
@@ -49,7 +49,7 @@ bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) | |||
49 | 49 | ||
50 | bool ath9k_hw_txstart(struct ath_hw *ah, u32 q) | 50 | bool ath9k_hw_txstart(struct ath_hw *ah, u32 q) |
51 | { | 51 | { |
52 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); | 52 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q); |
53 | 53 | ||
54 | REG_WRITE(ah, AR_Q_TXE, 1 << q); | 54 | REG_WRITE(ah, AR_Q_TXE, 1 << q); |
55 | 55 | ||
@@ -110,13 +110,15 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) | |||
110 | u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; | 110 | u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; |
111 | 111 | ||
112 | if (q >= pCap->total_queues) { | 112 | if (q >= pCap->total_queues) { |
113 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); | 113 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, " |
114 | "invalid queue: %u\n", q); | ||
114 | return false; | 115 | return false; |
115 | } | 116 | } |
116 | 117 | ||
117 | qi = &ah->txq[q]; | 118 | qi = &ah->txq[q]; |
118 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 119 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
119 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); | 120 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, " |
121 | "inactive queue: %u\n", q); | ||
120 | return false; | 122 | return false; |
121 | } | 123 | } |
122 | 124 | ||
@@ -146,7 +148,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) | |||
146 | break; | 148 | break; |
147 | 149 | ||
148 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | 150 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, |
149 | "TSF have moved while trying to set " | 151 | "TSF has moved while trying to set " |
150 | "quiet time TSF: 0x%08x\n", tsfLow); | 152 | "quiet time TSF: 0x%08x\n", tsfLow); |
151 | } | 153 | } |
152 | 154 | ||
@@ -158,8 +160,8 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) | |||
158 | wait = wait_time; | 160 | wait = wait_time; |
159 | while (ath9k_hw_numtxpending(ah, q)) { | 161 | while (ath9k_hw_numtxpending(ah, q)) { |
160 | if ((--wait) == 0) { | 162 | if ((--wait) == 0) { |
161 | DPRINTF(ah->ah_sc, ATH_DBG_XMIT, | 163 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, |
162 | "Failed to stop Tx DMA in 100 " | 164 | "Failed to stop TX DMA in 100 " |
163 | "msec after killing last frame\n"); | 165 | "msec after killing last frame\n"); |
164 | break; | 166 | break; |
165 | } | 167 | } |
@@ -454,17 +456,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, | |||
454 | struct ath9k_tx_queue_info *qi; | 456 | struct ath9k_tx_queue_info *qi; |
455 | 457 | ||
456 | if (q >= pCap->total_queues) { | 458 | if (q >= pCap->total_queues) { |
457 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); | 459 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, " |
460 | "invalid queue: %u\n", q); | ||
458 | return false; | 461 | return false; |
459 | } | 462 | } |
460 | 463 | ||
461 | qi = &ah->txq[q]; | 464 | qi = &ah->txq[q]; |
462 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 465 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
463 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); | 466 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, " |
467 | "inactive queue: %u\n", q); | ||
464 | return false; | 468 | return false; |
465 | } | 469 | } |
466 | 470 | ||
467 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %p\n", qi); | 471 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); |
468 | 472 | ||
469 | qi->tqi_ver = qinfo->tqi_ver; | 473 | qi->tqi_ver = qinfo->tqi_ver; |
470 | qi->tqi_subtype = qinfo->tqi_subtype; | 474 | qi->tqi_subtype = qinfo->tqi_subtype; |
@@ -521,13 +525,15 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, | |||
521 | struct ath9k_tx_queue_info *qi; | 525 | struct ath9k_tx_queue_info *qi; |
522 | 526 | ||
523 | if (q >= pCap->total_queues) { | 527 | if (q >= pCap->total_queues) { |
524 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); | 528 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, " |
529 | "invalid queue: %u\n", q); | ||
525 | return false; | 530 | return false; |
526 | } | 531 | } |
527 | 532 | ||
528 | qi = &ah->txq[q]; | 533 | qi = &ah->txq[q]; |
529 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 534 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
530 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); | 535 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, " |
536 | "inactive queue: %u\n", q); | ||
531 | return false; | 537 | return false; |
532 | } | 538 | } |
533 | 539 | ||
@@ -575,22 +581,23 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, | |||
575 | ATH9K_TX_QUEUE_INACTIVE) | 581 | ATH9K_TX_QUEUE_INACTIVE) |
576 | break; | 582 | break; |
577 | if (q == pCap->total_queues) { | 583 | if (q == pCap->total_queues) { |
578 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | 584 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, |
579 | "no available tx queue\n"); | 585 | "No available TX queue\n"); |
580 | return -1; | 586 | return -1; |
581 | } | 587 | } |
582 | break; | 588 | break; |
583 | default: | 589 | default: |
584 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "bad tx queue type %u\n", type); | 590 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Invalid TX queue type: %u\n", |
591 | type); | ||
585 | return -1; | 592 | return -1; |
586 | } | 593 | } |
587 | 594 | ||
588 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); | 595 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); |
589 | 596 | ||
590 | qi = &ah->txq[q]; | 597 | qi = &ah->txq[q]; |
591 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { | 598 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { |
592 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | 599 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, |
593 | "tx queue %u already active\n", q); | 600 | "TX queue: %u already active\n", q); |
594 | return -1; | 601 | return -1; |
595 | } | 602 | } |
596 | memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); | 603 | memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); |
@@ -620,16 +627,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) | |||
620 | struct ath9k_tx_queue_info *qi; | 627 | struct ath9k_tx_queue_info *qi; |
621 | 628 | ||
622 | if (q >= pCap->total_queues) { | 629 | if (q >= pCap->total_queues) { |
623 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); | 630 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, " |
631 | "invalid queue: %u\n", q); | ||
624 | return false; | 632 | return false; |
625 | } | 633 | } |
626 | qi = &ah->txq[q]; | 634 | qi = &ah->txq[q]; |
627 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 635 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
628 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); | 636 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, " |
637 | "inactive queue: %u\n", q); | ||
629 | return false; | 638 | return false; |
630 | } | 639 | } |
631 | 640 | ||
632 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); | 641 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); |
633 | 642 | ||
634 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; | 643 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; |
635 | ah->txok_interrupt_mask &= ~(1 << q); | 644 | ah->txok_interrupt_mask &= ~(1 << q); |
@@ -650,17 +659,19 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) | |||
650 | u32 cwMin, chanCwMin, value; | 659 | u32 cwMin, chanCwMin, value; |
651 | 660 | ||
652 | if (q >= pCap->total_queues) { | 661 | if (q >= pCap->total_queues) { |
653 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); | 662 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, " |
663 | "invalid queue: %u\n", q); | ||
654 | return false; | 664 | return false; |
655 | } | 665 | } |
656 | 666 | ||
657 | qi = &ah->txq[q]; | 667 | qi = &ah->txq[q]; |
658 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 668 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
659 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); | 669 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, " |
670 | "inactive queue: %u\n", q); | ||
660 | return true; | 671 | return true; |
661 | } | 672 | } |
662 | 673 | ||
663 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "reset queue %u\n", q); | 674 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); |
664 | 675 | ||
665 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { | 676 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { |
666 | if (chan && IS_CHAN_B(chan)) | 677 | if (chan && IS_CHAN_B(chan)) |
@@ -894,7 +905,7 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) | |||
894 | 905 | ||
895 | reg = REG_READ(ah, AR_OBS_BUS_1); | 906 | reg = REG_READ(ah, AR_OBS_BUS_1); |
896 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | 907 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, |
897 | "rx failed to go idle in 10 ms RXSM=0x%x\n", reg); | 908 | "RX failed to go idle in 10 ms RXSM=0x%x\n", reg); |
898 | 909 | ||
899 | return false; | 910 | return false; |
900 | } | 911 | } |
@@ -949,8 +960,8 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah) | |||
949 | } | 960 | } |
950 | 961 | ||
951 | if (i == 0) { | 962 | if (i == 0) { |
952 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | 963 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, |
953 | "dma failed to stop in %d ms " | 964 | "DMA failed to stop in %d ms " |
954 | "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", | 965 | "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", |
955 | AH_RX_STOP_DMA_TIMEOUT / 1000, | 966 | AH_RX_STOP_DMA_TIMEOUT / 1000, |
956 | REG_READ(ah, AR_CR), | 967 | REG_READ(ah, AR_CR), |