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authorNick Kossifidis <mick@madwifi.org>2008-09-28 19:09:09 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-09-30 14:07:25 -0400
commit1bef016a5a2c52de45b332c8fa797958becde9bf (patch)
tree2389e6e4bdf8151286d56511f7c2f39bb33077b9 /drivers/net/wireless/ath5k/qcu.c
parent14be9947ef9843102b67d315c7483de112b5b2d7 (diff)
ath5k: Update registers and SREV ids v2
* Update registers * Update SREV values and add some PHY srevs * Prepare ath5k.h for newer radios etc Thanks to Atheros 's HAL source we now know for sure how many parts we have and what their SREV values are. We also have some updates on registers. Prepare ath5k for some major updates ;-) My previous mail had 2 more patches following (git log misusage), sorry for double posting ;-( Changes-Licensed-under: ISC Signed-Off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath5k/qcu.c')
-rw-r--r--drivers/net/wireless/ath5k/qcu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath5k/qcu.c b/drivers/net/wireless/ath5k/qcu.c
index 2e20f7816ca..01bf09176d2 100644
--- a/drivers/net/wireless/ath5k/qcu.c
+++ b/drivers/net/wireless/ath5k/qcu.c
@@ -375,7 +375,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
375 case AR5K_TX_QUEUE_BEACON: 375 case AR5K_TX_QUEUE_BEACON:
376 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 376 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
377 AR5K_QCU_MISC_FRSHED_DBA_GT | 377 AR5K_QCU_MISC_FRSHED_DBA_GT |
378 AR5K_QCU_MISC_CBREXP_BCN | 378 AR5K_QCU_MISC_CBREXP_BCN_DIS |
379 AR5K_QCU_MISC_BCN_ENABLE); 379 AR5K_QCU_MISC_BCN_ENABLE);
380 380
381 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 381 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
@@ -395,8 +395,8 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
395 case AR5K_TX_QUEUE_CAB: 395 case AR5K_TX_QUEUE_CAB:
396 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 396 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
397 AR5K_QCU_MISC_FRSHED_DBA_GT | 397 AR5K_QCU_MISC_FRSHED_DBA_GT |
398 AR5K_QCU_MISC_CBREXP | 398 AR5K_QCU_MISC_CBREXP_DIS |
399 AR5K_QCU_MISC_CBREXP_BCN); 399 AR5K_QCU_MISC_CBREXP_BCN_DIS);
400 400
401 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 401 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
402 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << 402 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
@@ -405,7 +405,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
405 405
406 case AR5K_TX_QUEUE_UAPSD: 406 case AR5K_TX_QUEUE_UAPSD:
407 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 407 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
408 AR5K_QCU_MISC_CBREXP); 408 AR5K_QCU_MISC_CBREXP_DIS);
409 break; 409 break;
410 410
411 case AR5K_TX_QUEUE_DATA: 411 case AR5K_TX_QUEUE_DATA: