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authorHaiying Wang <Haiying.Wang@freescale.com>2009-06-17 09:16:10 -0400
committerDavid S. Miller <davem@davemloft.net>2009-06-17 21:46:45 -0400
commitfb1001f3de1a8576b25d929502f1fe7865ff32dc (patch)
treeafb9115df813d278e7747ccfc6c138464fe92a23 /drivers/net/ucc_geth.h
parentf3a32500ba8f3ec9ee0c12836fcfd315f1256db4 (diff)
net/ucc_geth: Add SGMII support for UCC GETH driver
-- derived from reverted commit 047584ce94108012288554a5f84585d792cc7f8f -- reworked by Grant Likely to play nice with commit: "net: Rework ucc_geth driver to use of_mdio infrastructure" (0b9da337dca972e7a4144e298ec3adb8f244d4a4) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ucc_geth.h')
-rw-r--r--drivers/net/ucc_geth.h28
1 files changed, 27 insertions, 1 deletions
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index dca628a922b..1525bf51341 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. 2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
3 * 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com> 4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * 5 *
@@ -193,6 +193,31 @@ struct ucc_geth {
193#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */ 193#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */
194#define ENET_TBI_MII_TBICON 0x11 /* TBI control */ 194#define ENET_TBI_MII_TBICON 0x11 /* TBI control */
195 195
196/* TBI MDIO register bit fields*/
197#define TBISR_LSTATUS 0x0004
198#define TBICON_CLK_SELECT 0x0020
199#define TBIANA_ASYMMETRIC_PAUSE 0x0100
200#define TBIANA_SYMMETRIC_PAUSE 0x0080
201#define TBIANA_HALF_DUPLEX 0x0040
202#define TBIANA_FULL_DUPLEX 0x0020
203#define TBICR_PHY_RESET 0x8000
204#define TBICR_ANEG_ENABLE 0x1000
205#define TBICR_RESTART_ANEG 0x0200
206#define TBICR_FULL_DUPLEX 0x0100
207#define TBICR_SPEED1_SET 0x0040
208
209#define TBIANA_SETTINGS ( \
210 TBIANA_ASYMMETRIC_PAUSE \
211 | TBIANA_SYMMETRIC_PAUSE \
212 | TBIANA_FULL_DUPLEX \
213 )
214#define TBICR_SETTINGS ( \
215 TBICR_PHY_RESET \
216 | TBICR_ANEG_ENABLE \
217 | TBICR_FULL_DUPLEX \
218 | TBICR_SPEED1_SET \
219 )
220
196/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ 221/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
197#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control 222#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
198 Rx */ 223 Rx */
@@ -1100,6 +1125,7 @@ struct ucc_geth_info {
1100 u16 pausePeriod; 1125 u16 pausePeriod;
1101 u16 extensionField; 1126 u16 extensionField;
1102 struct device_node *phy_node; 1127 struct device_node *phy_node;
1128 struct device_node *tbi_node;
1103 u8 weightfactor[NUM_TX_QUEUES]; 1129 u8 weightfactor[NUM_TX_QUEUES];
1104 u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; 1130 u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1105 u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; 1131 u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];