[TG3]: Add new 5761 NVRAM decode routines

This patch adds a new 5761-specific NVRAM strapping decode routine.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 23 insertions, 2 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index d8e829f6fcb..88d08f3ede0 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -124,6 +124,7 @@
 #define   ASIC_REV_5906                  0x0c
 #define   ASIC_REV_USE_PROD_ID_REG       0x0f
 #define   ASIC_REV_5784                  0x5784
+#define   ASIC_REV_5761                  0x5761
 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX                0x70
 #define   CHIPREV_5700_BX                0x71
@@ -1463,6 +1464,22 @@
 #define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ    0x03000002
 #define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ     0x03000000
 #define  FLASH_5787VENDOR_MICRO_EEPROM_376KHZ    0x02000000
+#define  FLASH_5761VENDOR_ATMEL_MDB021D  0x00800003
+#define  FLASH_5761VENDOR_ATMEL_MDB041D  0x00800000
+#define  FLASH_5761VENDOR_ATMEL_MDB081D  0x00800002
+#define  FLASH_5761VENDOR_ATMEL_MDB161D  0x00800001
+#define  FLASH_5761VENDOR_ATMEL_ADB021D  0x00000003
+#define  FLASH_5761VENDOR_ATMEL_ADB041D  0x00000000
+#define  FLASH_5761VENDOR_ATMEL_ADB081D  0x00000002
+#define  FLASH_5761VENDOR_ATMEL_ADB161D  0x00000001
+#define  FLASH_5761VENDOR_ST_M_M45PE20   0x02800001
+#define  FLASH_5761VENDOR_ST_M_M45PE40   0x02800000
+#define  FLASH_5761VENDOR_ST_M_M45PE80   0x02800002
+#define  FLASH_5761VENDOR_ST_M_M45PE16   0x02800003
+#define  FLASH_5761VENDOR_ST_A_M45PE20   0x02000001
+#define  FLASH_5761VENDOR_ST_A_M45PE40   0x02000000
+#define  FLASH_5761VENDOR_ST_A_M45PE80   0x02000002
+#define  FLASH_5761VENDOR_ST_A_M45PE16   0x02000003
 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
 #define  FLASH_5752PAGE_SIZE_256         0x00000000
 #define  FLASH_5752PAGE_SIZE_512         0x10000000
@@ -1493,9 +1510,11 @@
 #define  ACCESS_ENABLE                   0x00000001
 #define  ACCESS_WR_ENABLE                0x00000002
 #define NVRAM_WRITE1                    0x00007028
-/* 0x702c --> 0x7400 unused */
+/* 0x702c unused */
+
+#define NVRAM_ADDR_LOCKOUT              0x00007030
+/* 0x7034 --> 0x7c00 unused */
 
-/* 0x7400 --> 0x7c00 unused */
 #define PCIE_TRANSACTION_CFG            0x00007c04
 #define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
 #define PCIE_TRANS_CFG_LOM               0x00000020
@@ -2269,6 +2288,8 @@ struct tg3 {
 #define TG3_FLG2_PHY_JITTER_BUG         0x20000000
 #define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
 #define TG3_FLG2_PHY_ADJUST_TRIM        0x80000000
+        u32                             tg3_flags3;
+#define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
 
         struct timer_list               timer;
         u16                             timer_counter;