sky2: pci power savings

Turn on special bits to save more power when device is shutdown.
Tested on a limited range of hardware, some of the bits are for hardware
that probably isn't even in production (like Yukon Supreme) and was ported
from the vendor driver.

Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>

1 files changed, 15 insertions, 1 deletions

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index d63106cd74b..1fa82bf029d 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -28,6 +28,11 @@ enum pci_dev_reg_1 {
         PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
         PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
         PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
+
+        PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit  9.. 8:       GPHY Link Trigger Timer */
+        PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
+        PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
+        PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
 };
 
 enum pci_dev_reg_2 {
@@ -45,7 +50,11 @@ enum pci_dev_reg_2 {
 
 /*      PCI_OUR_REG_4           32 bit  Our Register 4 (Yukon-ECU only) */
 enum pci_dev_reg_4 {
-                                        /* (Link Training & Status State Machine) */
+                                /* (Link Training & Status State Machine) */
+        P_PEX_LTSSM_STAT_MSK    = 0x7fL<<25,    /* Bit 31..25:  PEX LTSSM Mask */
+#define P_PEX_LTSSM_STAT(x)     ((x << 25) & P_PEX_LTSSM_STAT_MSK)
+        P_PEX_LTSSM_L1_STAT     = 0x34,
+        P_PEX_LTSSM_DET_STAT    = 0x01,
         P_TIMER_VALUE_MSK       = 0xffL<<16,    /* Bit 23..16:  Timer Value Mask */
                                         /* (Active State Power Management) */
         P_FORCE_ASPM_REQUEST    = 1<<15, /* Force ASPM Request (A1 only) */
@@ -454,6 +463,9 @@ enum yukon_ex_rev {
         CHIP_REV_YU_EX_A0    = 1,
         CHIP_REV_YU_EX_B0    = 2,
 };
+enum yukon_supr_rev {
+        CHIP_REV_YU_SU_A0    = 0,
+};
 
 
 /*      B2_Y2_CLK_GATE   8 bit  Clock Gating (Yukon-2 only) */
@@ -2059,7 +2071,9 @@ struct sky2_hw {
 #define SKY2_HW_NEW_LE          0x00000020      /* new LSOv2 format */
 #define SKY2_HW_AUTO_TX_SUM     0x00000040      /* new IP decode for Tx */
 #define SKY2_HW_ADV_POWER_CTL   0x00000080      /* additional PHY power regs */
+#define SKY2_HW_CLK_POWER       0x00000100      /* clock power management */
 
+        int                  pm_cap;
         u8                   chip_id;
         u8                   chip_rev;
         u8                   pmd_type;