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authorAnirban Chakraborty <anirban.chakraborty@qlogic.com>2011-04-01 10:28:05 -0400
committerDavid S. Miller <davem@davemloft.net>2011-04-06 15:47:11 -0400
commitb1fc6d3cfaff6fefd838b84532cb356f8a80da7b (patch)
treecb453fc6ff25043aac738d84a56a9fd65a8715eb /drivers/net/qlcnic/qlcnic.h
parentf848d6dd10e8e27d5dd61a8ab7174a7dde3a3db5 (diff)
qlcnic: Cleanup patch
1. Changed adapter structure to move away from embedding hardware and receive context structs and use pointers to those objects 2. Packed all the structs that interface with FW 3. Removed unused code and structs Signed-off-by: Anirban Chakraborty <anirban.chakraborty@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/qlcnic/qlcnic.h')
-rw-r--r--drivers/net/qlcnic/qlcnic.h126
1 files changed, 38 insertions, 88 deletions
diff --git a/drivers/net/qlcnic/qlcnic.h b/drivers/net/qlcnic/qlcnic.h
index dc44564ef6f..15d950a4f46 100644
--- a/drivers/net/qlcnic/qlcnic.h
+++ b/drivers/net/qlcnic/qlcnic.h
@@ -93,8 +93,6 @@
93#define TX_IP_PKT 0x04 93#define TX_IP_PKT 0x04
94#define TX_TCP_LSO 0x05 94#define TX_TCP_LSO 0x05
95#define TX_TCP_LSO6 0x06 95#define TX_TCP_LSO6 0x06
96#define TX_IPSEC 0x07
97#define TX_IPSEC_CMD 0x0a
98#define TX_TCPV6_PKT 0x0b 96#define TX_TCPV6_PKT 0x0b
99#define TX_UDPV6_PKT 0x0c 97#define TX_UDPV6_PKT 0x0c
100 98
@@ -200,7 +198,7 @@ struct rcv_desc {
200 __le16 reserved; 198 __le16 reserved;
201 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 199 __le32 buffer_length; /* allocated buffer length (usually 2K) */
202 __le64 addr_buffer; 200 __le64 addr_buffer;
203}; 201} __packed;
204 202
205/* opcode field in status_desc */ 203/* opcode field in status_desc */
206#define QLCNIC_SYN_OFFLOAD 0x03 204#define QLCNIC_SYN_OFFLOAD 0x03
@@ -365,12 +363,6 @@ struct qlcnic_skb_frag {
365 u64 length; 363 u64 length;
366}; 364};
367 365
368struct qlcnic_recv_crb {
369 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
370 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
371 u32 sw_int_mask[NUM_STS_DESC_RINGS];
372};
373
374/* Following defines are for the state of the buffers */ 366/* Following defines are for the state of the buffers */
375#define QLCNIC_BUFFER_FREE 0 367#define QLCNIC_BUFFER_FREE 0
376#define QLCNIC_BUFFER_BUSY 1 368#define QLCNIC_BUFFER_BUSY 1
@@ -387,10 +379,10 @@ struct qlcnic_cmd_buffer {
387 379
388/* In rx_buffer, we do not need multiple fragments as is a single buffer */ 380/* In rx_buffer, we do not need multiple fragments as is a single buffer */
389struct qlcnic_rx_buffer { 381struct qlcnic_rx_buffer {
390 struct list_head list; 382 u16 ref_handle;
391 struct sk_buff *skb; 383 struct sk_buff *skb;
384 struct list_head list;
392 u64 dma; 385 u64 dma;
393 u16 ref_handle;
394}; 386};
395 387
396/* Board types */ 388/* Board types */
@@ -494,12 +486,12 @@ struct qlcnic_host_tx_ring {
494 * present elsewhere. 486 * present elsewhere.
495 */ 487 */
496struct qlcnic_recv_context { 488struct qlcnic_recv_context {
489 struct qlcnic_host_rds_ring *rds_rings;
490 struct qlcnic_host_sds_ring *sds_rings;
497 u32 state; 491 u32 state;
498 u16 context_id; 492 u16 context_id;
499 u16 virt_port; 493 u16 virt_port;
500 494
501 struct qlcnic_host_rds_ring *rds_rings;
502 struct qlcnic_host_sds_ring *sds_rings;
503}; 495};
504 496
505/* HW context creation */ 497/* HW context creation */
@@ -538,9 +530,6 @@ struct qlcnic_recv_context {
538#define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 530#define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
539#define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 531#define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
540#define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a 532#define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
541#define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
542#define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
543#define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
544#define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 533#define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
545#define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 534#define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
546#define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 535#define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
@@ -549,17 +538,11 @@ struct qlcnic_recv_context {
549#define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 538#define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
550#define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 539#define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
551#define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 540#define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
552#define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
553#define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
554#define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
555#define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
556#define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
557#define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f 541#define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
558 542
559#define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 543#define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
560#define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 544#define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
561#define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 545#define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
562#define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
563#define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 546#define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
564#define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 547#define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
565#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 548#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
@@ -597,14 +580,14 @@ struct qlcnic_hostrq_sds_ring {
597 __le32 ring_size; /* Ring entries */ 580 __le32 ring_size; /* Ring entries */
598 __le16 msi_index; 581 __le16 msi_index;
599 __le16 rsvd; /* Padding */ 582 __le16 rsvd; /* Padding */
600}; 583} __packed;
601 584
602struct qlcnic_hostrq_rds_ring { 585struct qlcnic_hostrq_rds_ring {
603 __le64 host_phys_addr; /* Ring base addr */ 586 __le64 host_phys_addr; /* Ring base addr */
604 __le64 buff_size; /* Packet buffer size */ 587 __le64 buff_size; /* Packet buffer size */
605 __le32 ring_size; /* Ring entries */ 588 __le32 ring_size; /* Ring entries */
606 __le32 ring_kind; /* Class of ring */ 589 __le32 ring_kind; /* Class of ring */
607}; 590} __packed;
608 591
609struct qlcnic_hostrq_rx_ctx { 592struct qlcnic_hostrq_rx_ctx {
610 __le64 host_rsp_dma_addr; /* Response dma'd here */ 593 __le64 host_rsp_dma_addr; /* Response dma'd here */
@@ -625,17 +608,17 @@ struct qlcnic_hostrq_rx_ctx {
625 - N hostrq_rds_rings 608 - N hostrq_rds_rings
626 - N hostrq_sds_rings */ 609 - N hostrq_sds_rings */
627 char data[0]; 610 char data[0];
628}; 611} __packed;
629 612
630struct qlcnic_cardrsp_rds_ring{ 613struct qlcnic_cardrsp_rds_ring{
631 __le32 host_producer_crb; /* Crb to use */ 614 __le32 host_producer_crb; /* Crb to use */
632 __le32 rsvd1; /* Padding */ 615 __le32 rsvd1; /* Padding */
633}; 616} __packed;
634 617
635struct qlcnic_cardrsp_sds_ring { 618struct qlcnic_cardrsp_sds_ring {
636 __le32 host_consumer_crb; /* Crb to use */ 619 __le32 host_consumer_crb; /* Crb to use */
637 __le32 interrupt_crb; /* Crb to use */ 620 __le32 interrupt_crb; /* Crb to use */
638}; 621} __packed;
639 622
640struct qlcnic_cardrsp_rx_ctx { 623struct qlcnic_cardrsp_rx_ctx {
641 /* These ring offsets are relative to data[0] below */ 624 /* These ring offsets are relative to data[0] below */
@@ -654,7 +637,7 @@ struct qlcnic_cardrsp_rx_ctx {
654 - N cardrsp_rds_rings 637 - N cardrsp_rds_rings
655 - N cardrs_sds_rings */ 638 - N cardrs_sds_rings */
656 char data[0]; 639 char data[0];
657}; 640} __packed;
658 641
659#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 642#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
660 (sizeof(HOSTRQ_RX) + \ 643 (sizeof(HOSTRQ_RX) + \
@@ -674,7 +657,7 @@ struct qlcnic_hostrq_cds_ring {
674 __le64 host_phys_addr; /* Ring base addr */ 657 __le64 host_phys_addr; /* Ring base addr */
675 __le32 ring_size; /* Ring entries */ 658 __le32 ring_size; /* Ring entries */
676 __le32 rsvd; /* Padding */ 659 __le32 rsvd; /* Padding */
677}; 660} __packed;
678 661
679struct qlcnic_hostrq_tx_ctx { 662struct qlcnic_hostrq_tx_ctx {
680 __le64 host_rsp_dma_addr; /* Response dma'd here */ 663 __le64 host_rsp_dma_addr; /* Response dma'd here */
@@ -689,12 +672,12 @@ struct qlcnic_hostrq_tx_ctx {
689 __le16 rsvd3; /* Padding */ 672 __le16 rsvd3; /* Padding */
690 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ 673 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
691 u8 reserved[128]; /* future expansion */ 674 u8 reserved[128]; /* future expansion */
692}; 675} __packed;
693 676
694struct qlcnic_cardrsp_cds_ring { 677struct qlcnic_cardrsp_cds_ring {
695 __le32 host_producer_crb; /* Crb to use */ 678 __le32 host_producer_crb; /* Crb to use */
696 __le32 interrupt_crb; /* Crb to use */ 679 __le32 interrupt_crb; /* Crb to use */
697}; 680} __packed;
698 681
699struct qlcnic_cardrsp_tx_ctx { 682struct qlcnic_cardrsp_tx_ctx {
700 __le32 host_ctx_state; /* Starting state */ 683 __le32 host_ctx_state; /* Starting state */
@@ -703,7 +686,7 @@ struct qlcnic_cardrsp_tx_ctx {
703 u8 virt_port; /* Virtual/Logical id of port */ 686 u8 virt_port; /* Virtual/Logical id of port */
704 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ 687 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
705 u8 reserved[128]; /* future expansion */ 688 u8 reserved[128]; /* future expansion */
706}; 689} __packed;
707 690
708#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 691#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
709#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 692#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
@@ -782,50 +765,20 @@ struct qlcnic_nic_intr_coalesce {
782/* 765/*
783 * Driver --> Firmware 766 * Driver --> Firmware
784 */ 767 */
785#define QLCNIC_H2C_OPCODE_START 0 768#define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
786#define QLCNIC_H2C_OPCODE_CONFIG_RSS 1 769#define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
787#define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2 770#define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
788#define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 771#define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
789#define QLCNIC_H2C_OPCODE_CONFIG_LED 4 772#define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
790#define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 773#define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
791#define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6 774#define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
792#define QLCNIC_H2C_OPCODE_LRO_REQUEST 7 775#define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
793#define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8 776#define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
794#define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
795#define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
796#define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
797#define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
798#define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
799#define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
800#define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
801#define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
802#define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
803#define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
804#define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
805#define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
806#define QLCNIC_C2C_OPCODE 22
807#define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
808#define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
809#define QLCNIC_H2C_OPCODE_LAST 25
810/* 777/*
811 * Firmware --> Driver 778 * Firmware --> Driver
812 */ 779 */
813 780
814#define QLCNIC_C2H_OPCODE_START 128
815#define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
816#define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
817#define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
818#define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
819#define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
820#define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
821#define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
822#define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
823#define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
824#define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
825#define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
826#define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
827#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 781#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
828#define QLCNIC_C2H_OPCODE_LAST 142
829 782
830#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 783#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
831#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 784#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
@@ -894,7 +847,7 @@ struct qlcnic_nic_req {
894 __le64 qhdr; 847 __le64 qhdr;
895 __le64 req_hdr; 848 __le64 req_hdr;
896 __le64 words[6]; 849 __le64 words[6];
897}; 850} __packed;
898 851
899struct qlcnic_mac_req { 852struct qlcnic_mac_req {
900 u8 op; 853 u8 op;
@@ -905,7 +858,7 @@ struct qlcnic_mac_req {
905struct qlcnic_vlan_req { 858struct qlcnic_vlan_req {
906 __le16 vlan_id; 859 __le16 vlan_id;
907 __le16 rsvd[3]; 860 __le16 rsvd[3];
908}; 861} __packed;
909 862
910struct qlcnic_ipaddr { 863struct qlcnic_ipaddr {
911 __be32 ipv4; 864 __be32 ipv4;
@@ -964,14 +917,14 @@ struct qlcnic_filter_hash {
964}; 917};
965 918
966struct qlcnic_adapter { 919struct qlcnic_adapter {
967 struct qlcnic_hardware_context ahw; 920 struct qlcnic_hardware_context *ahw;
968 921 struct qlcnic_recv_context *recv_ctx;
922 struct qlcnic_host_tx_ring *tx_ring;
969 struct net_device *netdev; 923 struct net_device *netdev;
970 struct pci_dev *pdev; 924 struct pci_dev *pdev;
971 struct list_head mac_list;
972 925
973 spinlock_t tx_clean_lock; 926 unsigned long state;
974 spinlock_t mac_learn_lock; 927 u32 flags;
975 928
976 u16 num_txd; 929 u16 num_txd;
977 u16 num_rxd; 930 u16 num_rxd;
@@ -989,7 +942,6 @@ struct qlcnic_adapter {
989 942
990 u8 mc_enabled; 943 u8 mc_enabled;
991 u8 max_mc_count; 944 u8 max_mc_count;
992 u8 rss_supported;
993 u8 fw_wait_cnt; 945 u8 fw_wait_cnt;
994 u8 fw_fail_cnt; 946 u8 fw_fail_cnt;
995 u8 tx_timeo_cnt; 947 u8 tx_timeo_cnt;
@@ -1014,7 +966,6 @@ struct qlcnic_adapter {
1014 966
1015 u32 fw_hal_version; 967 u32 fw_hal_version;
1016 u32 capabilities; 968 u32 capabilities;
1017 u32 flags;
1018 u32 irq; 969 u32 irq;
1019 u32 temp; 970 u32 temp;
1020 971
@@ -1039,9 +990,7 @@ struct qlcnic_adapter {
1039 struct qlcnic_nic_template *nic_ops; 990 struct qlcnic_nic_template *nic_ops;
1040 991
1041 struct qlcnic_adapter_stats stats; 992 struct qlcnic_adapter_stats stats;
1042 993 struct list_head mac_list;
1043 struct qlcnic_recv_context recv_ctx;
1044 struct qlcnic_host_tx_ring *tx_ring;
1045 994
1046 void __iomem *tgt_mask_reg; 995 void __iomem *tgt_mask_reg;
1047 void __iomem *tgt_status_reg; 996 void __iomem *tgt_status_reg;
@@ -1056,7 +1005,8 @@ struct qlcnic_adapter {
1056 1005
1057 struct qlcnic_filter_hash fhash; 1006 struct qlcnic_filter_hash fhash;
1058 1007
1059 unsigned long state; 1008 spinlock_t tx_clean_lock;
1009 spinlock_t mac_learn_lock;
1060 __le32 file_prd_off; /*File fw product offset*/ 1010 __le32 file_prd_off; /*File fw product offset*/
1061 u32 fw_version; 1011 u32 fw_version;
1062 const struct firmware *fw; 1012 const struct firmware *fw;
@@ -1078,7 +1028,7 @@ struct qlcnic_info {
1078 __le16 min_tx_bw; 1028 __le16 min_tx_bw;
1079 __le16 max_tx_bw; 1029 __le16 max_tx_bw;
1080 u8 reserved2[104]; 1030 u8 reserved2[104];
1081}; 1031} __packed;
1082 1032
1083struct qlcnic_pci_info { 1033struct qlcnic_pci_info {
1084 __le16 id; /* pci function id */ 1034 __le16 id; /* pci function id */
@@ -1092,7 +1042,7 @@ struct qlcnic_pci_info {
1092 1042
1093 u8 mac[ETH_ALEN]; 1043 u8 mac[ETH_ALEN];
1094 u8 reserved2[106]; 1044 u8 reserved2[106];
1095}; 1045} __packed;
1096 1046
1097struct qlcnic_npar_info { 1047struct qlcnic_npar_info {
1098 u16 pvid; 1048 u16 pvid;
@@ -1209,7 +1159,7 @@ struct __qlcnic_esw_statistics {
1209 __le64 local_frames; 1159 __le64 local_frames;
1210 __le64 numbytes; 1160 __le64 numbytes;
1211 __le64 rsvd[3]; 1161 __le64 rsvd[3];
1212}; 1162} __packed;
1213 1163
1214struct qlcnic_esw_statistics { 1164struct qlcnic_esw_statistics {
1215 struct __qlcnic_esw_statistics rx; 1165 struct __qlcnic_esw_statistics rx;
@@ -1293,7 +1243,7 @@ void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1293 1243
1294int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); 1244int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1295void qlcnic_watchdog_task(struct work_struct *work); 1245void qlcnic_watchdog_task(struct work_struct *work);
1296void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid, 1246void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1297 struct qlcnic_host_rds_ring *rds_ring); 1247 struct qlcnic_host_rds_ring *rds_ring);
1298int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); 1248int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1299void qlcnic_set_multi(struct net_device *netdev); 1249void qlcnic_set_multi(struct net_device *netdev);