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authorDhananjay Phadke <dhananjay@netxen.com>2009-02-17 23:26:44 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-17 23:26:44 -0500
commitd8313ce0f148e648d4e515db5d2c65bbd44fe29e (patch)
tree9c94c439f7d4763d16a4520a1ce7c0f016608bab /drivers/net/netxen/netxen_nic_hw.c
parentef38fa77786584c630f5da6696111a6a558c7f23 (diff)
netxen: fix sparse warnings
Fix following sparse warnings (multiple instances) warning: restricted degrades to integer warning: cast to restricted type warning: incorrect type in argument 3 (different signedness) warning: context imbalance in 'netxen_nic_hw_write_wx_2M' - different lock contexts for basic block Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/netxen/netxen_nic_hw.c')
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c179
1 files changed, 47 insertions, 132 deletions
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 821cff68b3f..81f55e1a34d 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -936,13 +936,12 @@ netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
936 u32 win_read; 936 u32 win_read;
937 937
938 adapter->crb_win = CRB_HI(*off); 938 adapter->crb_win = CRB_HI(*off);
939 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M + 939 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
940 adapter->ahw.pci_base0));
941 /* 940 /*
942 * Read back value to make sure write has gone through before trying 941 * Read back value to make sure write has gone through before trying
943 * to use it. 942 * to use it.
944 */ 943 */
945 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0)); 944 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
946 if (win_read != adapter->crb_win) { 945 if (win_read != adapter->crb_win) {
947 printk(KERN_ERR "%s: Written crbwin (0x%x) != " 946 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
948 "Read crbwin (0x%x), off=0x%lx\n", 947 "Read crbwin (0x%x), off=0x%lx\n",
@@ -992,6 +991,8 @@ netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
992{ 991{
993 void __iomem *addr; 992 void __iomem *addr;
994 993
994 BUG_ON(len != 4);
995
995 if (ADDR_IN_WINDOW1(off)) { 996 if (ADDR_IN_WINDOW1(off)) {
996 addr = NETXEN_CRB_NORMALIZE(adapter, off); 997 addr = NETXEN_CRB_NORMALIZE(adapter, off);
997 } else { /* Window 0 */ 998 } else { /* Window 0 */
@@ -999,37 +1000,13 @@ netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
999 netxen_nic_pci_change_crbwindow_128M(adapter, 0); 1000 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1000 } 1001 }
1001 1002
1002 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
1003 " data %llx len %d\n",
1004 pci_base(adapter, off), off, addr,
1005 *(unsigned long long *)data, len);
1006 if (!addr) { 1003 if (!addr) {
1007 netxen_nic_pci_change_crbwindow_128M(adapter, 1); 1004 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1008 return 1; 1005 return 1;
1009 } 1006 }
1010 1007
1011 switch (len) { 1008 writel(*(u32 *) data, addr);
1012 case 1:
1013 writeb(*(u8 *) data, addr);
1014 break;
1015 case 2:
1016 writew(*(u16 *) data, addr);
1017 break;
1018 case 4:
1019 writel(*(u32 *) data, addr);
1020 break;
1021 case 8:
1022 writeq(*(u64 *) data, addr);
1023 break;
1024 default:
1025 DPRINTK(INFO,
1026 "writing data %lx to offset %llx, num words=%d\n",
1027 *(unsigned long *)data, off, (len >> 3));
1028 1009
1029 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
1030 (len >> 3));
1031 break;
1032 }
1033 if (!ADDR_IN_WINDOW1(off)) 1010 if (!ADDR_IN_WINDOW1(off))
1034 netxen_nic_pci_change_crbwindow_128M(adapter, 1); 1011 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1035 1012
@@ -1042,6 +1019,8 @@ netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1042{ 1019{
1043 void __iomem *addr; 1020 void __iomem *addr;
1044 1021
1022 BUG_ON(len != 4);
1023
1045 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ 1024 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1046 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1025 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1047 } else { /* Window 0 */ 1026 } else { /* Window 0 */
@@ -1049,31 +1028,12 @@ netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1049 netxen_nic_pci_change_crbwindow_128M(adapter, 0); 1028 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1050 } 1029 }
1051 1030
1052 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
1053 pci_base(adapter, off), off, addr);
1054 if (!addr) { 1031 if (!addr) {
1055 netxen_nic_pci_change_crbwindow_128M(adapter, 1); 1032 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1056 return 1; 1033 return 1;
1057 } 1034 }
1058 switch (len) { 1035
1059 case 1: 1036 *(u32 *)data = readl(addr);
1060 *(u8 *) data = readb(addr);
1061 break;
1062 case 2:
1063 *(u16 *) data = readw(addr);
1064 break;
1065 case 4:
1066 *(u32 *) data = readl(addr);
1067 break;
1068 case 8:
1069 *(u64 *) data = readq(addr);
1070 break;
1071 default:
1072 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1073 (len >> 3));
1074 break;
1075 }
1076 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1077 1037
1078 if (!ADDR_IN_WINDOW1(off)) 1038 if (!ADDR_IN_WINDOW1(off))
1079 netxen_nic_pci_change_crbwindow_128M(adapter, 1); 1039 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
@@ -1088,6 +1048,8 @@ netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1088 unsigned long flags = 0; 1048 unsigned long flags = 0;
1089 int rv; 1049 int rv;
1090 1050
1051 BUG_ON(len != 4);
1052
1091 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len); 1053 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1092 1054
1093 if (rv == -1) { 1055 if (rv == -1) {
@@ -1101,34 +1063,12 @@ netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1101 write_lock_irqsave(&adapter->adapter_lock, flags); 1063 write_lock_irqsave(&adapter->adapter_lock, flags);
1102 crb_win_lock(adapter); 1064 crb_win_lock(adapter);
1103 netxen_nic_pci_set_crbwindow_2M(adapter, &off); 1065 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1104 } 1066 writel(*(uint32_t *)data, (void __iomem *)off);
1105
1106 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1107 *(unsigned long *)data, off, len);
1108
1109 switch (len) {
1110 case 1:
1111 writeb(*(uint8_t *)data, (void *)off);
1112 break;
1113 case 2:
1114 writew(*(uint16_t *)data, (void *)off);
1115 break;
1116 case 4:
1117 writel(*(uint32_t *)data, (void *)off);
1118 break;
1119 case 8:
1120 writeq(*(uint64_t *)data, (void *)off);
1121 break;
1122 default:
1123 DPRINTK(1, INFO,
1124 "writing data %lx to offset %llx, num words=%d\n",
1125 *(unsigned long *)data, off, (len>>3));
1126 break;
1127 }
1128 if (rv == 1) {
1129 crb_win_unlock(adapter); 1067 crb_win_unlock(adapter);
1130 write_unlock_irqrestore(&adapter->adapter_lock, flags); 1068 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1131 } 1069 } else
1070 writel(*(uint32_t *)data, (void __iomem *)off);
1071
1132 1072
1133 return 0; 1073 return 0;
1134} 1074}
@@ -1140,6 +1080,8 @@ netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1140 unsigned long flags = 0; 1080 unsigned long flags = 0;
1141 int rv; 1081 int rv;
1142 1082
1083 BUG_ON(len != 4);
1084
1143 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len); 1085 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1144 1086
1145 if (rv == -1) { 1087 if (rv == -1) {
@@ -1153,33 +1095,11 @@ netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1153 write_lock_irqsave(&adapter->adapter_lock, flags); 1095 write_lock_irqsave(&adapter->adapter_lock, flags);
1154 crb_win_lock(adapter); 1096 crb_win_lock(adapter);
1155 netxen_nic_pci_set_crbwindow_2M(adapter, &off); 1097 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1156 } 1098 *(uint32_t *)data = readl((void __iomem *)off);
1157
1158 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1159
1160 switch (len) {
1161 case 1:
1162 *(uint8_t *)data = readb((void *)off);
1163 break;
1164 case 2:
1165 *(uint16_t *)data = readw((void *)off);
1166 break;
1167 case 4:
1168 *(uint32_t *)data = readl((void *)off);
1169 break;
1170 case 8:
1171 *(uint64_t *)data = readq((void *)off);
1172 break;
1173 default:
1174 break;
1175 }
1176
1177 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
1178
1179 if (rv == 1) {
1180 crb_win_unlock(adapter); 1099 crb_win_unlock(adapter);
1181 write_unlock_irqrestore(&adapter->adapter_lock, flags); 1100 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1182 } 1101 } else
1102 *(uint32_t *)data = readl((void __iomem *)off);
1183 1103
1184 return 0; 1104 return 0;
1185} 1105}
@@ -1441,10 +1361,9 @@ static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1441 u64 off, void *data, int size) 1361 u64 off, void *data, int size)
1442{ 1362{
1443 unsigned long flags; 1363 unsigned long flags;
1444 void *addr; 1364 void __iomem *addr, *mem_ptr = NULL;
1445 int ret = 0; 1365 int ret = 0;
1446 u64 start; 1366 u64 start;
1447 uint8_t *mem_ptr = NULL;
1448 unsigned long mem_base; 1367 unsigned long mem_base;
1449 unsigned long mem_page; 1368 unsigned long mem_page;
1450 1369
@@ -1464,7 +1383,7 @@ static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1464 return -1; 1383 return -1;
1465 } 1384 }
1466 1385
1467 addr = (void *)(pci_base_offset(adapter, start)); 1386 addr = pci_base_offset(adapter, start);
1468 if (!addr) { 1387 if (!addr) {
1469 write_unlock_irqrestore(&adapter->adapter_lock, flags); 1388 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1470 mem_base = pci_resource_start(adapter->pdev, 0); 1389 mem_base = pci_resource_start(adapter->pdev, 0);
@@ -1503,7 +1422,6 @@ static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1503 break; 1422 break;
1504 } 1423 }
1505 write_unlock_irqrestore(&adapter->adapter_lock, flags); 1424 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1506 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1507 1425
1508 if (mem_ptr) 1426 if (mem_ptr)
1509 iounmap(mem_ptr); 1427 iounmap(mem_ptr);
@@ -1515,10 +1433,9 @@ netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1515 void *data, int size) 1433 void *data, int size)
1516{ 1434{
1517 unsigned long flags; 1435 unsigned long flags;
1518 void *addr; 1436 void __iomem *addr, *mem_ptr = NULL;
1519 int ret = 0; 1437 int ret = 0;
1520 u64 start; 1438 u64 start;
1521 uint8_t *mem_ptr = NULL;
1522 unsigned long mem_base; 1439 unsigned long mem_base;
1523 unsigned long mem_page; 1440 unsigned long mem_page;
1524 1441
@@ -1538,7 +1455,7 @@ netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1538 return -1; 1455 return -1;
1539 } 1456 }
1540 1457
1541 addr = (void *)(pci_base_offset(adapter, start)); 1458 addr = pci_base_offset(adapter, start);
1542 if (!addr) { 1459 if (!addr) {
1543 write_unlock_irqrestore(&adapter->adapter_lock, flags); 1460 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1544 mem_base = pci_resource_start(adapter->pdev, 0); 1461 mem_base = pci_resource_start(adapter->pdev, 0);
@@ -1575,8 +1492,6 @@ netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1575 break; 1492 break;
1576 } 1493 }
1577 write_unlock_irqrestore(&adapter->adapter_lock, flags); 1494 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1578 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1579 *(unsigned long long *)data, start);
1580 if (mem_ptr) 1495 if (mem_ptr)
1581 iounmap(mem_ptr); 1496 iounmap(mem_ptr);
1582 return ret; 1497 return ret;
@@ -1588,10 +1503,11 @@ int
1588netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, 1503netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1589 u64 off, void *data, int size) 1504 u64 off, void *data, int size)
1590{ 1505{
1591 unsigned long flags, mem_crb; 1506 unsigned long flags;
1592 int i, j, ret = 0, loop, sz[2], off0; 1507 int i, j, ret = 0, loop, sz[2], off0;
1593 uint32_t temp; 1508 uint32_t temp;
1594 uint64_t off8, tmpw, word[2] = {0, 0}; 1509 uint64_t off8, tmpw, word[2] = {0, 0};
1510 void __iomem *mem_crb;
1595 1511
1596 /* 1512 /*
1597 * If not MN, go check for MS or invalid. 1513 * If not MN, go check for MS or invalid.
@@ -1605,7 +1521,7 @@ netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1605 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1521 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1606 sz[1] = size - sz[0]; 1522 sz[1] = size - sz[0];
1607 loop = ((off0 + size - 1) >> 3) + 1; 1523 loop = ((off0 + size - 1) >> 3) + 1;
1608 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET); 1524 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1609 1525
1610 if ((size != 8) || (off0 != 0)) { 1526 if ((size != 8) || (off0 != 0)) {
1611 for (i = 0; i < loop; i++) { 1527 for (i = 0; i < loop; i++) {
@@ -1643,21 +1559,21 @@ netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1643 1559
1644 for (i = 0; i < loop; i++) { 1560 for (i = 0; i < loop; i++) {
1645 writel((uint32_t)(off8 + (i << 3)), 1561 writel((uint32_t)(off8 + (i << 3)),
1646 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO)); 1562 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1647 writel(0, 1563 writel(0,
1648 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI)); 1564 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1649 writel(word[i] & 0xffffffff, 1565 writel(word[i] & 0xffffffff,
1650 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO)); 1566 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1651 writel((word[i] >> 32) & 0xffffffff, 1567 writel((word[i] >> 32) & 0xffffffff,
1652 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI)); 1568 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1653 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, 1569 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1654 (void *)(mem_crb+MIU_TEST_AGT_CTRL)); 1570 (mem_crb+MIU_TEST_AGT_CTRL));
1655 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, 1571 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1656 (void *)(mem_crb+MIU_TEST_AGT_CTRL)); 1572 (mem_crb+MIU_TEST_AGT_CTRL));
1657 1573
1658 for (j = 0; j < MAX_CTL_CHECK; j++) { 1574 for (j = 0; j < MAX_CTL_CHECK; j++) {
1659 temp = readl( 1575 temp = readl(
1660 (void *)(mem_crb+MIU_TEST_AGT_CTRL)); 1576 (mem_crb+MIU_TEST_AGT_CTRL));
1661 if ((temp & MIU_TA_CTL_BUSY) == 0) 1577 if ((temp & MIU_TA_CTL_BUSY) == 0)
1662 break; 1578 break;
1663 } 1579 }
@@ -1679,10 +1595,11 @@ int
1679netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, 1595netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1680 u64 off, void *data, int size) 1596 u64 off, void *data, int size)
1681{ 1597{
1682 unsigned long flags, mem_crb; 1598 unsigned long flags;
1683 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1599 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1684 uint32_t temp; 1600 uint32_t temp;
1685 uint64_t off8, val, word[2] = {0, 0}; 1601 uint64_t off8, val, word[2] = {0, 0};
1602 void __iomem *mem_crb;
1686 1603
1687 1604
1688 /* 1605 /*
@@ -1697,24 +1614,24 @@ netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1697 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); 1614 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1698 sz[1] = size - sz[0]; 1615 sz[1] = size - sz[0];
1699 loop = ((off0[0] + size - 1) >> 3) + 1; 1616 loop = ((off0[0] + size - 1) >> 3) + 1;
1700 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET); 1617 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1701 1618
1702 write_lock_irqsave(&adapter->adapter_lock, flags); 1619 write_lock_irqsave(&adapter->adapter_lock, flags);
1703 netxen_nic_pci_change_crbwindow_128M(adapter, 0); 1620 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1704 1621
1705 for (i = 0; i < loop; i++) { 1622 for (i = 0; i < loop; i++) {
1706 writel((uint32_t)(off8 + (i << 3)), 1623 writel((uint32_t)(off8 + (i << 3)),
1707 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO)); 1624 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1708 writel(0, 1625 writel(0,
1709 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI)); 1626 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1710 writel(MIU_TA_CTL_ENABLE, 1627 writel(MIU_TA_CTL_ENABLE,
1711 (void *)(mem_crb+MIU_TEST_AGT_CTRL)); 1628 (mem_crb+MIU_TEST_AGT_CTRL));
1712 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE, 1629 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1713 (void *)(mem_crb+MIU_TEST_AGT_CTRL)); 1630 (mem_crb+MIU_TEST_AGT_CTRL));
1714 1631
1715 for (j = 0; j < MAX_CTL_CHECK; j++) { 1632 for (j = 0; j < MAX_CTL_CHECK; j++) {
1716 temp = readl( 1633 temp = readl(
1717 (void *)(mem_crb+MIU_TEST_AGT_CTRL)); 1634 (mem_crb+MIU_TEST_AGT_CTRL));
1718 if ((temp & MIU_TA_CTL_BUSY) == 0) 1635 if ((temp & MIU_TA_CTL_BUSY) == 0)
1719 break; 1636 break;
1720 } 1637 }
@@ -1729,7 +1646,7 @@ netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1729 end = (off0[i] + sz[i] - 1) >> 2; 1646 end = (off0[i] + sz[i] - 1) >> 2;
1730 for (k = start; k <= end; k++) { 1647 for (k = start; k <= end; k++) {
1731 word[i] |= ((uint64_t) readl( 1648 word[i] |= ((uint64_t) readl(
1732 (void *)(mem_crb + 1649 (mem_crb +
1733 MIU_TEST_AGT_RDDATA(k))) << (32*k)); 1650 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1734 } 1651 }
1735 } 1652 }
@@ -1761,7 +1678,6 @@ netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1761 *(uint64_t *)data = val; 1678 *(uint64_t *)data = val;
1762 break; 1679 break;
1763 } 1680 }
1764 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1765 return 0; 1681 return 0;
1766} 1682}
1767 1683
@@ -1970,7 +1886,6 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1970 *(uint64_t *)data = val; 1886 *(uint64_t *)data = val;
1971 break; 1887 break;
1972 } 1888 }
1973 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1974 return 0; 1889 return 0;
1975} 1890}
1976 1891
@@ -2024,10 +1939,10 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2024 int addr = NETXEN_BRDCFG_START; 1939 int addr = NETXEN_BRDCFG_START;
2025 struct netxen_board_info *boardinfo; 1940 struct netxen_board_info *boardinfo;
2026 int index; 1941 int index;
2027 u32 *ptr32; 1942 int *ptr32;
2028 1943
2029 boardinfo = &adapter->ahw.boardcfg; 1944 boardinfo = &adapter->ahw.boardcfg;
2030 ptr32 = (u32 *) boardinfo; 1945 ptr32 = (int *) boardinfo;
2031 1946
2032 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32); 1947 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
2033 index++) { 1948 index++) {
@@ -2207,13 +2122,13 @@ void netxen_nic_flash_print(struct netxen_adapter *adapter)
2207 char brd_name[NETXEN_MAX_SHORT_NAME]; 2122 char brd_name[NETXEN_MAX_SHORT_NAME];
2208 char serial_num[32]; 2123 char serial_num[32];
2209 int i, addr; 2124 int i, addr;
2210 __le32 *ptr32; 2125 int *ptr32;
2211 2126
2212 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); 2127 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
2213 2128
2214 adapter->driver_mismatch = 0; 2129 adapter->driver_mismatch = 0;
2215 2130
2216 ptr32 = (u32 *)&serial_num; 2131 ptr32 = (int *)&serial_num;
2217 addr = NETXEN_USER_START + 2132 addr = NETXEN_USER_START +
2218 offsetof(struct netxen_new_user_info, serial_num); 2133 offsetof(struct netxen_new_user_info, serial_num);
2219 for (i = 0; i < 8; i++) { 2134 for (i = 0; i < 8; i++) {