diff options
author | Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> | 2009-09-30 08:07:38 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-09-30 23:02:55 -0400 |
commit | 539e5f02c5d11d14a75dae88ed92b32386649e75 (patch) | |
tree | d99a52db1a13355bfe9137e7dcbfb9abc2051778 /drivers/net/ixgbe | |
parent | 84f62d4b5888bd1a254d6055e5ff6989bae8a6a9 (diff) |
ixgbe: Fix backplane flow control autoneg
Backplane flow control autonegotiation is currently broken for
ixgbe devices. This patch fixes the flow control issues
with clause 37 autoneg.
Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe')
-rw-r--r-- | drivers/net/ixgbe/ixgbe_82598.c | 2 | ||||
-rw-r--r-- | drivers/net/ixgbe/ixgbe_common.c | 228 | ||||
-rw-r--r-- | drivers/net/ixgbe/ixgbe_type.h | 9 |
3 files changed, 187 insertions, 52 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c index 56b12f3192f..e2d5343f127 100644 --- a/drivers/net/ixgbe/ixgbe_82598.c +++ b/drivers/net/ixgbe/ixgbe_82598.c | |||
@@ -425,7 +425,7 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
425 | #endif /* CONFIG_DCB */ | 425 | #endif /* CONFIG_DCB */ |
426 | default: | 426 | default: |
427 | hw_dbg(hw, "Flow control param set incorrectly\n"); | 427 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
428 | ret_val = -IXGBE_ERR_CONFIG; | 428 | ret_val = IXGBE_ERR_CONFIG; |
429 | goto out; | 429 | goto out; |
430 | break; | 430 | break; |
431 | } | 431 | } |
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c index 6621e172df3..143b0fcbe95 100644 --- a/drivers/net/ixgbe/ixgbe_common.c +++ b/drivers/net/ixgbe/ixgbe_common.c | |||
@@ -1663,7 +1663,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1663 | #endif /* CONFIG_DCB */ | 1663 | #endif /* CONFIG_DCB */ |
1664 | default: | 1664 | default: |
1665 | hw_dbg(hw, "Flow control param set incorrectly\n"); | 1665 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
1666 | ret_val = -IXGBE_ERR_CONFIG; | 1666 | ret_val = IXGBE_ERR_CONFIG; |
1667 | goto out; | 1667 | goto out; |
1668 | break; | 1668 | break; |
1669 | } | 1669 | } |
@@ -1734,75 +1734,140 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) | |||
1734 | s32 ret_val = 0; | 1734 | s32 ret_val = 0; |
1735 | ixgbe_link_speed speed; | 1735 | ixgbe_link_speed speed; |
1736 | u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; | 1736 | u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; |
1737 | u32 links2, anlp1_reg, autoc_reg, links; | ||
1737 | bool link_up; | 1738 | bool link_up; |
1738 | 1739 | ||
1739 | /* | 1740 | /* |
1740 | * AN should have completed when the cable was plugged in. | 1741 | * AN should have completed when the cable was plugged in. |
1741 | * Look for reasons to bail out. Bail out if: | 1742 | * Look for reasons to bail out. Bail out if: |
1742 | * - FC autoneg is disabled, or if | 1743 | * - FC autoneg is disabled, or if |
1743 | * - we don't have multispeed fiber, or if | 1744 | * - link is not up. |
1744 | * - we're not running at 1G, or if | ||
1745 | * - link is not up, or if | ||
1746 | * - link is up but AN did not complete, or if | ||
1747 | * - link is up and AN completed but timed out | ||
1748 | * | 1745 | * |
1749 | * Since we're being called from an LSC, link is already know to be up. | 1746 | * Since we're being called from an LSC, link is already known to be up. |
1750 | * So use link_up_wait_to_complete=false. | 1747 | * So use link_up_wait_to_complete=false. |
1751 | */ | 1748 | */ |
1752 | hw->mac.ops.check_link(hw, &speed, &link_up, false); | 1749 | hw->mac.ops.check_link(hw, &speed, &link_up, false); |
1753 | linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | 1750 | |
1754 | 1751 | if (hw->fc.disable_fc_autoneg || (!link_up)) { | |
1755 | if (hw->fc.disable_fc_autoneg || | ||
1756 | !hw->phy.multispeed_fiber || | ||
1757 | (speed != IXGBE_LINK_SPEED_1GB_FULL) || | ||
1758 | !link_up || | ||
1759 | ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || | ||
1760 | ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { | ||
1761 | hw->fc.fc_was_autonegged = false; | 1752 | hw->fc.fc_was_autonegged = false; |
1762 | hw->fc.current_mode = hw->fc.requested_mode; | 1753 | hw->fc.current_mode = hw->fc.requested_mode; |
1763 | hw_dbg(hw, "Autoneg FC was skipped.\n"); | ||
1764 | goto out; | 1754 | goto out; |
1765 | } | 1755 | } |
1766 | 1756 | ||
1767 | /* | 1757 | /* |
1758 | * On backplane, bail out if | ||
1759 | * - backplane autoneg was not completed, or if | ||
1760 | * - link partner is not AN enabled | ||
1761 | */ | ||
1762 | if (hw->phy.media_type == ixgbe_media_type_backplane) { | ||
1763 | links = IXGBE_READ_REG(hw, IXGBE_LINKS); | ||
1764 | links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); | ||
1765 | if (((links & IXGBE_LINKS_KX_AN_COMP) == 0) || | ||
1766 | ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)) { | ||
1767 | hw->fc.fc_was_autonegged = false; | ||
1768 | hw->fc.current_mode = hw->fc.requested_mode; | ||
1769 | goto out; | ||
1770 | } | ||
1771 | } | ||
1772 | |||
1773 | /* | ||
1774 | * On multispeed fiber at 1g, bail out if | ||
1775 | * - link is up but AN did not complete, or if | ||
1776 | * - link is up and AN completed but timed out | ||
1777 | */ | ||
1778 | if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) { | ||
1779 | linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | ||
1780 | if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || | ||
1781 | ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { | ||
1782 | hw->fc.fc_was_autonegged = false; | ||
1783 | hw->fc.current_mode = hw->fc.requested_mode; | ||
1784 | goto out; | ||
1785 | } | ||
1786 | } | ||
1787 | |||
1788 | /* | ||
1768 | * Read the AN advertisement and LP ability registers and resolve | 1789 | * Read the AN advertisement and LP ability registers and resolve |
1769 | * local flow control settings accordingly | 1790 | * local flow control settings accordingly |
1770 | */ | 1791 | */ |
1771 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | 1792 | if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && |
1772 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); | 1793 | (hw->phy.media_type != ixgbe_media_type_backplane)) { |
1773 | if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | 1794 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); |
1774 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { | 1795 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); |
1796 | if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1797 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { | ||
1798 | /* | ||
1799 | * Now we need to check if the user selected Rx ONLY | ||
1800 | * of pause frames. In this case, we had to advertise | ||
1801 | * FULL flow control because we could not advertise RX | ||
1802 | * ONLY. Hence, we must now check to see if we need to | ||
1803 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1804 | */ | ||
1805 | if (hw->fc.requested_mode == ixgbe_fc_full) { | ||
1806 | hw->fc.current_mode = ixgbe_fc_full; | ||
1807 | hw_dbg(hw, "Flow Control = FULL.\n"); | ||
1808 | } else { | ||
1809 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1810 | hw_dbg(hw, "Flow Control=RX PAUSE only\n"); | ||
1811 | } | ||
1812 | } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1813 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1814 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1815 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1816 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1817 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1818 | } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1819 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1820 | !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1821 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1822 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1823 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | ||
1824 | } else { | ||
1825 | hw->fc.current_mode = ixgbe_fc_none; | ||
1826 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1827 | } | ||
1828 | } | ||
1829 | |||
1830 | if (hw->phy.media_type == ixgbe_media_type_backplane) { | ||
1775 | /* | 1831 | /* |
1776 | * Now we need to check if the user selected Rx ONLY | 1832 | * Read the 10g AN autoc and LP ability registers and resolve |
1777 | * of pause frames. In this case, we had to advertise | 1833 | * local flow control settings accordingly |
1778 | * FULL flow control because we could not advertise RX | ||
1779 | * ONLY. Hence, we must now check to see if we need to | ||
1780 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1781 | */ | 1834 | */ |
1782 | if (hw->fc.requested_mode == ixgbe_fc_full) { | 1835 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1783 | hw->fc.current_mode = ixgbe_fc_full; | 1836 | anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); |
1784 | hw_dbg(hw, "Flow Control = FULL.\n"); | 1837 | |
1785 | } else { | 1838 | if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && |
1839 | (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) { | ||
1840 | /* | ||
1841 | * Now we need to check if the user selected Rx ONLY | ||
1842 | * of pause frames. In this case, we had to advertise | ||
1843 | * FULL flow control because we could not advertise RX | ||
1844 | * ONLY. Hence, we must now check to see if we need to | ||
1845 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1846 | */ | ||
1847 | if (hw->fc.requested_mode == ixgbe_fc_full) { | ||
1848 | hw->fc.current_mode = ixgbe_fc_full; | ||
1849 | hw_dbg(hw, "Flow Control = FULL.\n"); | ||
1850 | } else { | ||
1851 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1852 | hw_dbg(hw, "Flow Control=RX PAUSE only\n"); | ||
1853 | } | ||
1854 | } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && | ||
1855 | (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && | ||
1856 | (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && | ||
1857 | (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { | ||
1858 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1859 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1860 | } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && | ||
1861 | (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && | ||
1862 | !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && | ||
1863 | (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { | ||
1786 | hw->fc.current_mode = ixgbe_fc_rx_pause; | 1864 | hw->fc.current_mode = ixgbe_fc_rx_pause; |
1787 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | 1865 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); |
1866 | } else { | ||
1867 | hw->fc.current_mode = ixgbe_fc_none; | ||
1868 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1788 | } | 1869 | } |
1789 | } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1790 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1791 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1792 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1793 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1794 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1795 | } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1796 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1797 | !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1798 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1799 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1800 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | ||
1801 | } else { | ||
1802 | hw->fc.current_mode = ixgbe_fc_none; | ||
1803 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1804 | } | 1870 | } |
1805 | |||
1806 | /* Record that current_mode is the result of a successful autoneg */ | 1871 | /* Record that current_mode is the result of a successful autoneg */ |
1807 | hw->fc.fc_was_autonegged = true; | 1872 | hw->fc.fc_was_autonegged = true; |
1808 | 1873 | ||
@@ -1919,7 +1984,7 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1919 | #endif /* CONFIG_DCB */ | 1984 | #endif /* CONFIG_DCB */ |
1920 | default: | 1985 | default: |
1921 | hw_dbg(hw, "Flow control param set incorrectly\n"); | 1986 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
1922 | ret_val = -IXGBE_ERR_CONFIG; | 1987 | ret_val = IXGBE_ERR_CONFIG; |
1923 | goto out; | 1988 | goto out; |
1924 | break; | 1989 | break; |
1925 | } | 1990 | } |
@@ -1927,9 +1992,6 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1927 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); | 1992 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); |
1928 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); | 1993 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); |
1929 | 1994 | ||
1930 | /* Enable and restart autoneg to inform the link partner */ | ||
1931 | reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; | ||
1932 | |||
1933 | /* Disable AN timeout */ | 1995 | /* Disable AN timeout */ |
1934 | if (hw->fc.strict_ieee) | 1996 | if (hw->fc.strict_ieee) |
1935 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; | 1997 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; |
@@ -1937,6 +1999,70 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1937 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); | 1999 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); |
1938 | hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); | 2000 | hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); |
1939 | 2001 | ||
2002 | /* | ||
2003 | * Set up the 10G flow control advertisement registers so the HW | ||
2004 | * can do fc autoneg once the cable is plugged in. If we end up | ||
2005 | * using 1g instead, this is harmless. | ||
2006 | */ | ||
2007 | reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); | ||
2008 | |||
2009 | /* | ||
2010 | * The possible values of fc.requested_mode are: | ||
2011 | * 0: Flow control is completely disabled | ||
2012 | * 1: Rx flow control is enabled (we can receive pause frames, | ||
2013 | * but not send pause frames). | ||
2014 | * 2: Tx flow control is enabled (we can send pause frames but | ||
2015 | * we do not support receiving pause frames). | ||
2016 | * 3: Both Rx and Tx flow control (symmetric) are enabled. | ||
2017 | * other: Invalid. | ||
2018 | */ | ||
2019 | switch (hw->fc.requested_mode) { | ||
2020 | case ixgbe_fc_none: | ||
2021 | /* Flow control completely disabled by software override. */ | ||
2022 | reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2023 | break; | ||
2024 | case ixgbe_fc_rx_pause: | ||
2025 | /* | ||
2026 | * Rx Flow control is enabled and Tx Flow control is | ||
2027 | * disabled by software override. Since there really | ||
2028 | * isn't a way to advertise that we are capable of RX | ||
2029 | * Pause ONLY, we will advertise that we support both | ||
2030 | * symmetric and asymmetric Rx PAUSE. Later, we will | ||
2031 | * disable the adapter's ability to send PAUSE frames. | ||
2032 | */ | ||
2033 | reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2034 | break; | ||
2035 | case ixgbe_fc_tx_pause: | ||
2036 | /* | ||
2037 | * Tx Flow control is enabled, and Rx Flow control is | ||
2038 | * disabled by software override. | ||
2039 | */ | ||
2040 | reg |= (IXGBE_AUTOC_ASM_PAUSE); | ||
2041 | reg &= ~(IXGBE_AUTOC_SYM_PAUSE); | ||
2042 | break; | ||
2043 | case ixgbe_fc_full: | ||
2044 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | ||
2045 | reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2046 | break; | ||
2047 | #ifdef CONFIG_DCB | ||
2048 | case ixgbe_fc_pfc: | ||
2049 | goto out; | ||
2050 | break; | ||
2051 | #endif /* CONFIG_DCB */ | ||
2052 | default: | ||
2053 | hw_dbg(hw, "Flow control param set incorrectly\n"); | ||
2054 | ret_val = IXGBE_ERR_CONFIG; | ||
2055 | goto out; | ||
2056 | break; | ||
2057 | } | ||
2058 | /* | ||
2059 | * AUTOC restart handles negotiation of 1G and 10G. There is | ||
2060 | * no need to set the PCS1GCTL register. | ||
2061 | */ | ||
2062 | reg |= IXGBE_AUTOC_AN_RESTART; | ||
2063 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg); | ||
2064 | hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); | ||
2065 | |||
1940 | out: | 2066 | out: |
1941 | return ret_val; | 2067 | return ret_val; |
1942 | } | 2068 | } |
@@ -2000,7 +2126,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |||
2000 | 2126 | ||
2001 | while (timeout) { | 2127 | while (timeout) { |
2002 | if (ixgbe_get_eeprom_semaphore(hw)) | 2128 | if (ixgbe_get_eeprom_semaphore(hw)) |
2003 | return -IXGBE_ERR_SWFW_SYNC; | 2129 | return IXGBE_ERR_SWFW_SYNC; |
2004 | 2130 | ||
2005 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | 2131 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); |
2006 | if (!(gssr & (fwmask | swmask))) | 2132 | if (!(gssr & (fwmask | swmask))) |
@@ -2017,7 +2143,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |||
2017 | 2143 | ||
2018 | if (!timeout) { | 2144 | if (!timeout) { |
2019 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); | 2145 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); |
2020 | return -IXGBE_ERR_SWFW_SYNC; | 2146 | return IXGBE_ERR_SWFW_SYNC; |
2021 | } | 2147 | } |
2022 | 2148 | ||
2023 | gssr |= swmask; | 2149 | gssr |= swmask; |
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h index 8761d7899f7..7c93e923bf2 100644 --- a/drivers/net/ixgbe/ixgbe_type.h +++ b/drivers/net/ixgbe/ixgbe_type.h | |||
@@ -1336,6 +1336,8 @@ | |||
1336 | #define IXGBE_AUTOC_KX4_SUPP 0x80000000 | 1336 | #define IXGBE_AUTOC_KX4_SUPP 0x80000000 |
1337 | #define IXGBE_AUTOC_KX_SUPP 0x40000000 | 1337 | #define IXGBE_AUTOC_KX_SUPP 0x40000000 |
1338 | #define IXGBE_AUTOC_PAUSE 0x30000000 | 1338 | #define IXGBE_AUTOC_PAUSE 0x30000000 |
1339 | #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 | ||
1340 | #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 | ||
1339 | #define IXGBE_AUTOC_RF 0x08000000 | 1341 | #define IXGBE_AUTOC_RF 0x08000000 |
1340 | #define IXGBE_AUTOC_PD_TMR 0x06000000 | 1342 | #define IXGBE_AUTOC_PD_TMR 0x06000000 |
1341 | #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 | 1343 | #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 |
@@ -1404,6 +1406,8 @@ | |||
1404 | #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ | 1406 | #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ |
1405 | #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ | 1407 | #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ |
1406 | 1408 | ||
1409 | #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 | ||
1410 | |||
1407 | /* PCS1GLSTA Bit Masks */ | 1411 | /* PCS1GLSTA Bit Masks */ |
1408 | #define IXGBE_PCS1GLSTA_LINK_OK 1 | 1412 | #define IXGBE_PCS1GLSTA_LINK_OK 1 |
1409 | #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 | 1413 | #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 |
@@ -1424,6 +1428,11 @@ | |||
1424 | #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 | 1428 | #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 |
1425 | #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 | 1429 | #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 |
1426 | 1430 | ||
1431 | /* ANLP1 Bit Masks */ | ||
1432 | #define IXGBE_ANLP1_PAUSE 0x0C00 | ||
1433 | #define IXGBE_ANLP1_SYM_PAUSE 0x0400 | ||
1434 | #define IXGBE_ANLP1_ASM_PAUSE 0x0800 | ||
1435 | |||
1427 | /* SW Semaphore Register bitmasks */ | 1436 | /* SW Semaphore Register bitmasks */ |
1428 | #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | 1437 | #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ |
1429 | #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | 1438 | #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ |