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authorBruce Allan <bruce.w.allan@intel.com>2008-04-29 12:16:05 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-05-06 12:04:14 -0400
commit97ac8caee238d2a81c23661916f7acd3a22c85fe (patch)
tree52723d8582162e862c78fecb5da2d4d13f7a9579 /drivers/net/e1000e/hw.h
parente284e5c6601cbb16e48854be26aa57a8fa844e35 (diff)
e1000e: Add support for BM PHYs on ICH9
This patch adds support for the BM PHY, a new PHY model being used on ICH9-based implementations. This new PHY exposes issues in the ICH9 silicon when receiving jumbo frames large enough to use more than a certain part of the Rx FIFO, and this unfortunately breaks packet split jumbo receives. For this reason we re-introduce (for affected adapters only) the jumbo single-skb receive routine back so that people who do wish to use jumbo frames on these ich9 platforms can do so. Part of this problem has to do with CPU sleep states and to make sure that all the wake up timings are correctly we force them with the recently merged pm_qos infrastructure written by Mark Gross. (See http://lkml.org/lkml/2007/10/4/400). To make code read a bit easier we introduce a _IS_ICH flag so that we don't need to do mac type checks over the code. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/e1000e/hw.h')
-rw-r--r--drivers/net/e1000e/hw.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index a930e6d9cf0..74f263acb17 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -216,6 +216,21 @@ enum e1e_registers {
216#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 216#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
217#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 217#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
218#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 218#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
219#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
220#define IGP_PAGE_SHIFT 5
221#define PHY_REG_MASK 0x1F
222
223#define BM_WUC_PAGE 800
224#define BM_WUC_ADDRESS_OPCODE 0x11
225#define BM_WUC_DATA_OPCODE 0x12
226#define BM_WUC_ENABLE_PAGE 769
227#define BM_WUC_ENABLE_REG 17
228#define BM_WUC_ENABLE_BIT (1 << 2)
229#define BM_WUC_HOST_WU_BIT (1 << 4)
230
231#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
232#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
233#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
219 234
220#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 235#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
221#define IGP01E1000_PHY_POLARITY_MASK 0x0078 236#define IGP01E1000_PHY_POLARITY_MASK 0x0078
@@ -331,10 +346,16 @@ enum e1e_registers {
331#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 346#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
332#define E1000_DEV_ID_ICH8_IGP_M 0x104D 347#define E1000_DEV_ID_ICH8_IGP_M 0x104D
333#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 348#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
349#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
350#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
351#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
334#define E1000_DEV_ID_ICH9_IGP_C 0x294C 352#define E1000_DEV_ID_ICH9_IGP_C 0x294C
335#define E1000_DEV_ID_ICH9_IFE 0x10C0 353#define E1000_DEV_ID_ICH9_IFE 0x10C0
336#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 354#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
337#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 355#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
356#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
357#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
358#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
338 359
339#define E1000_FUNC_1 1 360#define E1000_FUNC_1 1
340 361
@@ -378,6 +399,7 @@ enum e1000_phy_type {
378 e1000_phy_gg82563, 399 e1000_phy_gg82563,
379 e1000_phy_igp_3, 400 e1000_phy_igp_3,
380 e1000_phy_ife, 401 e1000_phy_ife,
402 e1000_phy_bm,
381}; 403};
382 404
383enum e1000_bus_width { 405enum e1000_bus_width {