aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/cxgb3
diff options
context:
space:
mode:
authorDivy Le Ray <divy@chelsio.com>2007-03-18 16:10:12 -0400
committerJeff Garzik <jeff@garzik.org>2007-03-23 01:48:34 -0400
commitfc90664e3438c990d280f179ccb0642711d5c553 (patch)
tree8ece58a4eec002186f1c569385830f03336b50af /drivers/net/cxgb3
parent2e2839627a957714808f98a802d137a7a2a1df46 (diff)
cxgb3 - Fix potential MAC hang
Under rare conditions, the MAC might hang while generating a pause frame. This patch fine tunes the MAC settings to avoid the issue, allows for periodic MAC state check, and triggers a recovery if hung. Also fix one MAC statistics counter for the rev board T3B2. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/cxgb3')
-rw-r--r--drivers/net/cxgb3/common.h15
-rw-r--r--drivers/net/cxgb3/cxgb3_main.c46
-rw-r--r--drivers/net/cxgb3/regs.h22
-rw-r--r--drivers/net/cxgb3/xgmac.c133
4 files changed, 200 insertions, 16 deletions
diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h
index e23deeb7d06..85e5543cfb5 100644
--- a/drivers/net/cxgb3/common.h
+++ b/drivers/net/cxgb3/common.h
@@ -260,6 +260,10 @@ struct mac_stats {
260 unsigned long serdes_signal_loss; 260 unsigned long serdes_signal_loss;
261 unsigned long xaui_pcs_ctc_err; 261 unsigned long xaui_pcs_ctc_err;
262 unsigned long xaui_pcs_align_change; 262 unsigned long xaui_pcs_align_change;
263
264 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
265 unsigned long num_resets; /* # times reset due to stuck TX */
266
263}; 267};
264 268
265struct tp_mib_stats { 269struct tp_mib_stats {
@@ -400,6 +404,12 @@ struct adapter_params {
400 unsigned int rev; /* chip revision */ 404 unsigned int rev; /* chip revision */
401}; 405};
402 406
407enum { /* chip revisions */
408 T3_REV_A = 0,
409 T3_REV_B = 2,
410 T3_REV_B2 = 3,
411};
412
403struct trace_params { 413struct trace_params {
404 u32 sip; 414 u32 sip;
405 u32 sip_mask; 415 u32 sip_mask;
@@ -465,6 +475,10 @@ struct cmac {
465 struct adapter *adapter; 475 struct adapter *adapter;
466 unsigned int offset; 476 unsigned int offset;
467 unsigned int nucast; /* # of address filters for unicast MACs */ 477 unsigned int nucast; /* # of address filters for unicast MACs */
478 unsigned int tcnt;
479 unsigned int xcnt;
480 unsigned int toggle_cnt;
481 unsigned int txen;
468 struct mac_stats stats; 482 struct mac_stats stats;
469}; 483};
470 484
@@ -666,6 +680,7 @@ int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
666int t3_mac_set_num_ucast(struct cmac *mac, int n); 680int t3_mac_set_num_ucast(struct cmac *mac, int n);
667const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 681const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
668int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); 682int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
683int t3b2_mac_watchdog_task(struct cmac *mac);
669 684
670void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode); 685void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
671int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 686int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c
index b9bcda821f7..d5538361055 100644
--- a/drivers/net/cxgb3/cxgb3_main.c
+++ b/drivers/net/cxgb3/cxgb3_main.c
@@ -1056,7 +1056,11 @@ static char stats_strings[][ETH_GSTRING_LEN] = {
1056 "VLANinsertions ", 1056 "VLANinsertions ",
1057 "TxCsumOffload ", 1057 "TxCsumOffload ",
1058 "RxCsumGood ", 1058 "RxCsumGood ",
1059 "RxDrops " 1059 "RxDrops ",
1060
1061 "CheckTXEnToggled ",
1062 "CheckResets ",
1063
1060}; 1064};
1061 1065
1062static int get_stats_count(struct net_device *dev) 1066static int get_stats_count(struct net_device *dev)
@@ -1170,6 +1174,9 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1170 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM); 1174 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1171 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD); 1175 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
1172 *data++ = s->rx_cong_drops; 1176 *data++ = s->rx_cong_drops;
1177
1178 *data++ = s->num_toggled;
1179 *data++ = s->num_resets;
1173} 1180}
1174 1181
1175static inline void reg_block_dump(struct adapter *ap, void *buf, 1182static inline void reg_block_dump(struct adapter *ap, void *buf,
@@ -2095,6 +2102,40 @@ static void check_link_status(struct adapter *adapter)
2095 } 2102 }
2096} 2103}
2097 2104
2105static void check_t3b2_mac(struct adapter *adapter)
2106{
2107 int i;
2108
2109 rtnl_lock(); /* synchronize with ifdown */
2110 for_each_port(adapter, i) {
2111 struct net_device *dev = adapter->port[i];
2112 struct port_info *p = netdev_priv(dev);
2113 int status;
2114
2115 if (!netif_running(dev))
2116 continue;
2117
2118 status = 0;
2119 if (netif_running(dev))
2120 status = t3b2_mac_watchdog_task(&p->mac);
2121 if (status == 1)
2122 p->mac.stats.num_toggled++;
2123 else if (status == 2) {
2124 struct cmac *mac = &p->mac;
2125
2126 t3_mac_set_mtu(mac, dev->mtu);
2127 t3_mac_set_address(mac, 0, dev->dev_addr);
2128 cxgb_set_rxmode(dev);
2129 t3_link_start(&p->phy, mac, &p->link_config);
2130 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2131 t3_port_intr_enable(adapter, p->port_id);
2132 p->mac.stats.num_resets++;
2133 }
2134 }
2135 rtnl_unlock();
2136}
2137
2138
2098static void t3_adap_check_task(struct work_struct *work) 2139static void t3_adap_check_task(struct work_struct *work)
2099{ 2140{
2100 struct adapter *adapter = container_of(work, struct adapter, 2141 struct adapter *adapter = container_of(work, struct adapter,
@@ -2115,6 +2156,9 @@ static void t3_adap_check_task(struct work_struct *work)
2115 adapter->check_task_cnt = 0; 2156 adapter->check_task_cnt = 0;
2116 } 2157 }
2117 2158
2159 if (p->rev == T3_REV_B2)
2160 check_t3b2_mac(adapter);
2161
2118 /* Schedule the next check update if any port is active. */ 2162 /* Schedule the next check update if any port is active. */
2119 spin_lock(&adapter->work_lock); 2163 spin_lock(&adapter->work_lock);
2120 if (adapter->open_device_map & PORT_MASK) 2164 if (adapter->open_device_map & PORT_MASK)
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h
index b56c5f52bcd..b38629a244d 100644
--- a/drivers/net/cxgb3/regs.h
+++ b/drivers/net/cxgb3/regs.h
@@ -1206,6 +1206,14 @@
1206 1206
1207#define A_TP_RX_TRC_KEY0 0x120 1207#define A_TP_RX_TRC_KEY0 0x120
1208 1208
1209#define A_TP_TX_DROP_CNT_CH0 0x12d
1210
1211#define S_TXDROPCNTCH0RCVD 0
1212#define M_TXDROPCNTCH0RCVD 0xffff
1213#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
1214#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
1215 M_TXDROPCNTCH0RCVD)
1216
1209#define A_ULPRX_CTL 0x500 1217#define A_ULPRX_CTL 0x500
1210 1218
1211#define S_ROUND_ROBIN 4 1219#define S_ROUND_ROBIN 4
@@ -1834,6 +1842,8 @@
1834#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN) 1842#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
1835#define F_TXPAUSEEN V_TXPAUSEEN(1U) 1843#define F_TXPAUSEEN V_TXPAUSEEN(1U)
1836 1844
1845#define A_XGM_TX_PAUSE_QUANTA 0x808
1846
1837#define A_XGM_RX_CTRL 0x80c 1847#define A_XGM_RX_CTRL 0x80c
1838 1848
1839#define S_RXEN 0 1849#define S_RXEN 0
@@ -1920,6 +1930,11 @@
1920 1930
1921#define A_XGM_TXFIFO_CFG 0x888 1931#define A_XGM_TXFIFO_CFG 0x888
1922 1932
1933#define S_TXIPG 13
1934#define M_TXIPG 0xff
1935#define V_TXIPG(x) ((x) << S_TXIPG)
1936#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
1937
1923#define S_TXFIFOTHRESH 4 1938#define S_TXFIFOTHRESH 4
1924#define M_TXFIFOTHRESH 0x1ff 1939#define M_TXFIFOTHRESH 0x1ff
1925 1940
@@ -2190,6 +2205,13 @@
2190 2205
2191#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4 2206#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2192 2207
2208#define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
2209
2210#define S_TXSPI4SOPCNT 16
2211#define M_TXSPI4SOPCNT 0xffff
2212#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
2213#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
2214
2193#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac 2215#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
2194 2216
2195#define XGMAC0_1_BASE_ADDR 0xa00 2217#define XGMAC0_1_BASE_ADDR 0xa00
diff --git a/drivers/net/cxgb3/xgmac.c b/drivers/net/cxgb3/xgmac.c
index 907a272ae32..2b42c13ba8e 100644
--- a/drivers/net/cxgb3/xgmac.c
+++ b/drivers/net/cxgb3/xgmac.c
@@ -124,9 +124,6 @@ int t3_mac_reset(struct cmac *mac)
124 xaui_serdes_reset(mac); 124 xaui_serdes_reset(mac);
125 } 125 }
126 126
127 if (adap->params.rev > 0)
128 t3_write_reg(adap, A_XGM_PAUSE_TIMER + oft, 0xf000);
129
130 val = F_MAC_RESET_; 127 val = F_MAC_RESET_;
131 if (is_10G(adap)) 128 if (is_10G(adap))
132 val |= F_PCS_RESET_; 129 val |= F_PCS_RESET_;
@@ -145,6 +142,58 @@ int t3_mac_reset(struct cmac *mac)
145 return 0; 142 return 0;
146} 143}
147 144
145int t3b2_mac_reset(struct cmac *mac)
146{
147 struct adapter *adap = mac->adapter;
148 unsigned int oft = mac->offset;
149 u32 val;
150
151 if (!macidx(mac))
152 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
153 else
154 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
155
156 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
157 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
158
159 msleep(10);
160
161 /* Check for xgm Rx fifo empty */
162 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
163 0x80000000, 1, 5, 2)) {
164 CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
165 macidx(mac));
166 return -1;
167 }
168
169 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);
170 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
171
172 val = F_MAC_RESET_;
173 if (is_10G(adap))
174 val |= F_PCS_RESET_;
175 else if (uses_xaui(adap))
176 val |= F_PCS_RESET_ | F_XG2G_RESET_;
177 else
178 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
179 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
180 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
181 if ((val & F_PCS_RESET_) && adap->params.rev) {
182 msleep(1);
183 t3b_pcs_reset(mac);
184 }
185 t3_write_reg(adap, A_XGM_RX_CFG + oft,
186 F_DISPAUSEFRAMES | F_EN1536BFRAMES |
187 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST);
188
189 if (!macidx(mac))
190 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
191 else
192 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
193
194 return 0;
195}
196
148/* 197/*
149 * Set the exact match register 'idx' to recognize the given Ethernet address. 198 * Set the exact match register 'idx' to recognize the given Ethernet address.
150 */ 199 */
@@ -251,9 +300,11 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
251 * Adjust the PAUSE frame watermarks. We always set the LWM, and the 300 * Adjust the PAUSE frame watermarks. We always set the LWM, and the
252 * HWM only if flow-control is enabled. 301 * HWM only if flow-control is enabled.
253 */ 302 */
254 hwm = max(MAC_RXFIFO_SIZE - 3 * mtu, MAC_RXFIFO_SIZE / 2U); 303 hwm = max_t(unsigned int, MAC_RXFIFO_SIZE - 3 * mtu,
255 hwm = min(hwm, 3 * MAC_RXFIFO_SIZE / 4 + 1024); 304 MAC_RXFIFO_SIZE * 38 / 100);
256 lwm = hwm - 1024; 305 hwm = min(hwm, MAC_RXFIFO_SIZE - 8192);
306 lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
307
257 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset); 308 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
258 v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM); 309 v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);
259 v |= V_RXFIFOPAUSELWM(lwm / 8); 310 v |= V_RXFIFOPAUSELWM(lwm / 8);
@@ -270,7 +321,15 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
270 thres = mtu > thres ? (mtu - thres + 7) / 8 : 0; 321 thres = mtu > thres ? (mtu - thres + 7) / 8 : 0;
271 thres = max(thres, 8U); /* need at least 8 */ 322 thres = max(thres, 8U); /* need at least 8 */
272 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset, 323 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
273 V_TXFIFOTHRESH(M_TXFIFOTHRESH), V_TXFIFOTHRESH(thres)); 324 V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
325 V_TXFIFOTHRESH(thres) | V_TXIPG(1));
326
327 if (adap->params.rev > 0)
328 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
329 (hwm - lwm) * 4 / 8);
330 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
331 MAC_RXFIFO_SIZE * 4 * 8 / 512);
332
274 return 0; 333 return 0;
275} 334}
276 335
@@ -298,12 +357,6 @@ int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
298 V_PORTSPEED(M_PORTSPEED), val); 357 V_PORTSPEED(M_PORTSPEED), val);
299 } 358 }
300 359
301 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
302 val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
303 if (fc & PAUSE_TX)
304 val |= V_RXFIFOPAUSEHWM(G_RXFIFOPAUSELWM(val) + 128); /* +1KB */
305 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
306
307 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 360 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
308 (fc & PAUSE_RX) ? F_TXPAUSEEN : 0); 361 (fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
309 return 0; 362 return 0;
@@ -318,9 +371,17 @@ int t3_mac_enable(struct cmac *mac, int which)
318 if (which & MAC_DIRECTION_TX) { 371 if (which & MAC_DIRECTION_TX) {
319 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); 372 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
320 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); 373 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
321 t3_write_reg(adap, A_TP_PIO_DATA, 0xbf000001); 374 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
322 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE); 375 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
323 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx); 376 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
377
378 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
379 mac->tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
380 A_TP_PIO_DATA)));
381 mac->xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
382 A_XGM_TX_SPI4_SOP_EOP_CNT)));
383 mac->txen = F_TXEN;
384 mac->toggle_cnt = 0;
324 } 385 }
325 if (which & MAC_DIRECTION_RX) 386 if (which & MAC_DIRECTION_RX)
326 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN); 387 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
@@ -337,13 +398,50 @@ int t3_mac_disable(struct cmac *mac, int which)
337 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); 398 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
338 t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f); 399 t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f);
339 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE); 400 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
340 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 0); 401 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
402 mac->txen = 0;
341 } 403 }
342 if (which & MAC_DIRECTION_RX) 404 if (which & MAC_DIRECTION_RX)
343 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0); 405 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
344 return 0; 406 return 0;
345} 407}
346 408
409int t3b2_mac_watchdog_task(struct cmac *mac)
410{
411 struct adapter *adap = mac->adapter;
412 unsigned int tcnt, xcnt;
413 int status;
414
415 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + macidx(mac));
416 tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, A_TP_PIO_DATA)));
417 xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
418 A_XGM_TX_SPI4_SOP_EOP_CNT +
419 mac->offset)));
420
421 if (tcnt != mac->tcnt && xcnt == 0 && mac->xcnt == 0) {
422 if (mac->toggle_cnt > 4) {
423 t3b2_mac_reset(mac);
424 mac->toggle_cnt = 0;
425 status = 2;
426 } else {
427 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
428 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);
429 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset,
430 mac->txen);
431 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);
432 mac->toggle_cnt++;
433 status = 1;
434 }
435 } else {
436 mac->toggle_cnt = 0;
437 status = 0;
438 }
439 mac->tcnt = tcnt;
440 mac->xcnt = xcnt;
441
442 return status;
443}
444
347/* 445/*
348 * This function is called periodically to accumulate the current values of the 446 * This function is called periodically to accumulate the current values of the
349 * RMON counters into the port statistics. Since the packet counters are only 447 * RMON counters into the port statistics. Since the packet counters are only
@@ -375,6 +473,11 @@ const struct mac_stats *t3_mac_update_stats(struct cmac *mac)
375 RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES); 473 RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES);
376 mac->stats.rx_too_long += RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT); 474 mac->stats.rx_too_long += RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
377 475
476 v = RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
477 if (mac->adapter->params.rev == T3_REV_B2)
478 v &= 0x7fffffff;
479 mac->stats.rx_too_long += v;
480
378 RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES); 481 RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES);
379 RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES); 482 RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES);
380 RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES); 483 RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES);