diff options
author | Eilon Greenstein <eilong@broadcom.com> | 2009-08-12 04:23:04 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-13 02:02:27 -0400 |
commit | 239d686d494f10ecd83a89ddc4e31f9462ca4901 (patch) | |
tree | e3ce31aeb39bb144fa8ce9f74eadf764d39f05fd /drivers/net/bnx2x_reg.h | |
parent | bc7f0a053021491e292fc00810c4f2a8524453dd (diff) |
bnx2x: Adding XAUI CL73 autoneg support
Adding CL73 support to the built in PHY in the 5771x device. Also supporting
fallbacks to CL73 if the link partner does not respond.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_reg.h')
-rw-r--r-- | drivers/net/bnx2x_reg.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index 9a20da5bf19..999838629be 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h | |||
@@ -5596,6 +5596,9 @@ | |||
5596 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 | 5596 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 |
5597 | 5597 | ||
5598 | #define MDIO_REG_BANK_RX0 0x80b0 | 5598 | #define MDIO_REG_BANK_RX0 0x80b0 |
5599 | #define MDIO_RX0_RX_STATUS 0x10 | ||
5600 | #define MDIO_RX0_RX_STATUS_SIGDET 0x8000 | ||
5601 | #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 | ||
5599 | #define MDIO_RX0_RX_EQ_BOOST 0x1c | 5602 | #define MDIO_RX0_RX_EQ_BOOST 0x1c |
5600 | #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | 5603 | #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 |
5601 | #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 | 5604 | #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 |
@@ -5789,12 +5792,22 @@ | |||
5789 | #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 | 5792 | #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 |
5790 | #define MDIO_OVER_1G_LP_UP3 0x1E | 5793 | #define MDIO_OVER_1G_LP_UP3 0x1E |
5791 | 5794 | ||
5795 | #define MDIO_REG_BANK_REMOTE_PHY 0x8330 | ||
5796 | #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 | ||
5797 | #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 | ||
5798 | #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 | ||
5799 | |||
5792 | #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 | 5800 | #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 |
5793 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 | 5801 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 |
5794 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 | 5802 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 |
5795 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 | 5803 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 |
5796 | 5804 | ||
5797 | #define MDIO_REG_BANK_CL73_USERB0 0x8370 | 5805 | #define MDIO_REG_BANK_CL73_USERB0 0x8370 |
5806 | #define MDIO_CL73_USERB0_CL73_UCTRL 0x10 | ||
5807 | #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 | ||
5808 | #define MDIO_CL73_USERB0_CL73_USTAT1 0x11 | ||
5809 | #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 | ||
5810 | #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 | ||
5798 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 | 5811 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 |
5799 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 | 5812 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 |
5800 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 | 5813 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 |