bnx2x: Add dual-media changes

Add required changes in order to support dual-media boards.

Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 25 insertions, 0 deletions

diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index 398cf55b8e1..f0a69563b66 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -4964,6 +4964,8 @@
 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN                  0x0001
 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR                 0x0040
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1                     0x14
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII                       0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK                        0x0002
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX                      0x0004
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK                  0x0018
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT                 3
@@ -5192,6 +5194,8 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_XS_8706_REG_BANK_RX3       0x80ec
 #define MDIO_XS_8706_REG_BANK_RXA       0x80fc
 
+#define MDIO_XS_REG_8073_RX_CTRL_PCIE   0x80FA
+
 #define MDIO_AN_DEVAD                   0x7
 /*ieee*/
 #define MDIO_AN_REG_CTRL                0x0000
@@ -5227,6 +5231,27 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_AN_REG_8481_AUX_CTRL               0xfff8
 #define MDIO_AN_REG_8481_LEGACY_SHADOW          0xfffc
 
+/* BCM84823 only */
+#define MDIO_CTL_DEVAD                  0x1e
+#define MDIO_CTL_REG_84823_MEDIA                0x401a
+#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK               0x0018
+        /* These pins configure the BCM84823 interface to MAC after reset. */
+#define MDIO_CTL_REG_84823_CTRL_MAC_XFI                 0x0008
+#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M             0x0010
+        /* These pins configure the BCM84823 interface to Line after reset. */
+#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK              0x0060
+#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L            0x0020
+#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI               0x0040
+        /* When this pin is active high during reset, 10GBASE-T core is power
+         * down, When it is active low the 10GBASE-T is power up
+         */
+#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN       0x0080
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK          0x0100
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER        0x0000
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER         0x0100
+#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G                       0x1000
+
+
 #define IGU_FUNC_BASE                   0x0400
 
 #define IGU_ADDR_MSIX                   0x0000