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authorMichael Chan <mchan@broadcom.com>2006-11-19 17:14:35 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2006-12-03 00:24:32 -0500
commitd43584c8bf851145ed7ec6d148916a01979040f4 (patch)
tree1c2fc3ec23e3dd94123fcb12a34b4b2e4f8399da /drivers/net/bnx2.c
parent5793bfe19beaa3c804fa2d33af238bf51bf28211 (diff)
[BNX2]: Download 5709 firmware.
Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c42
1 files changed, 38 insertions, 4 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 52fe620e1a4..92897efbc26 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -53,6 +53,7 @@
53 53
54#include "bnx2.h" 54#include "bnx2.h"
55#include "bnx2_fw.h" 55#include "bnx2_fw.h"
56#include "bnx2_fw2.h"
56 57
57#define DRV_MODULE_NAME "bnx2" 58#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": " 59#define PFX DRV_MODULE_NAME ": "
@@ -2410,7 +2411,10 @@ bnx2_init_cpus(struct bnx2 *bp)
2410 cpu_reg.spad_base = BNX2_RXP_SCRATCH; 2411 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2411 cpu_reg.mips_view_base = 0x8000000; 2412 cpu_reg.mips_view_base = 0x8000000;
2412 2413
2413 fw = &bnx2_rxp_fw_06; 2414 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2415 fw = &bnx2_rxp_fw_09;
2416 else
2417 fw = &bnx2_rxp_fw_06;
2414 2418
2415 rc = load_cpu_fw(bp, &cpu_reg, fw); 2419 rc = load_cpu_fw(bp, &cpu_reg, fw);
2416 if (rc) 2420 if (rc)
@@ -2430,7 +2434,10 @@ bnx2_init_cpus(struct bnx2 *bp)
2430 cpu_reg.spad_base = BNX2_TXP_SCRATCH; 2434 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2431 cpu_reg.mips_view_base = 0x8000000; 2435 cpu_reg.mips_view_base = 0x8000000;
2432 2436
2433 fw = &bnx2_txp_fw_06; 2437 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2438 fw = &bnx2_txp_fw_09;
2439 else
2440 fw = &bnx2_txp_fw_06;
2434 2441
2435 rc = load_cpu_fw(bp, &cpu_reg, fw); 2442 rc = load_cpu_fw(bp, &cpu_reg, fw);
2436 if (rc) 2443 if (rc)
@@ -2450,7 +2457,10 @@ bnx2_init_cpus(struct bnx2 *bp)
2450 cpu_reg.spad_base = BNX2_TPAT_SCRATCH; 2457 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2451 cpu_reg.mips_view_base = 0x8000000; 2458 cpu_reg.mips_view_base = 0x8000000;
2452 2459
2453 fw = &bnx2_tpat_fw_06; 2460 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2461 fw = &bnx2_tpat_fw_09;
2462 else
2463 fw = &bnx2_tpat_fw_06;
2454 2464
2455 rc = load_cpu_fw(bp, &cpu_reg, fw); 2465 rc = load_cpu_fw(bp, &cpu_reg, fw);
2456 if (rc) 2466 if (rc)
@@ -2470,12 +2480,36 @@ bnx2_init_cpus(struct bnx2 *bp)
2470 cpu_reg.spad_base = BNX2_COM_SCRATCH; 2480 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2471 cpu_reg.mips_view_base = 0x8000000; 2481 cpu_reg.mips_view_base = 0x8000000;
2472 2482
2473 fw = &bnx2_com_fw_06; 2483 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2484 fw = &bnx2_com_fw_09;
2485 else
2486 fw = &bnx2_com_fw_06;
2474 2487
2475 rc = load_cpu_fw(bp, &cpu_reg, fw); 2488 rc = load_cpu_fw(bp, &cpu_reg, fw);
2476 if (rc) 2489 if (rc)
2477 goto init_cpu_err; 2490 goto init_cpu_err;
2478 2491
2492 /* Initialize the Command Processor. */
2493 cpu_reg.mode = BNX2_CP_CPU_MODE;
2494 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
2495 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
2496 cpu_reg.state = BNX2_CP_CPU_STATE;
2497 cpu_reg.state_value_clear = 0xffffff;
2498 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
2499 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
2500 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
2501 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
2502 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
2503 cpu_reg.spad_base = BNX2_CP_SCRATCH;
2504 cpu_reg.mips_view_base = 0x8000000;
2505
2506 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2507 fw = &bnx2_cp_fw_09;
2508
2509 load_cpu_fw(bp, &cpu_reg, fw);
2510 if (rc)
2511 goto init_cpu_err;
2512 }
2479init_cpu_err: 2513init_cpu_err:
2480 bnx2_gunzip_end(bp); 2514 bnx2_gunzip_end(bp);
2481 return rc; 2515 return rc;