diff options
author | Mike Hench <mhench@engagenet.com> | 2008-03-19 13:40:15 -0400 |
---|---|---|
committer | David Woodhouse <dwmw2@infradead.org> | 2008-04-22 15:52:09 -0400 |
commit | 1938de46cb7e108120ffbf5155678a2a5e05b377 (patch) | |
tree | 6b61e7b2bf6f40b6a4d412720035fa462005e4d0 /drivers/mtd/nand | |
parent | 9ebed3e60f9991e980e6c38b0edbdf9c8ff2ff6d (diff) |
[MTD] [NAND] corrected MPC8313 NAND fixes
Fix a race condition in fsl_elbc_run_command
Fix incorrect usage of clearbits32 that bashed option register
Remove work around for bashed register
Signed-off-by: Mike Hench <mhench@elutions.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r-- | drivers/mtd/nand/fsl_elbc_nand.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index cb12b67ce5e..919c192b8f2 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c | |||
@@ -184,11 +184,11 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) | |||
184 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), | 184 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), |
185 | in_be32(&lbc->fbcr), priv->bank); | 185 | in_be32(&lbc->fbcr), priv->bank); |
186 | 186 | ||
187 | ctrl->irq_status = 0; | ||
187 | /* execute special operation */ | 188 | /* execute special operation */ |
188 | out_be32(&lbc->lsor, priv->bank); | 189 | out_be32(&lbc->lsor, priv->bank); |
189 | 190 | ||
190 | /* wait for FCM complete flag or timeout */ | 191 | /* wait for FCM complete flag or timeout */ |
191 | ctrl->irq_status = 0; | ||
192 | wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, | 192 | wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, |
193 | FCM_TIMEOUT_MSECS * HZ/1000); | 193 | FCM_TIMEOUT_MSECS * HZ/1000); |
194 | ctrl->status = ctrl->irq_status; | 194 | ctrl->status = ctrl->irq_status; |
@@ -667,7 +667,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |||
667 | /* adjust Option Register and ECC to match Flash page size */ | 667 | /* adjust Option Register and ECC to match Flash page size */ |
668 | if (mtd->writesize == 512) { | 668 | if (mtd->writesize == 512) { |
669 | priv->page_size = 0; | 669 | priv->page_size = 0; |
670 | clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS); | 670 | clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
671 | } else if (mtd->writesize == 2048) { | 671 | } else if (mtd->writesize == 2048) { |
672 | priv->page_size = 1; | 672 | priv->page_size = 1; |
673 | setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); | 673 | setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
@@ -688,11 +688,6 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |||
688 | return -1; | 688 | return -1; |
689 | } | 689 | } |
690 | 690 | ||
691 | /* The default u-boot configuration on MPC8313ERDB causes errors; | ||
692 | * more delay is needed. This should be safe for other boards | ||
693 | * as well. | ||
694 | */ | ||
695 | setbits32(&lbc->bank[priv->bank].or, 0x70); | ||
696 | return 0; | 691 | return 0; |
697 | } | 692 | } |
698 | 693 | ||