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authorDavid Woodhouse <dwmw2@infradead.org>2007-05-02 07:04:57 -0400
committerDavid Woodhouse <dwmw2@infradead.org>2007-05-02 07:04:57 -0400
commit14448005abd10887a2d361e20e04760dc3d8482f (patch)
tree78db8f161d5017a2197a22ee5d8c83a04116376f /drivers/mtd/nand/cafe.c
parent8c61b7a7f4d4e46be61cf1777361749b2d300c14 (diff)
[MTD] [NAND] Rename cafe.c to cafe_nand.c and remove the multi-obj magic
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'drivers/mtd/nand/cafe.c')
-rw-r--r--drivers/mtd/nand/cafe.c838
1 files changed, 0 insertions, 838 deletions
diff --git a/drivers/mtd/nand/cafe.c b/drivers/mtd/nand/cafe.c
deleted file mode 100644
index 05f6ec9f5aa..00000000000
--- a/drivers/mtd/nand/cafe.c
+++ /dev/null
@@ -1,838 +0,0 @@
1/*
2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
3 *
4 * Copyright © 2006 Red Hat, Inc.
5 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
6 */
7
8#define DEBUG
9
10#include <linux/device.h>
11#undef DEBUG
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/nand.h>
14#include <linux/rslib.h>
15#include <linux/pci.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/dma-mapping.h>
19#include <asm/io.h>
20
21#define CAFE_NAND_CTRL1 0x00
22#define CAFE_NAND_CTRL2 0x04
23#define CAFE_NAND_CTRL3 0x08
24#define CAFE_NAND_STATUS 0x0c
25#define CAFE_NAND_IRQ 0x10
26#define CAFE_NAND_IRQ_MASK 0x14
27#define CAFE_NAND_DATA_LEN 0x18
28#define CAFE_NAND_ADDR1 0x1c
29#define CAFE_NAND_ADDR2 0x20
30#define CAFE_NAND_TIMING1 0x24
31#define CAFE_NAND_TIMING2 0x28
32#define CAFE_NAND_TIMING3 0x2c
33#define CAFE_NAND_NONMEM 0x30
34#define CAFE_NAND_ECC_RESULT 0x3C
35#define CAFE_NAND_DMA_CTRL 0x40
36#define CAFE_NAND_DMA_ADDR0 0x44
37#define CAFE_NAND_DMA_ADDR1 0x48
38#define CAFE_NAND_ECC_SYN01 0x50
39#define CAFE_NAND_ECC_SYN23 0x54
40#define CAFE_NAND_ECC_SYN45 0x58
41#define CAFE_NAND_ECC_SYN67 0x5c
42#define CAFE_NAND_READ_DATA 0x1000
43#define CAFE_NAND_WRITE_DATA 0x2000
44
45#define CAFE_GLOBAL_CTRL 0x3004
46#define CAFE_GLOBAL_IRQ 0x3008
47#define CAFE_GLOBAL_IRQ_MASK 0x300c
48#define CAFE_NAND_RESET 0x3034
49
50struct cafe_priv {
51 struct nand_chip nand;
52 struct pci_dev *pdev;
53 void __iomem *mmio;
54 struct rs_control *rs;
55 uint32_t ctl1;
56 uint32_t ctl2;
57 int datalen;
58 int nr_data;
59 int data_pos;
60 int page_addr;
61 dma_addr_t dmaaddr;
62 unsigned char *dmabuf;
63};
64
65static int usedma = 1;
66module_param(usedma, int, 0644);
67
68static int skipbbt = 0;
69module_param(skipbbt, int, 0644);
70
71static int debug = 0;
72module_param(debug, int, 0644);
73
74static int regdebug = 0;
75module_param(regdebug, int, 0644);
76
77static int checkecc = 1;
78module_param(checkecc, int, 0644);
79
80static int numtimings;
81static int timing[3];
82module_param_array(timing, int, &numtimings, 0644);
83
84/* Hrm. Why isn't this already conditional on something in the struct device? */
85#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
86
87/* Make it easier to switch to PIO if we need to */
88#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
89#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
90
91static int cafe_device_ready(struct mtd_info *mtd)
92{
93 struct cafe_priv *cafe = mtd->priv;
94 int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
95 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
96
97 cafe_writel(cafe, irqs, NAND_IRQ);
98
99 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
100 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
101 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
102
103 return result;
104}
105
106
107static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
108{
109 struct cafe_priv *cafe = mtd->priv;
110
111 if (usedma)
112 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
113 else
114 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
115
116 cafe->datalen += len;
117
118 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
119 len, cafe->datalen);
120}
121
122static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
123{
124 struct cafe_priv *cafe = mtd->priv;
125
126 if (usedma)
127 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
128 else
129 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
130
131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
132 len, cafe->datalen);
133 cafe->datalen += len;
134}
135
136static uint8_t cafe_read_byte(struct mtd_info *mtd)
137{
138 struct cafe_priv *cafe = mtd->priv;
139 uint8_t d;
140
141 cafe_read_buf(mtd, &d, 1);
142 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
143
144 return d;
145}
146
147static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
148 int column, int page_addr)
149{
150 struct cafe_priv *cafe = mtd->priv;
151 int adrbytes = 0;
152 uint32_t ctl1;
153 uint32_t doneint = 0x80000000;
154
155 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
156 command, column, page_addr);
157
158 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
159 /* Second half of a command we already calculated */
160 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
161 ctl1 = cafe->ctl1;
162 cafe->ctl2 &= ~(1<<30);
163 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
164 cafe->ctl1, cafe->nr_data);
165 goto do_command;
166 }
167 /* Reset ECC engine */
168 cafe_writel(cafe, 0, NAND_CTRL2);
169
170 /* Emulate NAND_CMD_READOOB on large-page chips */
171 if (mtd->writesize > 512 &&
172 command == NAND_CMD_READOOB) {
173 column += mtd->writesize;
174 command = NAND_CMD_READ0;
175 }
176
177 /* FIXME: Do we need to send read command before sending data
178 for small-page chips, to position the buffer correctly? */
179
180 if (column != -1) {
181 cafe_writel(cafe, column, NAND_ADDR1);
182 adrbytes = 2;
183 if (page_addr != -1)
184 goto write_adr2;
185 } else if (page_addr != -1) {
186 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
187 page_addr >>= 16;
188 write_adr2:
189 cafe_writel(cafe, page_addr, NAND_ADDR2);
190 adrbytes += 2;
191 if (mtd->size > mtd->writesize << 16)
192 adrbytes++;
193 }
194
195 cafe->data_pos = cafe->datalen = 0;
196
197 /* Set command valid bit */
198 ctl1 = 0x80000000 | command;
199
200 /* Set RD or WR bits as appropriate */
201 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
202 ctl1 |= (1<<26); /* rd */
203 /* Always 5 bytes, for now */
204 cafe->datalen = 4;
205 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
206 adrbytes = 1;
207 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
208 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
209 ctl1 |= 1<<26; /* rd */
210 /* For now, assume just read to end of page */
211 cafe->datalen = mtd->writesize + mtd->oobsize - column;
212 } else if (command == NAND_CMD_SEQIN)
213 ctl1 |= 1<<25; /* wr */
214
215 /* Set number of address bytes */
216 if (adrbytes)
217 ctl1 |= ((adrbytes-1)|8) << 27;
218
219 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
220 /* Ignore the first command of a pair; the hardware
221 deals with them both at once, later */
222 cafe->ctl1 = ctl1;
223 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
224 cafe->ctl1, cafe->datalen);
225 return;
226 }
227 /* RNDOUT and READ0 commands need a following byte */
228 if (command == NAND_CMD_RNDOUT)
229 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
230 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
231 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
232
233 do_command:
234 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
235 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
236
237 /* NB: The datasheet lies -- we really should be subtracting 1 here */
238 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
239 cafe_writel(cafe, 0x90000000, NAND_IRQ);
240 if (usedma && (ctl1 & (3<<25))) {
241 uint32_t dmactl = 0xc0000000 + cafe->datalen;
242 /* If WR or RD bits set, set up DMA */
243 if (ctl1 & (1<<26)) {
244 /* It's a read */
245 dmactl |= (1<<29);
246 /* ... so it's done when the DMA is done, not just
247 the command. */
248 doneint = 0x10000000;
249 }
250 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
251 }
252 cafe->datalen = 0;
253
254 if (unlikely(regdebug)) {
255 int i;
256 printk("About to write command %08x to register 0\n", ctl1);
257 for (i=4; i< 0x5c; i+=4)
258 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
259 }
260
261 cafe_writel(cafe, ctl1, NAND_CTRL1);
262 /* Apply this short delay always to ensure that we do wait tWB in
263 * any case on any machine. */
264 ndelay(100);
265
266 if (1) {
267 int c;
268 uint32_t irqs;
269
270 for (c = 500000; c != 0; c--) {
271 irqs = cafe_readl(cafe, NAND_IRQ);
272 if (irqs & doneint)
273 break;
274 udelay(1);
275 if (!(c % 100000))
276 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
277 cpu_relax();
278 }
279 cafe_writel(cafe, doneint, NAND_IRQ);
280 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
281 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
282 }
283
284 WARN_ON(cafe->ctl2 & (1<<30));
285
286 switch (command) {
287
288 case NAND_CMD_CACHEDPROG:
289 case NAND_CMD_PAGEPROG:
290 case NAND_CMD_ERASE1:
291 case NAND_CMD_ERASE2:
292 case NAND_CMD_SEQIN:
293 case NAND_CMD_RNDIN:
294 case NAND_CMD_STATUS:
295 case NAND_CMD_DEPLETE1:
296 case NAND_CMD_RNDOUT:
297 case NAND_CMD_STATUS_ERROR:
298 case NAND_CMD_STATUS_ERROR0:
299 case NAND_CMD_STATUS_ERROR1:
300 case NAND_CMD_STATUS_ERROR2:
301 case NAND_CMD_STATUS_ERROR3:
302 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
303 return;
304 }
305 nand_wait_ready(mtd);
306 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
307}
308
309static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
310{
311 //struct cafe_priv *cafe = mtd->priv;
312 // cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
313}
314
315static int cafe_nand_interrupt(int irq, void *id)
316{
317 struct mtd_info *mtd = id;
318 struct cafe_priv *cafe = mtd->priv;
319 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
320 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
321 if (!irqs)
322 return IRQ_NONE;
323
324 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
325 return IRQ_HANDLED;
326}
327
328static void cafe_nand_bug(struct mtd_info *mtd)
329{
330 BUG();
331}
332
333static int cafe_nand_write_oob(struct mtd_info *mtd,
334 struct nand_chip *chip, int page)
335{
336 int status = 0;
337
338 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
339 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
340 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
341 status = chip->waitfunc(mtd, chip);
342
343 return status & NAND_STATUS_FAIL ? -EIO : 0;
344}
345
346/* Don't use -- use nand_read_oob_std for now */
347static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
348 int page, int sndcmd)
349{
350 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
351 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
352 return 1;
353}
354/**
355 * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
356 * @mtd: mtd info structure
357 * @chip: nand chip info structure
358 * @buf: buffer to store read data
359 *
360 * The hw generator calculates the error syndrome automatically. Therefor
361 * we need a special oob layout and handling.
362 */
363static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
364 uint8_t *buf)
365{
366 struct cafe_priv *cafe = mtd->priv;
367
368 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
369 cafe_readl(cafe, NAND_ECC_RESULT),
370 cafe_readl(cafe, NAND_ECC_SYN01));
371
372 chip->read_buf(mtd, buf, mtd->writesize);
373 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
374
375 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
376 unsigned short syn[8], pat[4];
377 int pos[4];
378 u8 *oob = chip->oob_poi;
379 int i, n;
380
381 for (i=0; i<8; i+=2) {
382 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
383 syn[i] = cafe->rs->index_of[tmp & 0xfff];
384 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
385 }
386
387 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
388 pat);
389
390 for (i = 0; i < n; i++) {
391 int p = pos[i];
392
393 /* The 12-bit symbols are mapped to bytes here */
394
395 if (p > 1374) {
396 /* out of range */
397 n = -1374;
398 } else if (p == 0) {
399 /* high four bits do not correspond to data */
400 if (pat[i] > 0xff)
401 n = -2048;
402 else
403 buf[0] ^= pat[i];
404 } else if (p == 1365) {
405 buf[2047] ^= pat[i] >> 4;
406 oob[0] ^= pat[i] << 4;
407 } else if (p > 1365) {
408 if ((p & 1) == 1) {
409 oob[3*p/2 - 2048] ^= pat[i] >> 4;
410 oob[3*p/2 - 2047] ^= pat[i] << 4;
411 } else {
412 oob[3*p/2 - 2049] ^= pat[i] >> 8;
413 oob[3*p/2 - 2048] ^= pat[i];
414 }
415 } else if ((p & 1) == 1) {
416 buf[3*p/2] ^= pat[i] >> 4;
417 buf[3*p/2 + 1] ^= pat[i] << 4;
418 } else {
419 buf[3*p/2 - 1] ^= pat[i] >> 8;
420 buf[3*p/2] ^= pat[i];
421 }
422 }
423
424 if (n < 0) {
425 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
426 cafe_readl(cafe, NAND_ADDR2) * 2048);
427 for (i = 0; i < 0x5c; i += 4)
428 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
429 mtd->ecc_stats.failed++;
430 } else {
431 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
432 mtd->ecc_stats.corrected += n;
433 }
434 }
435
436 return 0;
437}
438
439static struct nand_ecclayout cafe_oobinfo_2048 = {
440 .eccbytes = 14,
441 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
442 .oobfree = {{14, 50}}
443};
444
445/* Ick. The BBT code really ought to be able to work this bit out
446 for itself from the above, at least for the 2KiB case */
447static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
448static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
449
450static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
451static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
452
453
454static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
455 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
456 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
457 .offs = 14,
458 .len = 4,
459 .veroffs = 18,
460 .maxblocks = 4,
461 .pattern = cafe_bbt_pattern_2048
462};
463
464static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
465 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
466 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
467 .offs = 14,
468 .len = 4,
469 .veroffs = 18,
470 .maxblocks = 4,
471 .pattern = cafe_mirror_pattern_2048
472};
473
474static struct nand_ecclayout cafe_oobinfo_512 = {
475 .eccbytes = 14,
476 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
477 .oobfree = {{14, 2}}
478};
479
480static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
481 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
482 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
483 .offs = 14,
484 .len = 1,
485 .veroffs = 15,
486 .maxblocks = 4,
487 .pattern = cafe_bbt_pattern_512
488};
489
490static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
491 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
492 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
493 .offs = 14,
494 .len = 1,
495 .veroffs = 15,
496 .maxblocks = 4,
497 .pattern = cafe_mirror_pattern_512
498};
499
500
501static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
502 struct nand_chip *chip, const uint8_t *buf)
503{
504 struct cafe_priv *cafe = mtd->priv;
505
506 chip->write_buf(mtd, buf, mtd->writesize);
507 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
508
509 /* Set up ECC autogeneration */
510 cafe->ctl2 |= (1<<30);
511}
512
513static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
514 const uint8_t *buf, int page, int cached, int raw)
515{
516 int status;
517
518 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
519
520 if (unlikely(raw))
521 chip->ecc.write_page_raw(mtd, chip, buf);
522 else
523 chip->ecc.write_page(mtd, chip, buf);
524
525 /*
526 * Cached progamming disabled for now, Not sure if its worth the
527 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
528 */
529 cached = 0;
530
531 if (!cached || !(chip->options & NAND_CACHEPRG)) {
532
533 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
534 status = chip->waitfunc(mtd, chip);
535 /*
536 * See if operation failed and additional status checks are
537 * available
538 */
539 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
540 status = chip->errstat(mtd, chip, FL_WRITING, status,
541 page);
542
543 if (status & NAND_STATUS_FAIL)
544 return -EIO;
545 } else {
546 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
547 status = chip->waitfunc(mtd, chip);
548 }
549
550#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
551 /* Send command to read back the data */
552 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
553
554 if (chip->verify_buf(mtd, buf, mtd->writesize))
555 return -EIO;
556#endif
557 return 0;
558}
559
560static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
561{
562 return 0;
563}
564
565/* F_2[X]/(X**6+X+1) */
566static unsigned short __devinit gf64_mul(u8 a, u8 b)
567{
568 u8 c;
569 unsigned int i;
570
571 c = 0;
572 for (i = 0; i < 6; i++) {
573 if (a & 1)
574 c ^= b;
575 a >>= 1;
576 b <<= 1;
577 if ((b & 0x40) != 0)
578 b ^= 0x43;
579 }
580
581 return c;
582}
583
584/* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
585static u16 __devinit gf4096_mul(u16 a, u16 b)
586{
587 u8 ah, al, bh, bl, ch, cl;
588
589 ah = a >> 6;
590 al = a & 0x3f;
591 bh = b >> 6;
592 bl = b & 0x3f;
593
594 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
595 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
596
597 return (ch << 6) ^ cl;
598}
599
600static int __devinit cafe_mul(int x)
601{
602 if (x == 0)
603 return 1;
604 return gf4096_mul(x, 0xe01);
605}
606
607static int __devinit cafe_nand_probe(struct pci_dev *pdev,
608 const struct pci_device_id *ent)
609{
610 struct mtd_info *mtd;
611 struct cafe_priv *cafe;
612 uint32_t ctrl;
613 int err = 0;
614
615 err = pci_enable_device(pdev);
616 if (err)
617 return err;
618
619 pci_set_master(pdev);
620
621 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
622 if (!mtd) {
623 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
624 return -ENOMEM;
625 }
626 cafe = (void *)(&mtd[1]);
627
628 mtd->priv = cafe;
629 mtd->owner = THIS_MODULE;
630
631 cafe->pdev = pdev;
632 cafe->mmio = pci_iomap(pdev, 0, 0);
633 if (!cafe->mmio) {
634 dev_warn(&pdev->dev, "failed to iomap\n");
635 err = -ENOMEM;
636 goto out_free_mtd;
637 }
638 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
639 &cafe->dmaaddr, GFP_KERNEL);
640 if (!cafe->dmabuf) {
641 err = -ENOMEM;
642 goto out_ior;
643 }
644 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
645
646 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
647 if (!cafe->rs) {
648 err = -ENOMEM;
649 goto out_ior;
650 }
651
652 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
653 cafe->nand.dev_ready = cafe_device_ready;
654 cafe->nand.read_byte = cafe_read_byte;
655 cafe->nand.read_buf = cafe_read_buf;
656 cafe->nand.write_buf = cafe_write_buf;
657 cafe->nand.select_chip = cafe_select_chip;
658
659 cafe->nand.chip_delay = 0;
660
661 /* Enable the following for a flash based bad block table */
662 cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
663
664 if (skipbbt) {
665 cafe->nand.options |= NAND_SKIP_BBTSCAN;
666 cafe->nand.block_bad = cafe_nand_block_bad;
667 }
668
669 if (numtimings && numtimings != 3) {
670 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
671 }
672
673 if (numtimings == 3) {
674 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
675 timing[0], timing[1], timing[2]);
676 } else {
677 timing[0] = cafe_readl(cafe, NAND_TIMING1);
678 timing[1] = cafe_readl(cafe, NAND_TIMING2);
679 timing[2] = cafe_readl(cafe, NAND_TIMING3);
680
681 if (timing[0] | timing[1] | timing[2]) {
682 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
683 timing[0], timing[1], timing[2]);
684 } else {
685 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
686 timing[0] = timing[1] = timing[2] = 0xffffffff;
687 }
688 }
689
690 /* Start off by resetting the NAND controller completely */
691 cafe_writel(cafe, 1, NAND_RESET);
692 cafe_writel(cafe, 0, NAND_RESET);
693
694 cafe_writel(cafe, timing[0], NAND_TIMING1);
695 cafe_writel(cafe, timing[1], NAND_TIMING2);
696 cafe_writel(cafe, timing[2], NAND_TIMING3);
697
698 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
699 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
700 "CAFE NAND", mtd);
701 if (err) {
702 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
703 goto out_free_dma;
704 }
705
706 /* Disable master reset, enable NAND clock */
707 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
708 ctrl &= 0xffffeff0;
709 ctrl |= 0x00007000;
710 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
711 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
712 cafe_writel(cafe, 0, NAND_DMA_CTRL);
713
714 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
715 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
716
717 /* Set up DMA address */
718 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
719 if (sizeof(cafe->dmaaddr) > 4)
720 /* Shift in two parts to shut the compiler up */
721 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
722 else
723 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
724
725 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
726 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
727
728 /* Enable NAND IRQ in global IRQ mask register */
729 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
730 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
731 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
732
733 /* Scan to find existence of the device */
734 if (nand_scan_ident(mtd, 1)) {
735 err = -ENXIO;
736 goto out_irq;
737 }
738
739 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
740 if (mtd->writesize == 2048)
741 cafe->ctl2 |= 1<<29; /* 2KiB page size */
742
743 /* Set up ECC according to the type of chip we found */
744 if (mtd->writesize == 2048) {
745 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
746 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
747 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
748 } else if (mtd->writesize == 512) {
749 cafe->nand.ecc.layout = &cafe_oobinfo_512;
750 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
751 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
752 } else {
753 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
754 mtd->writesize);
755 goto out_irq;
756 }
757 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
758 cafe->nand.ecc.size = mtd->writesize;
759 cafe->nand.ecc.bytes = 14;
760 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
761 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
762 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
763 cafe->nand.write_page = cafe_nand_write_page;
764 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
765 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
766 cafe->nand.ecc.read_page = cafe_nand_read_page;
767 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
768
769 err = nand_scan_tail(mtd);
770 if (err)
771 goto out_irq;
772
773 pci_set_drvdata(pdev, mtd);
774 add_mtd_device(mtd);
775 goto out;
776
777 out_irq:
778 /* Disable NAND IRQ in global IRQ mask register */
779 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
780 free_irq(pdev->irq, mtd);
781 out_free_dma:
782 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
783 out_ior:
784 pci_iounmap(pdev, cafe->mmio);
785 out_free_mtd:
786 kfree(mtd);
787 out:
788 return err;
789}
790
791static void __devexit cafe_nand_remove(struct pci_dev *pdev)
792{
793 struct mtd_info *mtd = pci_get_drvdata(pdev);
794 struct cafe_priv *cafe = mtd->priv;
795
796 del_mtd_device(mtd);
797 /* Disable NAND IRQ in global IRQ mask register */
798 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
799 free_irq(pdev->irq, mtd);
800 nand_release(mtd);
801 free_rs(cafe->rs);
802 pci_iounmap(pdev, cafe->mmio);
803 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
804 kfree(mtd);
805}
806
807static struct pci_device_id cafe_nand_tbl[] = {
808 { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
809};
810
811MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
812
813static struct pci_driver cafe_nand_pci_driver = {
814 .name = "CAFÉ NAND",
815 .id_table = cafe_nand_tbl,
816 .probe = cafe_nand_probe,
817 .remove = __devexit_p(cafe_nand_remove),
818#ifdef CONFIG_PMx
819 .suspend = cafe_nand_suspend,
820 .resume = cafe_nand_resume,
821#endif
822};
823
824static int cafe_nand_init(void)
825{
826 return pci_register_driver(&cafe_nand_pci_driver);
827}
828
829static void cafe_nand_exit(void)
830{
831 pci_unregister_driver(&cafe_nand_pci_driver);
832}
833module_init(cafe_nand_init);
834module_exit(cafe_nand_exit);
835
836MODULE_LICENSE("GPL");
837MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
838MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 14:09:16 -0500