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authorMauro Carvalho Chehab <mchehab@infradead.org>2006-08-28 18:18:49 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2006-09-26 11:30:34 -0400
commit96ecfc4edf6bdb535b4ae3d87db2ba7f91596dd8 (patch)
treeb4ba4231a0af8f658113d7015be875e56e6ce58f /drivers/media
parent236f16d241e16b269cd00ef0116975882f498be5 (diff)
V4L/DVB (4551): Added register aliases for saa711x registers, instead of using reg numbers
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/video/saa7115.c793
-rw-r--r--drivers/media/video/saa711x_regs.h549
2 files changed, 1000 insertions, 342 deletions
diff --git a/drivers/media/video/saa7115.c b/drivers/media/video/saa7115.c
index e5558c92086..d5052dbd074 100644
--- a/drivers/media/video/saa7115.c
+++ b/drivers/media/video/saa7115.c
@@ -33,6 +33,7 @@
33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
34 */ 34 */
35 35
36#include "saa711x_regs.h"
36 37
37#include <linux/kernel.h> 38#include <linux/kernel.h>
38#include <linux/module.h> 39#include <linux/module.h>
@@ -111,385 +112,470 @@ static inline int saa7115_read(struct i2c_client *client, u8 reg)
111 112
112static const unsigned char saa7115_init_auto_input[] = { 113static const unsigned char saa7115_init_auto_input[] = {
113 /* Front-End Part */ 114 /* Front-End Part */
114 0x01, 0x48, /* white peak control disabled */ 115 R_01_INC_DELAY, 0x48, /* white peak control disabled */
115 0x03, 0x20, /* was 0x30. 0x20: long vertical blanking */ 116 R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */
116 0x04, 0x90, /* analog gain set to 0 */ 117 R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */
117 0x05, 0x90, /* analog gain set to 0 */ 118 R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */
118 /* Decoder Part */ 119 /* Decoder Part */
119 0x06, 0xeb, /* horiz sync begin = -21 */ 120 R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */
120 0x07, 0xe0, /* horiz sync stop = -17 */ 121 R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */
121 0x0a, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */ 122 R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
122 0x0b, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */ 123 R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
123 0x0c, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */ 124 R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
124 0x0d, 0x00, /* chrominance hue control */ 125 R_0D_CHROMA_HUE_CNTL, 0x00,
125 0x0f, 0x00, /* chrominance gain control: use automicatic mode */ 126 R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */
126 0x10, 0x06, /* chrominance/luminance control: active adaptive combfilter */ 127 R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */
127 0x11, 0x00, /* delay control */ 128 R_11_MODE_DELAY_CNTL, 0x00,
128 0x12, 0x9d, /* RTS0 output control: VGATE */ 129 R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */
129 0x13, 0x80, /* X-port output control: ITU656 standard mode, RTCO output enable RTCE */ 130 R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */
130 0x14, 0x00, /* analog/ADC/auto compatibility control */ 131 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
131 0x18, 0x40, /* raw data gain 0x00 = nominal */ 132 R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */
132 0x19, 0x80, /* raw data offset 0x80 = 0 LSB */ 133 R_19_RAW_DATA_OFF_CNTL, 0x80,
133 0x1a, 0x77, /* color killer level control 0x77 = recommended */ 134 R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */
134 0x1b, 0x42, /* misc chroma control 0x42 = recommended */ 135 R_1B_MISC_TVVCRDET, 0x42, /* recommended value */
135 0x1c, 0xa9, /* combfilter control 0xA9 = recommended */ 136 R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */
136 0x1d, 0x01, /* combfilter control 0x01 = recommended */ 137 R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */
137 138
138 /* Power Device Control */ 139 /* Power Device Control */
139 0x88, 0xd0, /* reset device */ 140 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */
140 0x88, 0xf0, /* set device programmed, all in operational mode */ 141 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */
141 0x00, 0x00 142 0x00, 0x00
142}; 143};
143 144
144static const unsigned char saa7115_cfg_reset_scaler[] = { 145static const unsigned char saa7115_cfg_reset_scaler[] = {
145 0x87, 0x00, /* disable I-port output */ 146 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
146 0x88, 0xd0, /* reset scaler */ 147 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
147 0x88, 0xf0, /* activate scaler */ 148 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
148 0x87, 0x01, /* enable I-port output */ 149 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */
149 0x00, 0x00 150 0x00, 0x00
150}; 151};
151 152
152/* ============== SAA7715 VIDEO templates ============= */ 153/* ============== SAA7715 VIDEO templates ============= */
153 154
154static const unsigned char saa7115_cfg_60hz_fullres_x[] = { 155static const unsigned char saa7115_cfg_60hz_fullres_x[] = {
155 0xcc, 0xd0, /* hsize low (output), hor. output window size = 0x2d0 = 720 */ 156 /* hsize = 0x2d0 = 720 */
156 0xcd, 0x02, /* hsize hi (output) */ 157 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
158 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
157 159
158 /* Why not in 60hz-Land, too? */ 160 /* Why not in 60hz-Land, too? */
159 0xd0, 0x01, /* downscale = 1 */ 161 R_D0_B_HORIZ_PRESCALING, 0x01, /* downscale = 1 */
160 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ 162 /* hor lum scaling 0x0400 = 1 */
161 0xd9, 0x04, 163 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
162 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ 164 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
163 0xdd, 0x02, /* H-scaling incr chroma */ 165
166 /* must be hor lum scaling / 2 */
167 R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
168 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
164 169
165 0x00, 0x00 170 0x00, 0x00
166}; 171};
172
167static const unsigned char saa7115_cfg_60hz_fullres_y[] = { 173static const unsigned char saa7115_cfg_60hz_fullres_y[] = {
168 0xce, 0xf8, /* vsize low (output), ver. output window size = 248 (but 60hz is 240?) */ 174 /* output window size = 248 (but 60hz is 240?) */
169 0xcf, 0x00, /* vsize hi (output) */ 175 R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0xf8,
176 R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
170 177
171 /* Why not in 60hz-Land, too? */ 178 /* Why not in 60hz-Land, too? */
172 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ 179 R_D5_B_LUMA_CONTRAST_CNTL, 0x40, /* Lum contrast, nominal value = 0x40 */
173 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ 180 R_D6_B_CHROMA_SATURATION_CNTL, 0x40, /* Chroma satur. nominal value = 0x80 */
174 181
175 0xe0, 0x00, /* V-scaling incr luma low */ 182 R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
176 0xe1, 0x04, /* " hi */ 183 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
177 0xe2, 0x00, /* V-scaling incr chroma low */ 184
178 0xe3, 0x04, /* " hi */ 185 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
186 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
179 187
180 0x00, 0x00 188 0x00, 0x00
181}; 189};
182 190
183static const unsigned char saa7115_cfg_60hz_video[] = { 191static const unsigned char saa7115_cfg_60hz_video[] = {
184 0x80, 0x00, /* reset tasks */ 192 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
185 0x88, 0xd0, /* reset scaler */ 193 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
186 194
187 0x15, 0x03, /* VGATE pulse start */ 195 R_15_VGATE_START_FID_CHG, 0x03,
188 0x16, 0x11, /* VGATE pulse stop */ 196 R_16_VGATE_STOP, 0x11,
189 0x17, 0x9c, /* VGATE MSB and other values */ 197 R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
190 198
191 0x08, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ 199 R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
192 0x0e, 0x07, /* lots of different stuff... video autodetection is on */ 200 R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */
193 201
194 0x5a, 0x06, /* Vertical offset, standard 60hz value for ITU656 line counting */ 202 R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */
195 203
196 /* Task A */ 204 /* Task A */
197 0x90, 0x80, /* Task Handling Control */ 205 R_90_A_TASK_HANDLING_CNTL, 0x80,
198 0x91, 0x48, /* X-port formats/config */ 206 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
199 0x92, 0x40, /* Input Ref. signal Def. */ 207 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
200 0x93, 0x84, /* I-port config */ 208 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
201 0x94, 0x01, /* hoffset low (input), 0x0002 is minimum */ 209
202 0x95, 0x00, /* hoffset hi (input) */ 210 /* hoffset low (input), 0x0002 is minimum */
203 0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */ 211 R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
204 0x97, 0x02, /* hsize hi (input) */ 212 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
205 0x98, 0x05, /* voffset low (input) */ 213
206 0x99, 0x00, /* voffset hi (input) */ 214 /* hsize low (input), 0x02d0 = 720 */
207 0x9a, 0x0c, /* vsize low (input), 0x0c = 12 */ 215 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
208 0x9b, 0x00, /* vsize hi (input) */ 216 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
209 0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */ 217
210 0x9d, 0x05, /* hsize hi (output) */ 218 R_98_A_VERT_INPUT_WINDOW_START, 0x05,
211 0x9e, 0x0c, /* vsize low (output), 0x0c = 12 */ 219 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
212 0x9f, 0x00, /* vsize hi (output) */ 220
221 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
222 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
223
224 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
225 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
226
227 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
228 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
213 229
214 /* Task B */ 230 /* Task B */
215 0xc0, 0x00, /* Task Handling Control */ 231 R_C0_B_TASK_HANDLING_CNTL, 0x00,
216 0xc1, 0x08, /* X-port formats/config */ 232 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
217 0xc2, 0x00, /* Input Ref. signal Def. */ 233 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
218 0xc3, 0x80, /* I-port config */ 234 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
219 0xc4, 0x02, /* hoffset low (input), 0x0002 is minimum */ 235
220 0xc5, 0x00, /* hoffset hi (input) */ 236 /* 0x0002 is minimum */
221 0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */ 237 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
222 0xc7, 0x02, /* hsize hi (input) */ 238 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
223 0xc8, 0x12, /* voffset low (input), 0x12 = 18 */ 239
224 0xc9, 0x00, /* voffset hi (input) */ 240 /* 0x02d0 = 720 */
225 0xca, 0xf8, /* vsize low (input), 0xf8 = 248 */ 241 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
226 0xcb, 0x00, /* vsize hi (input) */ 242 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
227 0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */ 243
228 0xcd, 0x02, /* hsize hi (output) */ 244 /* vwindow start 0x12 = 18 */
229 245 R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
230 0xf0, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */ 246 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
231 0xf1, 0x05, /* low bit with 0xF0 */ 247
232 0xf5, 0xad, /* Set pulse generator register */ 248 /* vwindow length 0xf8 = 248 */
233 0xf6, 0x01, 249 R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0xf8,
234 250 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
235 0x87, 0x00, /* Disable I-port output */ 251
236 0x88, 0xd0, /* reset scaler */ 252 /* hwindow 0x02d0 = 720 */
237 0x80, 0x20, /* Activate only task "B", continuous mode (was 0xA0) */ 253 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
238 0x88, 0xf0, /* activate scaler */ 254 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
239 0x87, 0x01, /* Enable I-port output */ 255
256 R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
257 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */
258 R_F5_PULSGEN_LINE_LENGTH, 0xad,
259 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
260
261 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* Disable I-port output */
262 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
263 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B", continuous mode (was 0xA0) */
264 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
265 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
240 0x00, 0x00 266 0x00, 0x00
241}; 267};
242 268
243static const unsigned char saa7115_cfg_50hz_fullres_x[] = { 269static const unsigned char saa7115_cfg_50hz_fullres_x[] = {
244 0xcc, 0xd0, /* hsize low (output), 720 same as 60hz */ 270 /* hsize low (output), 720 same as 60hz */
245 0xcd, 0x02, /* hsize hi (output) */ 271 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
272 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
246 273
247 0xd0, 0x01, /* down scale = 1 */ 274 R_D0_B_HORIZ_PRESCALING, 0x01, /* down scale = 1 */
248 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ 275 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, /* hor lum scaling 0x0400 = 1 */
249 0xd9, 0x04, 276 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
250 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ 277
251 0xdd, 0x02, /* H-scaling incr chroma */ 278 /* must be hor lum scaling / 2 */
279 R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
280 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
252 281
253 0x00, 0x00 282 0x00, 0x00
254}; 283};
255static const unsigned char saa7115_cfg_50hz_fullres_y[] = { 284static const unsigned char saa7115_cfg_50hz_fullres_y[] = {
256 0xce, 0x20, /* vsize low (output), 0x0120 = 288 */ 285 /* vsize low (output), 0x0120 = 288 */
257 0xcf, 0x01, /* vsize hi (output) */ 286 R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
287 R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
288
289 R_D5_B_LUMA_CONTRAST_CNTL, 0x40, /* Lum contrast, nominal value = 0x40 */
290 R_D6_B_CHROMA_SATURATION_CNTL, 0x40, /* Chroma satur. nominal value = 0x80 */
258 291
259 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ 292 R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
260 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ 293 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
261 294
262 0xe0, 0x00, /* V-scaling incr luma low */ 295 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
263 0xe1, 0x04, /* " hi */ 296 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
264 0xe2, 0x00, /* V-scaling incr chroma low */
265 0xe3, 0x04, /* " hi */
266 297
267 0x00, 0x00 298 0x00, 0x00
268}; 299};
269 300
270static const unsigned char saa7115_cfg_50hz_video[] = { 301static const unsigned char saa7115_cfg_50hz_video[] = {
271 0x80, 0x00, /* reset tasks */ 302 R_80_GLOBAL_CNTL_1, 0x00,
272 0x88, 0xd0, /* reset scaler */ 303 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
273 304
274 0x15, 0x37, /* VGATE start */ 305 R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */
275 0x16, 0x16, /* VGATE stop */ 306 R_16_VGATE_STOP, 0x16,
276 0x17, 0x99, /* VGATE MSB and other values */ 307 R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
277 308
278 0x08, 0x28, /* 0x28 = PAL */ 309 R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */
279 0x0e, 0x07, /* chrominance control 1 */ 310 R_0E_CHROMA_CNTL_1, 0x07,
280 311
281 0x5a, 0x03, /* Vertical offset, standard 50hz value */ 312 R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */
282 313
283 /* Task A */ 314 /* Task A */
284 0x90, 0x81, /* Task Handling Control */ 315 R_90_A_TASK_HANDLING_CNTL, 0x81,
285 0x91, 0x48, /* X-port formats/config */ 316 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
286 0x92, 0x40, /* Input Ref. signal Def. */ 317 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
287 0x93, 0x84, /* I-port config */ 318 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
319
288 /* This is weird: the datasheet says that you should use 2 as the minimum value, */ 320 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
289 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ 321 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
290 0x94, 0x00, /* hoffset low (input), 0x0002 is minimum */ 322 /* hoffset low (input), 0x0002 is minimum */
291 0x95, 0x00, /* hoffset hi (input) */ 323 R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
292 0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */ 324 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
293 0x97, 0x02, /* hsize hi (input) */ 325
294 0x98, 0x03, /* voffset low (input) */ 326 /* hsize low (input), 0x02d0 = 720 */
295 0x99, 0x00, /* voffset hi (input) */ 327 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
296 0x9a, 0x12, /* vsize low (input), 0x12 = 18 */ 328 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
297 0x9b, 0x00, /* vsize hi (input) */ 329
298 0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */ 330 R_98_A_VERT_INPUT_WINDOW_START, 0x03,
299 0x9d, 0x05, /* hsize hi (output) */ 331 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
300 0x9e, 0x12, /* vsize low (output), 0x12 = 18 */ 332
301 0x9f, 0x00, /* vsize hi (output) */ 333 /* vsize 0x12 = 18 */
334 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
335 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
336
337 /* hsize 0x05a0 = 1440 */
338 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
339 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */
340 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */
341 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */
302 342
303 /* Task B */ 343 /* Task B */
304 0xc0, 0x00, /* Task Handling Control */ 344 R_C0_B_TASK_HANDLING_CNTL, 0x00,
305 0xc1, 0x08, /* X-port formats/config */ 345 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
306 0xc2, 0x00, /* Input Ref. signal Def. */ 346 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
307 0xc3, 0x80, /* I-port config */ 347 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
308 0xc4, 0x00, /* hoffset low (input), 0x0002 is minimum. See comment at 0x94 above. */ 348
309 0xc5, 0x00, /* hoffset hi (input) */ 349 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
310 0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */ 350 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
311 0xc7, 0x02, /* hsize hi (input) */ 351 /* hoffset low (input), 0x0002 is minimum. See comment above. */
312 0xc8, 0x16, /* voffset low (input), 0x16 = 22 */ 352 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
313 0xc9, 0x00, /* voffset hi (input) */ 353 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
314 0xca, 0x20, /* vsize low (input), 0x0120 = 288 */ 354
315 0xcb, 0x01, /* vsize hi (input) */ 355 /* hsize 0x02d0 = 720 */
316 0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */ 356 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
317 0xcd, 0x02, /* hsize hi (output) */ 357 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
318 0xce, 0x20, /* vsize low (output), 0x0120 = 288 */ 358
319 0xcf, 0x01, /* vsize hi (output) */ 359 /* voffset 0x16 = 22 */
320 360 R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
321 0xf0, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */ 361 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
322 0xf1, 0x05, /* low bit with 0xF0, (was 0x05) */ 362
323 0xf5, 0xb0, /* Set pulse generator register */ 363 /* vsize 0x0120 = 288 */
324 0xf6, 0x01, 364 R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
325 365 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
326 0x87, 0x00, /* Disable I-port output */ 366
327 0x88, 0xd0, /* reset scaler (was 0xD0) */ 367 /* hsize 0x02d0 = 720 */
328 0x80, 0x20, /* Activate only task "B" */ 368 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
329 0x88, 0xf0, /* activate scaler */ 369 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
330 0x87, 0x01, /* Enable I-port output */ 370
371 /* vsize 0x0120 = 288 */
372 R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
373 R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
374
375 R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
376 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */
377 R_F5_PULSGEN_LINE_LENGTH, 0xb0,
378 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
379
380 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* Disable I-port output */
381 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler (was 0xD0) */
382 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
383 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
384 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
385
331 0x00, 0x00 386 0x00, 0x00
332}; 387};
333 388
334/* ============== SAA7715 VIDEO templates (end) ======= */ 389/* ============== SAA7715 VIDEO templates (end) ======= */
335 390
336static const unsigned char saa7115_cfg_vbi_on[] = { 391static const unsigned char saa7115_cfg_vbi_on[] = {
337 0x80, 0x00, /* reset tasks */ 392 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
338 0x88, 0xd0, /* reset scaler */ 393 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
339 0x80, 0x30, /* Activate both tasks */ 394 R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */
340 0x88, 0xf0, /* activate scaler */ 395 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
341 0x87, 0x01, /* Enable I-port output */ 396 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
397
342 0x00, 0x00 398 0x00, 0x00
343}; 399};
344 400
345static const unsigned char saa7115_cfg_vbi_off[] = { 401static const unsigned char saa7115_cfg_vbi_off[] = {
346 0x80, 0x00, /* reset tasks */ 402 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
347 0x88, 0xd0, /* reset scaler */ 403 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
348 0x80, 0x20, /* Activate only task "B" */ 404 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
349 0x88, 0xf0, /* activate scaler */ 405 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
350 0x87, 0x01, /* Enable I-port output */ 406 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
407
351 0x00, 0x00 408 0x00, 0x00
352}; 409};
353 410
354static const unsigned char saa7113_init_auto_input[] = { 411static const unsigned char saa7113_init_auto_input[] = {
355 0x01, 0x08, /* PH7113_INCREMENT_DELAY - (1) (1) (1) (1) IDEL3 IDEL2 IDELL1 IDEL0 */ 412 R_01_INC_DELAY, 0x08,
356 0x02, 0xc2, /* PH7113_ANALOG_INPUT_CONTR_1 - FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0 */ 413 R_02_INPUT_CNTL_1, 0xc2,
357 0x03, 0x30, /* PH7113_ANALOG_INPUT_CONTR_2 - (1) HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18 */ 414 R_03_INPUT_CNTL_2, 0x30,
358 0x04, 0x00, /* PH7113_ANALOG_INPUT_CONTR_3 - GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 */ 415 R_04_INPUT_CNTL_3, 0x00,
359 0x05, 0x00, /* PH7113_ANALOG_INPUT_CONTR_4 - GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 */ 416 R_05_INPUT_CNTL_4, 0x00,
360 0x06, 0x89, /* PH7113_HORIZONTAL_SYNC_START - HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 */ 417 R_06_H_SYNC_START, 0x89,
361 0x07, 0x0d, /* PH7113_HORIZONTAL_SYNC_STOP - HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 */ 418 R_07_H_SYNC_STOP, 0x0d,
362 0x08, 0x88, /* PH7113_SYNC_CONTROL - AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 */ 419 R_08_SYNC_CNTL, 0x88,
363 0x09, 0x01, /* PH7113_LUMINANCE_CONTROL - BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0 */ 420 R_09_LUMA_CNTL, 0x01,
364 0x0a, 0x80, /* PH7113_LUMINANCE_BRIGHTNESS - BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 */ 421 R_0A_LUMA_BRIGHT_CNTL, 0x80,
365 0x0b, 0x47, /* PH7113_LUMINANCE_CONTRAST - CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 */ 422 R_0B_LUMA_CONTRAST_CNTL, 0x47,
366 0x0c, 0x40, /* PH7113_CHROMA_SATURATION - SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 */ 423 R_0C_CHROMA_SAT_CNTL, 0x40,
367 0x0d, 0x00, /* PH7113_CHROMA_HUE_CONTROL - HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 */ 424 R_0D_CHROMA_HUE_CNTL, 0x00,
368 0x0e, 0x01, /* PH7113_CHROMA_CONTROL - CDTO CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0 */ 425 R_0E_CHROMA_CNTL_1, 0x01,
369 0x0f, 0x2a, /* PH7113_CHROMA_GAIN_CONTROL - ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 */ 426 R_0F_CHROMA_GAIN_CNTL, 0x2a,
370 0x10, 0x08, /* PH7113_FORMAT_DELAY_CONTROL - OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0 */ 427 R_10_CHROMA_CNTL_2, 0x08,
371 0x11, 0x0c, /* PH7113_OUTPUT_CONTROL_1 - GPSW1 CM99 GPSW0 HLSEL OEYC OERT VIPB COLO */ 428 R_11_MODE_DELAY_CNTL, 0x0c,
372 0x12, 0x07, /* PH7113_OUTPUT_CONTROL_2 - RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 */ 429 R_12_RT_SIGNAL_CNTL, 0x07,
373 0x13, 0x00, /* PH7113_OUTPUT_CONTROL_3 - ADLSB (1) (1) OLDSB FIDP (1) AOSL1 AOSL0 */ 430 R_13_RT_X_PORT_OUT_CNTL, 0x00,
374 0x14, 0x00, /* RESERVED 14 - (1) (1) (1) (1) (1) (1) (1) (1) */ 431 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
375 0x15, 0x00, /* PH7113_V_GATE1_START - VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 */ 432 R_15_VGATE_START_FID_CHG, 0x00,
376 0x16, 0x00, /* PH7113_V_GATE1_STOP - VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 */ 433 R_16_VGATE_STOP, 0x00,
377 0x17, 0x00, /* PH7113_V_GATE1_MSB - (1) (1) (1) (1) (1) (1) VSTO8 VSTA8 */ 434 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
435
378 0x00, 0x00 436 0x00, 0x00
379}; 437};
380 438
381static const unsigned char saa7115_init_misc[] = { 439static const unsigned char saa7115_init_misc[] = {
382 0x81, 0x01, /* reg 0x15,0x16 define blanking window */ 440 R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
383 0x82, 0x00, 441 0x82, 0x00, /* Reserved register - value should be zero*/
384 0x83, 0x01, /* I port settings */ 442 R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
385 0x84, 0x20, 443 R_84_I_PORT_SIGNAL_DEF, 0x20,
386 0x85, 0x21, 444 R_85_I_PORT_SIGNAL_POLAR, 0x21,
387 0x86, 0xc5, 445 R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
388 0x87, 0x01, 446 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
389 447
390 /* Task A */ 448 /* Task A */
391 0xa0, 0x01, /* down scale = 1 */ 449 R_A0_A_HORIZ_PRESCALING, 0x01,
392 0xa1, 0x00, /* prescale accumulation length = 1 */ 450 R_A1_A_ACCUMULATION_LENGTH, 0x00,
393 0xa2, 0x00, /* dc gain and fir prefilter control */ 451 R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
394 0xa4, 0x80, /* Lum Brightness, nominal value = 0x80 */ 452
395 0xa5, 0x40, /* Lum contrast, nominal value = 0x40 */ 453 /* Configure controls at nominal value*/
396 0xa6, 0x40, /* Chroma satur. nominal value = 0x80 */ 454 R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
397 0xa8, 0x00, /* hor lum scaling 0x0200 = 2 zoom */ 455 R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
398 0xa9, 0x02, /* note: 2 x zoom ensures that VBI lines have same length as video lines. */ 456 R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
399 0xaa, 0x00, /* H-phase offset Luma = 0 */ 457
400 0xac, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ 458 /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
401 0xad, 0x01, /* H-scaling incr chroma */ 459 R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
402 0xae, 0x00, /* H-phase offset chroma. must be offset luma / 2 */ 460 R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
403 461
404 0xb0, 0x00, /* V-scaling incr luma low */ 462 R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
405 0xb1, 0x04, /* " hi */ 463
406 0xb2, 0x00, /* V-scaling incr chroma low */ 464 /* must be horiz lum scaling / 2 */
407 0xb3, 0x04, /* " hi */ 465 R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
408 0xb4, 0x01, /* V-scaling mode control */ 466 R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
409 0xb8, 0x00, /* V-phase offset chroma 00 */ 467
410 0xb9, 0x00, /* V-phase offset chroma 01 */ 468 /* must be offset luma / 2 */
411 0xba, 0x00, /* V-phase offset chroma 10 */ 469 R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
412 0xbb, 0x00, /* V-phase offset chroma 11 */ 470
413 0xbc, 0x00, /* V-phase offset luma 00 */ 471 R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
414 0xbd, 0x00, /* V-phase offset luma 01 */ 472 R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
415 0xbe, 0x00, /* V-phase offset luma 10 */ 473
416 0xbf, 0x00, /* V-phase offset luma 11 */ 474 R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
475 R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
476
477 R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
478
479 R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
480 R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
481 R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
482 R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
483
484 R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
485 R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
486 R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
487 R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
417 488
418 /* Task B */ 489 /* Task B */
419 0xd0, 0x01, /* down scale = 1 */ 490 R_D0_B_HORIZ_PRESCALING, 0x01,
420 0xd1, 0x00, /* prescale accumulation length = 1 */ 491 R_D1_B_ACCUMULATION_LENGTH, 0x00,
421 0xd2, 0x00, /* dc gain and fir prefilter control */ 492 R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
422 0xd4, 0x80, /* Lum Brightness, nominal value = 0x80 */ 493
423 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ 494 /* Configure controls at nominal value*/
424 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ 495 R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
425 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ 496 R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
426 0xd9, 0x04, 497 R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
427 0xda, 0x00, /* H-phase offset Luma = 0 */ 498
428 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ 499 /* hor lum scaling 0x0400 = 1 */
429 0xdd, 0x02, /* H-scaling incr chroma */ 500 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
430 0xde, 0x00, /* H-phase offset chroma. must be offset luma / 2 */ 501 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
431 502
432 0xe0, 0x00, /* V-scaling incr luma low */ 503 R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
433 0xe1, 0x04, /* " hi */ 504
434 0xe2, 0x00, /* V-scaling incr chroma low */ 505 /* must be hor lum scaling / 2 */
435 0xe3, 0x04, /* " hi */ 506 R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
436 0xe4, 0x01, /* V-scaling mode control */ 507 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
437 0xe8, 0x00, /* V-phase offset chroma 00 */ 508
438 0xe9, 0x00, /* V-phase offset chroma 01 */ 509 /* must be offset luma / 2 */
439 0xea, 0x00, /* V-phase offset chroma 10 */ 510 R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
440 0xeb, 0x00, /* V-phase offset chroma 11 */ 511
441 0xec, 0x00, /* V-phase offset luma 00 */ 512 R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
442 0xed, 0x00, /* V-phase offset luma 01 */ 513 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
443 0xee, 0x00, /* V-phase offset luma 10 */ 514
444 0xef, 0x00, /* V-phase offset luma 11 */ 515 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
445 516 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
446 0xf2, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */ 517
447 0xf3, 0x46, 518 R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
448 0xf4, 0x00, 519
449 0xf7, 0x4b, /* not the recommended settings! */ 520 R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
450 0xf8, 0x00, 521 R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
451 0xf9, 0x4b, 522 R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
452 0xfa, 0x00, 523 R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
453 0xfb, 0x4b, 524
454 0xff, 0x88, /* PLL2 lock detection settings: 71 lines 50% phase error */ 525 R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
526 R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
527 R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
528 R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
529
530 R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
531 R_F3_PLL_INCREMENT, 0x46,
532 R_F4_PLL2_STATUS, 0x00,
533 R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */
534 R_F8_PULSE_B_POS, 0x00,
535 R_F9_PULSE_B_POS_MSB, 0x4b,
536 R_FA_PULSE_C_POS, 0x00,
537 R_FB_PULSE_C_POS_MSB, 0x4b,
538
539 /* PLL2 lock detection settings: 71 lines 50% phase error */
540 R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
455 541
456 /* Turn off VBI */ 542 /* Turn off VBI */
457 0x40, 0x20, /* No framing code errors allowed. */ 543 R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */
458 0x41, 0xff, 544 R_41_LCR_BASE, 0xff,
459 0x42, 0xff, 545 R_41_LCR_BASE+1, 0xff,
460 0x43, 0xff, 546 R_41_LCR_BASE+2, 0xff,
461 0x44, 0xff, 547 R_41_LCR_BASE+3, 0xff,
462 0x45, 0xff, 548 R_41_LCR_BASE+4, 0xff,
463 0x46, 0xff, 549 R_41_LCR_BASE+5, 0xff,
464 0x47, 0xff, 550 R_41_LCR_BASE+6, 0xff,
465 0x48, 0xff, 551 R_41_LCR_BASE+7, 0xff,
466 0x49, 0xff, 552 R_41_LCR_BASE+8, 0xff,
467 0x4a, 0xff, 553 R_41_LCR_BASE+9, 0xff,
468 0x4b, 0xff, 554 R_41_LCR_BASE+10, 0xff,
469 0x4c, 0xff, 555 R_41_LCR_BASE+11, 0xff,
470 0x4d, 0xff, 556 R_41_LCR_BASE+12, 0xff,
471 0x4e, 0xff, 557 R_41_LCR_BASE+13, 0xff,
472 0x4f, 0xff, 558 R_41_LCR_BASE+14, 0xff,
473 0x50, 0xff, 559 R_41_LCR_BASE+15, 0xff,
474 0x51, 0xff, 560 R_41_LCR_BASE+16, 0xff,
475 0x52, 0xff, 561 R_41_LCR_BASE+17, 0xff,
476 0x53, 0xff, 562 R_41_LCR_BASE+18, 0xff,
477 0x54, 0xff, 563 R_41_LCR_BASE+19, 0xff,
478 0x55, 0xff, 564 R_41_LCR_BASE+20, 0xff,
479 0x56, 0xff, 565 R_41_LCR_BASE+21, 0xff,
480 0x57, 0xff, 566 R_41_LCR_BASE+22, 0xff,
481 0x58, 0x40, 567 R_58_PROGRAM_FRAMING_CODE, 0x40,
482 0x59, 0x47, 568 R_59_H_OFF_FOR_SLICER, 0x47,
483 0x5b, 0x83, 569 R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
484 0x5d, 0xbd, 570 R_5D_DID, 0xbd,
485 0x5e, 0x35, 571 R_5E_SDID, 0x35,
486 572
487 0x02, 0x84, /* input tuner -> input 4, amplifier active */ 573 R_02_INPUT_CNTL_1, 0x84, /* input tuner -> input 4, amplifier active */
488 0x09, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */ 574 R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
489 575
490 0x80, 0x20, /* enable task B */ 576 R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */
491 0x88, 0xd0, 577 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
492 0x88, 0xf0, 578 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
493 0x00, 0x00 579 0x00, 0x00
494}; 580};
495 581
@@ -617,15 +703,19 @@ static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq)
617 if (state->apll) 703 if (state->apll)
618 acc |= 0x08; 704 acc |= 0x08;
619 705
620 saa7115_write(client, 0x38, 0x03); 706 saa7115_write(client, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
621 saa7115_write(client, 0x39, 0x10); 707 saa7115_write(client, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
622 saa7115_write(client, 0x3a, acc); 708 saa7115_write(client, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
623 saa7115_write(client, 0x30, acpf & 0xff); 709
624 saa7115_write(client, 0x31, (acpf >> 8) & 0xff); 710 saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
625 saa7115_write(client, 0x32, (acpf >> 16) & 0x03); 711 saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
626 saa7115_write(client, 0x34, acni & 0xff); 712 (acpf >> 8) & 0xff);
627 saa7115_write(client, 0x35, (acni >> 8) & 0xff); 713 saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
628 saa7115_write(client, 0x36, (acni >> 16) & 0x3f); 714 (acpf >> 16) & 0x03);
715
716 saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
717 saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
718 saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
629 state->audclk_freq = freq; 719 state->audclk_freq = freq;
630 return 0; 720 return 0;
631} 721}
@@ -642,7 +732,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
642 } 732 }
643 733
644 state->bright = ctrl->value; 734 state->bright = ctrl->value;
645 saa7115_write(client, 0x0a, state->bright); 735 saa7115_write(client, R_0A_LUMA_BRIGHT_CNTL, state->bright);
646 break; 736 break;
647 737
648 case V4L2_CID_CONTRAST: 738 case V4L2_CID_CONTRAST:
@@ -652,7 +742,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
652 } 742 }
653 743
654 state->contrast = ctrl->value; 744 state->contrast = ctrl->value;
655 saa7115_write(client, 0x0b, state->contrast); 745 saa7115_write(client, R_0B_LUMA_CONTRAST_CNTL, state->contrast);
656 break; 746 break;
657 747
658 case V4L2_CID_SATURATION: 748 case V4L2_CID_SATURATION:
@@ -662,7 +752,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
662 } 752 }
663 753
664 state->sat = ctrl->value; 754 state->sat = ctrl->value;
665 saa7115_write(client, 0x0c, state->sat); 755 saa7115_write(client, R_0C_CHROMA_SAT_CNTL, state->sat);
666 break; 756 break;
667 757
668 case V4L2_CID_HUE: 758 case V4L2_CID_HUE:
@@ -672,7 +762,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
672 } 762 }
673 763
674 state->hue = ctrl->value; 764 state->hue = ctrl->value;
675 saa7115_write(client, 0x0d, state->hue); 765 saa7115_write(client, R_0D_CHROMA_HUE_CNTL, state->hue);
676 break; 766 break;
677 767
678 default: 768 default:
@@ -709,7 +799,7 @@ static int saa7115_get_v4lctrl(struct i2c_client *client, struct v4l2_control *c
709static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std) 799static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
710{ 800{
711 struct saa7115_state *state = i2c_get_clientdata(client); 801 struct saa7115_state *state = i2c_get_clientdata(client);
712 int taskb = saa7115_read(client, 0x80) & 0x10; 802 int taskb = saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10;
713 803
714 /* Prevent unnecessary standard changes. During a standard 804 /* Prevent unnecessary standard changes. During a standard
715 change the I-Port is temporarily disabled. Any devices 805 change the I-Port is temporarily disabled. Any devices
@@ -740,7 +830,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
740 100 reserved NTSC-Japan (3.58MHz) 830 100 reserved NTSC-Japan (3.58MHz)
741 */ 831 */
742 if (state->ident == V4L2_IDENT_SAA7113) { 832 if (state->ident == V4L2_IDENT_SAA7113) {
743 u8 reg = saa7115_read(client, 0x0e) & 0x8f; 833 u8 reg = saa7115_read(client, R_0E_CHROMA_CNTL_1) & 0x8f;
744 834
745 if (std == V4L2_STD_PAL_M) { 835 if (std == V4L2_STD_PAL_M) {
746 reg |= 0x30; 836 reg |= 0x30;
@@ -751,7 +841,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
751 } else if (std == V4L2_STD_NTSC_M_JP) { 841 } else if (std == V4L2_STD_NTSC_M_JP) {
752 reg |= 0x40; 842 reg |= 0x40;
753 } 843 }
754 saa7115_write(client, 0x0e, reg); 844 saa7115_write(client, R_0E_CHROMA_CNTL_1, reg);
755 } 845 }
756 846
757 847
@@ -783,7 +873,7 @@ static void saa7115_log_status(struct i2c_client *client)
783 v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq); 873 v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq);
784 if (state->ident != V4L2_IDENT_SAA7115) { 874 if (state->ident != V4L2_IDENT_SAA7115) {
785 /* status for the saa7114 */ 875 /* status for the saa7114 */
786 reg1f = saa7115_read(client, 0x1f); 876 reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
787 signalOk = (reg1f & 0xc1) == 0x81; 877 signalOk = (reg1f & 0xc1) == 0x81;
788 v4l_info(client, "Video signal: %s\n", signalOk ? "ok" : "bad"); 878 v4l_info(client, "Video signal: %s\n", signalOk ? "ok" : "bad");
789 v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); 879 v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
@@ -791,8 +881,8 @@ static void saa7115_log_status(struct i2c_client *client)
791 } 881 }
792 882
793 /* status for the saa7115 */ 883 /* status for the saa7115 */
794 reg1e = saa7115_read(client, 0x1e); 884 reg1e = saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC);
795 reg1f = saa7115_read(client, 0x1f); 885 reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
796 886
797 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80; 887 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
798 vcr = !(reg1f & 0x10); 888 vcr = !(reg1f & 0x10);
@@ -888,11 +978,13 @@ static void saa7115_set_lcr(struct i2c_client *client, struct v4l2_sliced_vbi_fo
888 978
889 /* write the lcr registers */ 979 /* write the lcr registers */
890 for (i = 2; i <= 23; i++) { 980 for (i = 2; i <= 23; i++) {
891 saa7115_write(client, i - 2 + 0x41, lcr[i]); 981 saa7115_write(client, i - 2 + R_41_LCR_BASE, lcr[i]);
892 } 982 }
893 983
894 /* enable/disable raw VBI capturing */ 984 /* enable/disable raw VBI capturing */
895 saa7115_writeregs(client, fmt->service_set == 0 ? saa7115_cfg_vbi_on : saa7115_cfg_vbi_off); 985 saa7115_writeregs(client, fmt->service_set == 0 ?
986 saa7115_cfg_vbi_on :
987 saa7115_cfg_vbi_off);
896} 988}
897 989
898static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt) 990static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt)
@@ -911,10 +1003,10 @@ static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
911 return -EINVAL; 1003 return -EINVAL;
912 memset(sliced, 0, sizeof(*sliced)); 1004 memset(sliced, 0, sizeof(*sliced));
913 /* done if using raw VBI */ 1005 /* done if using raw VBI */
914 if (saa7115_read(client, 0x80) & 0x10) 1006 if (saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10)
915 return 0; 1007 return 0;
916 for (i = 2; i <= 23; i++) { 1008 for (i = 2; i <= 23; i++) {
917 u8 v = saa7115_read(client, i - 2 + 0x41); 1009 u8 v = saa7115_read(client, i - 2 + R_41_LCR_BASE);
918 1010
919 sliced->service_lines[0][i] = lcr2vbi[v >> 4]; 1011 sliced->service_lines[0][i] = lcr2vbi[v >> 4];
920 sliced->service_lines[1][i] = lcr2vbi[v & 0xf]; 1012 sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
@@ -952,11 +1044,15 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
952 /* probably have a valid size, let's set it */ 1044 /* probably have a valid size, let's set it */
953 /* Set output width/height */ 1045 /* Set output width/height */
954 /* width */ 1046 /* width */
955 saa7115_write(client, 0xcc, (u8) (pix->width & 0xff)); 1047 saa7115_write(client, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
956 saa7115_write(client, 0xcd, (u8) ((pix->width >> 8) & 0xff)); 1048 (u8) (pix->width & 0xff));
1049 saa7115_write(client, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
1050 (u8) ((pix->width >> 8) & 0xff));
957 /* height */ 1051 /* height */
958 saa7115_write(client, 0xce, (u8) (pix->height & 0xff)); 1052 saa7115_write(client, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
959 saa7115_write(client, 0xcf, (u8) ((pix->height >> 8) & 0xff)); 1053 (u8) (pix->height & 0xff));
1054 saa7115_write(client, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
1055 (u8) ((pix->height >> 8) & 0xff));
960 1056
961 /* Scaling settings */ 1057 /* Scaling settings */
962 /* Hprescaler is floor(inres/outres) */ 1058 /* Hprescaler is floor(inres/outres) */
@@ -970,15 +1066,20 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
970 v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC); 1066 v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
971 /* FIXME hardcodes to "Task B" 1067 /* FIXME hardcodes to "Task B"
972 * write H prescaler integer */ 1068 * write H prescaler integer */
973 saa7115_write(client, 0xd0, (u8) (HPSC & 0x3f)); 1069 saa7115_write(client, R_D0_B_HORIZ_PRESCALING,
1070 (u8) (HPSC & 0x3f));
974 1071
975 /* write H fine-scaling (luminance) */ 1072 /* write H fine-scaling (luminance) */
976 saa7115_write(client, 0xd8, (u8) (HFSC & 0xff)); 1073 saa7115_write(client, R_D8_B_HORIZ_LUMA_SCALING_INC,
977 saa7115_write(client, 0xd9, (u8) ((HFSC >> 8) & 0xff)); 1074 (u8) (HFSC & 0xff));
1075 saa7115_write(client, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
1076 (u8) ((HFSC >> 8) & 0xff));
978 /* write H fine-scaling (chrominance) 1077 /* write H fine-scaling (chrominance)
979 * must be lum/2, so i'll just bitshift :) */ 1078 * must be lum/2, so i'll just bitshift :) */
980 saa7115_write(client, 0xDC, (u8) ((HFSC >> 1) & 0xff)); 1079 saa7115_write(client, R_DC_B_HORIZ_CHROMA_SCALING,
981 saa7115_write(client, 0xDD, (u8) ((HFSC >> 9) & 0xff)); 1080 (u8) ((HFSC >> 1) & 0xff));
1081 saa7115_write(client, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
1082 (u8) ((HFSC >> 9) & 0xff));
982 } else { 1083 } else {
983 if (is_50hz) { 1084 if (is_50hz) {
984 v4l_dbg(1, debug, client, "Setting full 50hz width\n"); 1085 v4l_dbg(1, debug, client, "Setting full 50hz width\n");
@@ -996,15 +1097,21 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
996 v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY); 1097 v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
997 1098
998 /* Correct Contrast and Luminance */ 1099 /* Correct Contrast and Luminance */
999 saa7115_write(client, 0xd5, (u8) (64 * 1024 / VSCY)); 1100 saa7115_write(client, R_D5_B_LUMA_CONTRAST_CNTL,
1000 saa7115_write(client, 0xd6, (u8) (64 * 1024 / VSCY)); 1101 (u8) (64 * 1024 / VSCY));
1102 saa7115_write(client, R_D6_B_CHROMA_SATURATION_CNTL,
1103 (u8) (64 * 1024 / VSCY));
1001 1104
1002 /* write V fine-scaling (luminance) */ 1105 /* write V fine-scaling (luminance) */
1003 saa7115_write(client, 0xe0, (u8) (VSCY & 0xff)); 1106 saa7115_write(client, R_E0_B_VERT_LUMA_SCALING_INC,
1004 saa7115_write(client, 0xe1, (u8) ((VSCY >> 8) & 0xff)); 1107 (u8) (VSCY & 0xff));
1108 saa7115_write(client, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
1109 (u8) ((VSCY >> 8) & 0xff));
1005 /* write V fine-scaling (chrominance) */ 1110 /* write V fine-scaling (chrominance) */
1006 saa7115_write(client, 0xe2, (u8) (VSCY & 0xff)); 1111 saa7115_write(client, R_E2_B_VERT_CHROMA_SCALING_INC,
1007 saa7115_write(client, 0xe3, (u8) ((VSCY >> 8) & 0xff)); 1112 (u8) (VSCY & 0xff));
1113 saa7115_write(client, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
1114 (u8) ((VSCY >> 8) & 0xff));
1008 } else { 1115 } else {
1009 if (is_50hz) { 1116 if (is_50hz) {
1010 v4l_dbg(1, debug, client, "Setting full 50Hz height\n"); 1117 v4l_dbg(1, debug, client, "Setting full 50Hz height\n");
@@ -1023,7 +1130,7 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
1023 The format is described in the saa7115 datasheet in Tables 25 and 26 1130 The format is described in the saa7115 datasheet in Tables 25 and 26
1024 and in Figure 33. 1131 and in Figure 33.
1025 The current implementation uses SAV/EAV codes and not the ancillary data 1132 The current implementation uses SAV/EAV codes and not the ancillary data
1026 headers. The vbi->p pointer points to the SDID byte right after the SAV 1133 headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
1027 code. */ 1134 code. */
1028static void saa7115_decode_vbi_line(struct i2c_client *client, 1135static void saa7115_decode_vbi_line(struct i2c_client *client,
1029 struct v4l2_decode_vbi_line *vbi) 1136 struct v4l2_decode_vbi_line *vbi)
@@ -1113,7 +1220,7 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
1113 1220
1114 if (state->radio) 1221 if (state->radio)
1115 break; 1222 break;
1116 status = saa7115_read(client, 0x1f); 1223 status = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
1117 1224
1118 v4l_dbg(1, debug, client, "status: 0x%02x\n", status); 1225 v4l_dbg(1, debug, client, "status: 0x%02x\n", status);
1119 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0; 1226 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
@@ -1187,13 +1294,13 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
1187 state->input = route->input; 1294 state->input = route->input;
1188 1295
1189 /* select mode */ 1296 /* select mode */
1190 saa7115_write(client, 0x02, 1297 saa7115_write(client, R_02_INPUT_CNTL_1,
1191 (saa7115_read(client, 0x02) & 0xf0) | 1298 (saa7115_read(client, R_02_INPUT_CNTL_1) & 0xf0) |
1192 state->input); 1299 state->input);
1193 1300
1194 /* bypass chrominance trap for S-Video modes */ 1301 /* bypass chrominance trap for S-Video modes */
1195 saa7115_write(client, 0x09, 1302 saa7115_write(client, R_09_LUMA_CNTL,
1196 (saa7115_read(client, 0x09) & 0x7f) | 1303 (saa7115_read(client, R_09_LUMA_CNTL) & 0x7f) |
1197 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0)); 1304 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1198 break; 1305 break;
1199 } 1306 }
@@ -1205,7 +1312,9 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
1205 1312
1206 if (state->enable != (cmd == VIDIOC_STREAMON)) { 1313 if (state->enable != (cmd == VIDIOC_STREAMON)) {
1207 state->enable = (cmd == VIDIOC_STREAMON); 1314 state->enable = (cmd == VIDIOC_STREAMON);
1208 saa7115_write(client, 0x87, state->enable); 1315 saa7115_write(client,
1316 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED,
1317 state->enable);
1209 } 1318 }
1210 break; 1319 break;
1211 1320
@@ -1392,7 +1501,7 @@ static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind)
1392 i2c_attach_client(client); 1501 i2c_attach_client(client);
1393 1502
1394 v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n", 1503 v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n",
1395 saa7115_read(client, 0x1e), saa7115_read(client, 0x1f)); 1504 saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC), saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC));
1396 1505
1397 return 0; 1506 return 0;
1398} 1507}
diff --git a/drivers/media/video/saa711x_regs.h b/drivers/media/video/saa711x_regs.h
new file mode 100644
index 00000000000..4e5f2eb0a2c
--- /dev/null
+++ b/drivers/media/video/saa711x_regs.h
@@ -0,0 +1,549 @@
1/* saa711x - Philips SAA711x video decoder register specifications
2 *
3 * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@infradead.org>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#define R_00_CHIP_VERSION 0x00
17/* Video Decoder */
18 /* Video Decoder - Frontend part */
19#define R_01_INC_DELAY 0x01
20#define R_02_INPUT_CNTL_1 0x02
21#define R_03_INPUT_CNTL_2 0x03
22#define R_04_INPUT_CNTL_3 0x04
23#define R_05_INPUT_CNTL_4 0x05
24 /* Video Decoder - Decoder part */
25#define R_06_H_SYNC_START 0x06
26#define R_07_H_SYNC_STOP 0x07
27#define R_08_SYNC_CNTL 0x08
28#define R_09_LUMA_CNTL 0x09
29#define R_0A_LUMA_BRIGHT_CNTL 0x0a
30#define R_0B_LUMA_CONTRAST_CNTL 0x0b
31#define R_0C_CHROMA_SAT_CNTL 0x0c
32#define R_0D_CHROMA_HUE_CNTL 0x0d
33#define R_0E_CHROMA_CNTL_1 0x0e
34#define R_0F_CHROMA_GAIN_CNTL 0x0f
35#define R_10_CHROMA_CNTL_2 0x10
36#define R_11_MODE_DELAY_CNTL 0x11
37#define R_12_RT_SIGNAL_CNTL 0x12
38#define R_13_RT_X_PORT_OUT_CNTL 0x13
39#define R_14_ANAL_ADC_COMPAT_CNTL 0x14
40#define R_15_VGATE_START_FID_CHG 0x15
41#define R_16_VGATE_STOP 0x16
42#define R_17_MISC_VGATE_CONF_AND_MSB 0x17
43#define R_18_RAW_DATA_GAIN_CNTL 0x18
44#define R_19_RAW_DATA_OFF_CNTL 0x19
45#define R_1A_COLOR_KILL_LVL_CNTL 0x1a
46#define R_1B_MISC_TVVCRDET 0x1b
47#define R_1C_ENHAN_COMB_CTRL1 0x1c
48#define R_1D_ENHAN_COMB_CTRL2 0x1d
49#define R_1E_STATUS_BYTE_1_VD_DEC 0x1e
50#define R_1F_STATUS_BYTE_2_VD_DEC 0x1f
51
52/* Component processing and interrupt masking part */
53#define R_23_INPUT_CNTL_5 0x23
54#define R_24_INPUT_CNTL_6 0x24
55#define R_25_INPUT_CNTL_7 0x25
56#define R_29_COMP_DELAY 0x29
57#define R_2A_COMP_BRIGHT_CNTL 0x2a
58#define R_2B_COMP_CONTRAST_CNTL 0x2b
59#define R_2C_COMP_SAT_CNTL 0x2c
60#define R_2D_INTERRUPT_MASK_1 0x2d
61#define R_2E_INTERRUPT_MASK_2 0x2e
62#define R_2F_INTERRUPT_MASK_3 0x2f
63
64/* Audio clock generator part */
65#define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD 0x30
66#define R_34_AUD_MAST_CLK_NOMINAL_INC 0x34
67#define R_38_CLK_RATIO_AMXCLK_TO_ASCLK 0x38
68#define R_39_CLK_RATIO_ASCLK_TO_ALRCLK 0x39
69#define R_3A_AUD_CLK_GEN_BASIC_SETUP 0x3a
70
71/* General purpose VBI data slicer part */
72#define R_40_SLICER_CNTL_1 0x40
73#define R_41_LCR_BASE 0x41
74#define R_58_PROGRAM_FRAMING_CODE 0x58
75#define R_59_H_OFF_FOR_SLICER 0x59
76#define R_5A_V_OFF_FOR_SLICER 0x5a
77#define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF 0x5b
78#define R_5D_DID 0x5d
79#define R_5E_SDID 0x5e
80#define R_60_SLICER_STATUS_BYTE_0 0x60
81#define R_61_SLICER_STATUS_BYTE_1 0x61
82#define R_62_SLICER_STATUS_BYTE_2 0x62
83
84/* X port, I port and the scaler part */
85 /* Task independent global settings */
86#define R_80_GLOBAL_CNTL_1 0x80
87#define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81
88#define R_83_X_PORT_I_O_ENA_AND_OUT_CLK 0x83
89#define R_84_I_PORT_SIGNAL_DEF 0x84
90#define R_85_I_PORT_SIGNAL_POLAR 0x85
91#define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT 0x86
92#define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED 0x87
93#define R_88_POWER_SAVE_ADC_PORT_CNTL 0x88
94#define R_8F_STATUS_INFO_SCALER 0x8f
95 /* Task A definition */
96 /* Basic settings and acquisition window definition */
97#define R_90_A_TASK_HANDLING_CNTL 0x90
98#define R_91_A_X_PORT_FORMATS_AND_CONF 0x91
99#define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL 0x92
100#define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF 0x93
101#define R_94_A_HORIZ_INPUT_WINDOW_START 0x94
102#define R_95_A_HORIZ_INPUT_WINDOW_START_MSB 0x95
103#define R_96_A_HORIZ_INPUT_WINDOW_LENGTH 0x96
104#define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB 0x97
105#define R_98_A_VERT_INPUT_WINDOW_START 0x98
106#define R_99_A_VERT_INPUT_WINDOW_START_MSB 0x99
107#define R_9A_A_VERT_INPUT_WINDOW_LENGTH 0x9a
108#define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB 0x9b
109#define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH 0x9c
110#define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0x9d
111#define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH 0x9e
112#define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB 0x9f
113 /* FIR filtering and prescaling */
114#define R_A0_A_HORIZ_PRESCALING 0xa0
115#define R_A1_A_ACCUMULATION_LENGTH 0xa1
116#define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xa2
117#define R_A4_A_LUMA_BRIGHTNESS_CNTL 0xa4
118#define R_A5_A_LUMA_CONTRAST_CNTL 0xa5
119#define R_A6_A_CHROMA_SATURATION_CNTL 0xa6
120 /* Horizontal phase scaling */
121#define R_A8_A_HORIZ_LUMA_SCALING_INC 0xa8
122#define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB 0xa9
123#define R_AA_A_HORIZ_LUMA_PHASE_OFF 0xaa
124#define R_AC_A_HORIZ_CHROMA_SCALING_INC 0xac
125#define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB 0xad
126#define R_AE_A_HORIZ_CHROMA_PHASE_OFF 0xae
127#define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB 0xaf
128 /* Vertical scaling */
129#define R_B0_A_VERT_LUMA_SCALING_INC 0xb0
130#define R_B1_A_VERT_LUMA_SCALING_INC_MSB 0xb1
131#define R_B2_A_VERT_CHROMA_SCALING_INC 0xb2
132#define R_B3_A_VERT_CHROMA_SCALING_INC_MSB 0xb3
133#define R_B4_A_VERT_SCALING_MODE_CNTL 0xb4
134#define R_B8_A_VERT_CHROMA_PHASE_OFF_00 0xb8
135#define R_B9_A_VERT_CHROMA_PHASE_OFF_01 0xb9
136#define R_BA_A_VERT_CHROMA_PHASE_OFF_10 0xba
137#define R_BB_A_VERT_CHROMA_PHASE_OFF_11 0xbb
138#define R_BC_A_VERT_LUMA_PHASE_OFF_00 0xbc
139#define R_BD_A_VERT_LUMA_PHASE_OFF_01 0xbd
140#define R_BE_A_VERT_LUMA_PHASE_OFF_10 0xbe
141#define R_BF_A_VERT_LUMA_PHASE_OFF_11 0xbf
142 /* Task B definition */
143 /* Basic settings and acquisition window definition */
144#define R_C0_B_TASK_HANDLING_CNTL 0xc0
145#define R_C1_B_X_PORT_FORMATS_AND_CONF 0xc1
146#define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION 0xc2
147#define R_C3_B_I_PORT_FORMATS_AND_CONF 0xc3
148#define R_C4_B_HORIZ_INPUT_WINDOW_START 0xc4
149#define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB 0xc5
150#define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH 0xc6
151#define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB 0xc7
152#define R_C8_B_VERT_INPUT_WINDOW_START 0xc8
153#define R_C9_B_VERT_INPUT_WINDOW_START_MSB 0xc9
154#define R_CA_B_VERT_INPUT_WINDOW_LENGTH 0xca
155#define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB 0xcb
156#define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH 0xcc
157#define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0xcd
158#define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH 0xce
159#define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB 0xcf
160 /* FIR filtering and prescaling */
161#define R_D0_B_HORIZ_PRESCALING 0xd0
162#define R_D1_B_ACCUMULATION_LENGTH 0xd1
163#define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xd2
164#define R_D4_B_LUMA_BRIGHTNESS_CNTL 0xd4
165#define R_D5_B_LUMA_CONTRAST_CNTL 0xd5
166#define R_D6_B_CHROMA_SATURATION_CNTL 0xd6
167 /* Horizontal phase scaling */
168#define R_D8_B_HORIZ_LUMA_SCALING_INC 0xd8
169#define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB 0xd9
170#define R_DA_B_HORIZ_LUMA_PHASE_OFF 0xda
171#define R_DC_B_HORIZ_CHROMA_SCALING 0xdc
172#define R_DD_B_HORIZ_CHROMA_SCALING_MSB 0xdd
173#define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA 0xde
174 /* Vertical scaling */
175#define R_E0_B_VERT_LUMA_SCALING_INC 0xe0
176#define R_E1_B_VERT_LUMA_SCALING_INC_MSB 0xe1
177#define R_E2_B_VERT_CHROMA_SCALING_INC 0xe2
178#define R_E3_B_VERT_CHROMA_SCALING_INC_MSB 0xe3
179#define R_E4_B_VERT_SCALING_MODE_CNTL 0xe4
180#define R_E8_B_VERT_CHROMA_PHASE_OFF_00 0xe8
181#define R_E9_B_VERT_CHROMA_PHASE_OFF_01 0xe9
182#define R_EA_B_VERT_CHROMA_PHASE_OFF_10 0xea
183#define R_EB_B_VERT_CHROMA_PHASE_OFF_11 0xeb
184#define R_EC_B_VERT_LUMA_PHASE_OFF_00 0xec
185#define R_ED_B_VERT_LUMA_PHASE_OFF_01 0xed
186#define R_EE_B_VERT_LUMA_PHASE_OFF_10 0xee
187#define R_EF_B_VERT_LUMA_PHASE_OFF_11 0xef
188
189/* second PLL (PLL2) and Pulsegenerator Programming */
190#define R_F0_LFCO_PER_LINE 0xf0
191#define R_F1_P_I_PARAM_SELECT 0xf1
192#define R_F2_NOMINAL_PLL2_DTO 0xf2
193#define R_F3_PLL_INCREMENT 0xf3
194#define R_F4_PLL2_STATUS 0xf4
195#define R_F5_PULSGEN_LINE_LENGTH 0xf5
196#define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG 0xf6
197#define R_F7_PULSE_A_POS_MSB 0xf7
198#define R_F8_PULSE_B_POS 0xf8
199#define R_F9_PULSE_B_POS_MSB 0xf9
200#define R_FA_PULSE_C_POS 0xfa
201#define R_FB_PULSE_C_POS_MSB 0xfb
202#define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES 0xff
203
204#if 0
205/* Those structs will be used in the future for debug purposes */
206struct saa711x_reg_descr {
207 u8 reg;
208 int count;
209 char *name;
210};
211
212struct saa711x_reg_descr saa711x_regs[] = {
213 /* REG COUNT NAME */
214 {R_00_CHIP_VERSION,1,
215 "Chip version"},
216
217 /* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */
218
219 /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
220 {R_01_INC_DELAY,1,
221 "Increment delay"},
222 {R_02_INPUT_CNTL_1,1,
223 "Analog input control 1"},
224 {R_03_INPUT_CNTL_2,1,
225 "Analog input control 2"},
226 {R_04_INPUT_CNTL_3,1,
227 "Analog input control 3"},
228 {R_05_INPUT_CNTL_4,1,
229 "Analog input control 4"},
230
231 /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
232 {R_06_H_SYNC_START,1,
233 "Horizontal sync start"},
234 {R_07_H_SYNC_STOP,1,
235 "Horizontal sync stop"},
236 {R_08_SYNC_CNTL,1,
237 "Sync control"},
238 {R_09_LUMA_CNTL,1,
239 "Luminance control"},
240 {R_0A_LUMA_BRIGHT_CNTL,1,
241 "Luminance brightness control"},
242 {R_0B_LUMA_CONTRAST_CNTL,1,
243 "Luminance contrast control"},
244 {R_0C_CHROMA_SAT_CNTL,1,
245 "Chrominance saturation control"},
246 {R_0D_CHROMA_HUE_CNTL,1,
247 "Chrominance hue control"},
248 {R_0E_CHROMA_CNTL_1,1,
249 "Chrominance control 1"},
250 {R_0F_CHROMA_GAIN_CNTL,1,
251 "Chrominance gain control"},
252 {R_10_CHROMA_CNTL_2,1,
253 "Chrominance control 2"},
254 {R_11_MODE_DELAY_CNTL,1,
255 "Mode/delay control"},
256 {R_12_RT_SIGNAL_CNTL,1,
257 "RT signal control"},
258 {R_13_RT_X_PORT_OUT_CNTL,1,
259 "RT/X port output control"},
260 {R_14_ANAL_ADC_COMPAT_CNTL,1,
261 "Analog/ADC/compatibility control"},
262 {R_15_VGATE_START_FID_CHG, 1,
263 "VGATE start FID change"},
264 {R_16_VGATE_STOP,1,
265 "VGATE stop"},
266 {R_17_MISC_VGATE_CONF_AND_MSB, 1,
267 "Miscellaneous VGATE configuration and MSBs"},
268 {R_18_RAW_DATA_GAIN_CNTL,1,
269 "Raw data gain control",},
270 {R_19_RAW_DATA_OFF_CNTL,1,
271 "Raw data offset control",},
272 {R_1A_COLOR_KILL_LVL_CNTL,1,
273 "Color Killer Level Control"},
274 { R_1B_MISC_TVVCRDET, 1,
275 "MISC /TVVCRDET"},
276 { R_1C_ENHAN_COMB_CTRL1, 1,
277 "Enhanced comb ctrl1"},
278 { R_1D_ENHAN_COMB_CTRL2, 1,
279 "Enhanced comb ctrl1"},
280 {R_1E_STATUS_BYTE_1_VD_DEC,1,
281 "Status byte 1 video decoder"},
282 {R_1F_STATUS_BYTE_2_VD_DEC,1,
283 "Status byte 2 video decoder"},
284
285 /* Component processing and interrupt masking part: 0x20h to R_2F_INTERRUPT_MASK_3 */
286 /* 0x20 to 0x22 - Reserved */
287 {R_23_INPUT_CNTL_5,1,
288 "Analog input control 5"},
289 {R_24_INPUT_CNTL_6,1,
290 "Analog input control 6"},
291 {R_25_INPUT_CNTL_7,1,
292 "Analog input control 7"},
293 /* 0x26 to 0x28 - Reserved */
294 {R_29_COMP_DELAY,1,
295 "Component delay"},
296 {R_2A_COMP_BRIGHT_CNTL,1,
297 "Component brightness control"},
298 {R_2B_COMP_CONTRAST_CNTL,1,
299 "Component contrast control"},
300 {R_2C_COMP_SAT_CNTL,1,
301 "Component saturation control"},
302 {R_2D_INTERRUPT_MASK_1,1,
303 "Interrupt mask 1"},
304 {R_2E_INTERRUPT_MASK_2,1,
305 "Interrupt mask 2"},
306 {R_2F_INTERRUPT_MASK_3,1,
307 "Interrupt mask 3"},
308
309 /* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */
310 {R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3,
311 "Audio master clock cycles per field"},
312 /* 0x33 - Reserved */
313 {R_34_AUD_MAST_CLK_NOMINAL_INC,3,
314 "Audio master clock nominal increment"},
315 /* 0x37 - Reserved */
316 {R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
317 "Clock ratio AMXCLK to ASCLK"},
318 {R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
319 "Clock ratio ASCLK to ALRCLK"},
320 {R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
321 "Audio clock generator basic setup"},
322 /* 0x3b-0x3f - Reserved */
323
324 /* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */
325 {R_40_SLICER_CNTL_1,1,
326 "Slicer control 1"},
327 {R_41_LCR,23,
328 "R_41_LCR"},
329 {R_58_PROGRAM_FRAMING_CODE,1,
330 "Programmable framing code"},
331 {R_59_H_OFF_FOR_SLICER,1,
332 "Horizontal offset for slicer"},
333 {R_5A_V_OFF_FOR_SLICER,1,
334 "Vertical offset for slicer"},
335 {R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
336 "Field offset and MSBs for horizontal and vertical offset"},
337 {R_5D_DID,1,
338 "Header and data identification (R_5D_DID)"},
339 {R_5E_SDID,1,
340 "Sliced data identification (R_5E_SDID) code"},
341 {R_60_SLICER_STATUS_BYTE_0,1,
342 "Slicer status byte 0"},
343 {R_61_SLICER_STATUS_BYTE_1,1,
344 "Slicer status byte 1"},
345 {R_62_SLICER_STATUS_BYTE_2,1,
346 "Slicer status byte 2"},
347 /* 0x63-0x7f - Reserved */
348
349 /* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
350 /* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */
351 {R_80_GLOBAL_CNTL_1,1,
352 "Global control 1"},
353 {R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
354 "Vertical sync and Field ID source selection, retimed V and F signals"},
355 /* 0x82 - Reserved */
356 {R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
357 "X port I/O enable and output clock"},
358 {R_84_I_PORT_SIGNAL_DEF,1,
359 "I port signal definitions"},
360 {R_85_I_PORT_SIGNAL_POLAR,1,
361 "I port signal polarities"},
362 {R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
363 "I port FIFO flag control and arbitration"},
364 {R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 1,
365 "I port I/O enable output clock and gated"},
366 {R_88_POWER_SAVE_ADC_PORT_CNTL,1,
367 "Power save/ADC port control"},
368 /* 089-0x8e - Reserved */
369 {R_8F_STATUS_INFO_SCALER,1,
370 "Status information scaler part"},
371
372 /* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
373 /* Task A: Basic settings and acquisition window definition */
374 {R_90_A_TASK_HANDLING_CNTL,1,
375 "Task A: Task handling control"},
376 {R_91_A_X_PORT_FORMATS_AND_CONF,1,
377 "Task A: X port formats and configuration"},
378 {R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
379 "Task A: X port input reference signal definition"},
380 {R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
381 "Task A: I port output formats and configuration"},
382 {R_94_A_HORIZ_INPUT_WINDOW_START,2,
383 "Task A: Horizontal input window start"},
384 {R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2,
385 "Task A: Horizontal input window length"},
386 {R_98_A_VERT_INPUT_WINDOW_START,2,
387 "Task A: Vertical input window start"},
388 {R_9A_A_VERT_INPUT_WINDOW_LENGTH,2,
389 "Task A: Vertical input window length"},
390 {R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
391 "Task A: Horizontal output window length"},
392 {R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2,
393 "Task A: Vertical output window length"},
394
395 /* Task A: FIR filtering and prescaling */
396 {R_A0_A_HORIZ_PRESCALING,1,
397 "Task A: Horizontal prescaling"},
398 {R_A1_A_ACCUMULATION_LENGTH,1,
399 "Task A: Accumulation length"},
400 {R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
401 "Task A: Prescaler DC gain and FIR prefilter"},
402 /* 0xa3 - Reserved */
403 {R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
404 "Task A: Luminance brightness control"},
405 {R_A5_A_LUMA_CONTRAST_CNTL,1,
406 "Task A: Luminance contrast control"},
407 {R_A6_A_CHROMA_SATURATION_CNTL,1,
408 "Task A: Chrominance saturation control"},
409 /* 0xa7 - Reserved */
410
411 /* Task A: Horizontal phase scaling */
412 {R_A8_A_HORIZ_LUMA_SCALING_INC,2,
413 "Task A: Horizontal luminance scaling increment"},
414 {R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
415 "Task A: Horizontal luminance phase offset"},
416 /* 0xab - Reserved */
417 {R_AC_A_HORIZ_CHROMA_SCALING_INC,2,
418 "Task A: Horizontal chrominance scaling increment"},
419 {R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
420 "Task A: Horizontal chrominance phase offset"},
421 /* 0xaf - Reserved */
422
423 /* Task A: Vertical scaling */
424 {R_B0_A_VERT_LUMA_SCALING_INC,2,
425 "Task A: Vertical luminance scaling increment"},
426 {R_B2_A_VERT_CHROMA_SCALING_INC,2,
427 "Task A: Vertical chrominance scaling increment"},
428 {R_B4_A_VERT_SCALING_MODE_CNTL,1,
429 "Task A: Vertical scaling mode control"},
430 /* 0xb5-0xb7 - Reserved */
431 {R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
432 "Task A: Vertical chrominance phase offset '00'"},
433 {R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
434 "Task A: Vertical chrominance phase offset '01'"},
435 {R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
436 "Task A: Vertical chrominance phase offset '10'"},
437 {R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
438 "Task A: Vertical chrominance phase offset '11'"},
439 {R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
440 "Task A: Vertical luminance phase offset '00'"},
441 {R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
442 "Task A: Vertical luminance phase offset '01'"},
443 {R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
444 "Task A: Vertical luminance phase offset '10'"},
445 {R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
446 "Task A: Vertical luminance phase offset '11'"},
447
448 /* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
449 /* Task B: Basic settings and acquisition window definition */
450 {R_C0_B_TASK_HANDLING_CNTL,1,
451 "Task B: Task handling control"},
452 {R_C1_B_X_PORT_FORMATS_AND_CONF,1,
453 "Task B: X port formats and configuration"},
454 {R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
455 "Task B: Input reference signal definition"},
456 {R_C3_B_I_PORT_FORMATS_AND_CONF,1,
457 "Task B: I port formats and configuration"},
458 {R_C4_B_HORIZ_INPUT_WINDOW_START,2,
459 "Task B: Horizontal input window start"},
460 {R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2,
461 "Task B: Horizontal input window length"},
462 {R_C8_B_VERT_INPUT_WINDOW_START,2,
463 "Task B: Vertical input window start"},
464 {R_CA_B_VERT_INPUT_WINDOW_LENGTH,2,
465 "Task B: Vertical input window length"},
466 {R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
467 "Task B: Horizontal output window length"},
468 {R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2,
469 "Task B: Vertical output window length"},
470
471 /* Task B: FIR filtering and prescaling */
472 {R_D0_B_HORIZ_PRESCALING,1,
473 "Task B: Horizontal prescaling"},
474 {R_D1_B_ACCUMULATION_LENGTH,1,
475 "Task B: Accumulation length"},
476 {R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
477 "Task B: Prescaler DC gain and FIR prefilter"},
478 /* 0xd3 - Reserved */
479 {R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
480 "Task B: Luminance brightness control"},
481 {R_D5_B_LUMA_CONTRAST_CNTL,1,
482 "Task B: Luminance contrast control"},
483 {R_D6_B_CHROMA_SATURATION_CNTL,1,
484 "Task B: Chrominance saturation control"},
485 /* 0xd7 - Reserved */
486
487 /* Task B: Horizontal phase scaling */
488 {R_D8_B_HORIZ_LUMA_SCALING_INC,2,
489 "Task B: Horizontal luminance scaling increment"},
490 {R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
491 "Task B: Horizontal luminance phase offset"},
492 /* 0xdb - Reserved */
493 {R_DC_B_HORIZ_CHROMA_SCALING,2,
494 "Task B: Horizontal chrominance scaling"},
495 {R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
496 "Task B: Horizontal Phase Offset Chroma"},
497 /* 0xdf - Reserved */
498
499 /* Task B: Vertical scaling */
500 {R_E0_B_VERT_LUMA_SCALING_INC,2,
501 "Task B: Vertical luminance scaling increment"},
502 {R_E2_B_VERT_CHROMA_SCALING_INC,2,
503 "Task B: Vertical chrominance scaling increment"},
504 {R_E4_B_VERT_SCALING_MODE_CNTL,1,
505 "Task B: Vertical scaling mode control"},
506 /* 0xe5-0xe7 - Reserved */
507 {R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
508 "Task B: Vertical chrominance phase offset '00'"},
509 {R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
510 "Task B: Vertical chrominance phase offset '01'"},
511 {R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
512 "Task B: Vertical chrominance phase offset '10'"},
513 {R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
514 "Task B: Vertical chrominance phase offset '11'"},
515 {R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
516 "Task B: Vertical luminance phase offset '00'"},
517 {R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
518 "Task B: Vertical luminance phase offset '01'"},
519 {R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
520 "Task B: Vertical luminance phase offset '10'"},
521 {R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
522 "Task B: Vertical luminance phase offset '11'"},
523
524 /* second PLL (PLL2) and Pulsegenerator Programming */
525 { R_F0_LFCO_PER_LINE, 1,
526 "LFCO's per line"},
527 { R_F1_P_I_PARAM_SELECT,1,
528 "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"},
529 { R_F2_NOMINAL_PLL2_DTO,1,
530 "Nominal PLL2 DTO"},
531 {R_F3_PLL_INCREMENT,1,
532 "PLL2 Increment"},
533 {R_F4_PLL2_STATUS,1,
534 "PLL2 Status"},
535 {R_F5_PULSGEN_LINE_LENGTH,1,
536 "Pulsgen. line length"},
537 {R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
538 "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
539 {R_F7_PULSE_A_POS_MSB,1,
540 "Pulse A Position"},
541 {R_F8_PULSE_B_POS,2,
542 "Pulse B Position"},
543 {R_FA_PULSE_C_POS,2,
544 "Pulse C Position"},
545 /* 0xfc to 0xfe - Reserved */
546 {R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
547 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
548};
549#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 19:41:49 -0500