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authorJonathan Corbet <corbet@lwn.net>2007-08-17 00:02:33 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2007-08-20 11:18:04 -0400
commit6d77444aca298b43a88086be446f943cd0442ef7 (patch)
tree3d0b4c4834fcd1048e4f80c5f60847efbe102fdf /drivers/media/video
parent01659f2a0067d855089811529fa596cbc40f1e75 (diff)
V4L/DVB (6027): Get rid of an ill-behaved msleep in i2c write
Configuring the OLPC camera requires something over 150 register writes. Unfortunately, querying the CAFE i2c controller too soon after a write causes the hardware to flake. The problem had been "solved" with an msleep() call, but, between the number of registers and how msleep() behaves, that resulted in a 3-second delay on camera initialization. Instead, we hand-code a wait for the completion interrupt which avoids reading the status registers. Signed-off-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/video')
-rw-r--r--drivers/media/video/cafe_ccic.c22
-rw-r--r--drivers/media/video/ov7670.c5
2 files changed, 25 insertions, 2 deletions
diff --git a/drivers/media/video/cafe_ccic.c b/drivers/media/video/cafe_ccic.c
index 88090107cd4..acf64b19730 100644
--- a/drivers/media/video/cafe_ccic.c
+++ b/drivers/media/video/cafe_ccic.c
@@ -356,6 +356,7 @@ static int cafe_smbus_write_data(struct cafe_camera *cam,
356{ 356{
357 unsigned int rval; 357 unsigned int rval;
358 unsigned long flags; 358 unsigned long flags;
359 DEFINE_WAIT(the_wait);
359 360
360 spin_lock_irqsave(&cam->dev_lock, flags); 361 spin_lock_irqsave(&cam->dev_lock, flags);
361 rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID); 362 rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
@@ -369,10 +370,29 @@ static int cafe_smbus_write_data(struct cafe_camera *cam,
369 rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR); 370 rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
370 cafe_reg_write(cam, REG_TWSIC1, rval); 371 cafe_reg_write(cam, REG_TWSIC1, rval);
371 spin_unlock_irqrestore(&cam->dev_lock, flags); 372 spin_unlock_irqrestore(&cam->dev_lock, flags);
372 msleep(2); /* Required or things flake */
373 373
374 /*
375 * Time to wait for the write to complete. THIS IS A RACY
376 * WAY TO DO IT, but the sad fact is that reading the TWSIC1
377 * register too quickly after starting the operation sends
378 * the device into a place that may be kinder and better, but
379 * which is absolutely useless for controlling the sensor. In
380 * practice we have plenty of time to get into our sleep state
381 * before the interrupt hits, and the worst case is that we
382 * time out and then see that things completed, so this seems
383 * the best way for now.
384 */
385 do {
386 prepare_to_wait(&cam->smbus_wait, &the_wait,
387 TASK_UNINTERRUPTIBLE);
388 schedule_timeout(1); /* even 1 jiffy is too long */
389 finish_wait(&cam->smbus_wait, &the_wait);
390 } while (!cafe_smbus_write_done(cam));
391
392#ifdef IF_THE_CAFE_HARDWARE_WORKED_RIGHT
374 wait_event_timeout(cam->smbus_wait, cafe_smbus_write_done(cam), 393 wait_event_timeout(cam->smbus_wait, cafe_smbus_write_done(cam),
375 CAFE_SMBUS_TIMEOUT); 394 CAFE_SMBUS_TIMEOUT);
395#endif
376 spin_lock_irqsave(&cam->dev_lock, flags); 396 spin_lock_irqsave(&cam->dev_lock, flags);
377 rval = cafe_reg_read(cam, REG_TWSIC1); 397 rval = cafe_reg_read(cam, REG_TWSIC1);
378 spin_unlock_irqrestore(&cam->dev_lock, flags); 398 spin_unlock_irqrestore(&cam->dev_lock, flags);
diff --git a/drivers/media/video/ov7670.c b/drivers/media/video/ov7670.c
index f8f21ddd984..c4c5bd67f79 100644
--- a/drivers/media/video/ov7670.c
+++ b/drivers/media/video/ov7670.c
@@ -416,7 +416,10 @@ static int ov7670_read(struct i2c_client *c, unsigned char reg,
416static int ov7670_write(struct i2c_client *c, unsigned char reg, 416static int ov7670_write(struct i2c_client *c, unsigned char reg,
417 unsigned char value) 417 unsigned char value)
418{ 418{
419 return i2c_smbus_write_byte_data(c, reg, value); 419 int ret = i2c_smbus_write_byte_data(c, reg, value);
420 if (reg == REG_COM7 && (value & COM7_RESET))
421 msleep(2); /* Wait for reset to run */
422 return ret;
420} 423}
421 424
422 425