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authorDevin Heitmueller <devin.heitmueller@gmail.com>2008-11-25 04:03:31 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-12-29 14:53:41 -0500
commit55927684e7c616b0b0976cc52926997f2da5930d (patch)
tree52e97907f181cc7412a3b72c63cb685dc6b502ea /drivers/media/video/em28xx/em28xx-reg.h
parent2f56c34b2bc25a5a3419715f38f7d761fcd61b23 (diff)
V4L/DVB (9744): em28xx: cleanup XCLK register usage
Convert over to setting the XCLK register usage with the new em28xx_write_reg() function. Thanks to Ray Lu from Empia for providing the em2860/2880 datasheet. Signed-off-by: Devin Heitmueller <devin.heitmueller@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/em28xx/em28xx-reg.h')
-rw-r--r--drivers/media/video/em28xx/em28xx-reg.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/media/video/em28xx/em28xx-reg.h b/drivers/media/video/em28xx/em28xx-reg.h
index 98e95054e81..45d588c3a6c 100644
--- a/drivers/media/video/em28xx/em28xx-reg.h
+++ b/drivers/media/video/em28xx/em28xx-reg.h
@@ -51,6 +51,24 @@
51#define EM28XX_R0E_AUDIOSRC 0x0e 51#define EM28XX_R0E_AUDIOSRC 0x0e
52#define EM28XX_R0F_XCLK 0x0f 52#define EM28XX_R0F_XCLK 0x0f
53 53
54/* em28xx XCLK Register (0x0f) */
55#define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */
56#define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */
57#define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */
58#define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10
59#define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */
60#define EM28XX_XCLK_FREQUENCY_15MHZ 0x01
61#define EM28XX_XCLK_FREQUENCY_10MHZ 0x02
62#define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03
63#define EM28XX_XCLK_FREQUENCY_6MHZ 0x04
64#define EM28XX_XCLK_FREQUENCY_5MHZ 0x05
65#define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06
66#define EM28XX_XCLK_FREQUENCY_12MHZ 0x07
67#define EM28XX_XCLK_FREQUENCY_20MHZ 0x08
68#define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09
69#define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a
70#define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b
71
54#define EM28XX_R10_VINMODE 0x10 72#define EM28XX_R10_VINMODE 0x10
55#define EM28XX_R11_VINCTRL 0x11 73#define EM28XX_R11_VINCTRL 0x11
56#define EM28XX_R12_VINENABLE 0x12 /* */ 74#define EM28XX_R12_VINENABLE 0x12 /* */