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authorManu Abraham <abraham.manu@gmail.com>2007-07-03 08:53:42 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-12-29 14:53:13 -0500
commit8bd135bab91f4659d4c62466029aff468e56f235 (patch)
tree9cc0450ed16abc4e1029f6ed3bb62d4abfbeee63 /drivers/media/dvb
parent2b1b945f88537a110f018f6a50b1f01bbb23fb7e (diff)
V4L/DVB (9375): Add STB0899 support
Signed-off-by: Manu Abraham <manu@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r--drivers/media/dvb/frontends/stb0899_algo.c1542
-rw-r--r--drivers/media/dvb/frontends/stb0899_drv.c1963
-rw-r--r--drivers/media/dvb/frontends/stb0899_drv.h94
-rw-r--r--drivers/media/dvb/frontends/stb0899_priv.h272
-rw-r--r--drivers/media/dvb/frontends/stb0899_reg.h2018
5 files changed, 5889 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/stb0899_algo.c b/drivers/media/dvb/frontends/stb0899_algo.c
new file mode 100644
index 00000000000..0ae96497581
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_algo.c
@@ -0,0 +1,1542 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "stb0899_drv.h"
23#include "stb0899_priv.h"
24#include "stb0899_reg.h"
25
26/*
27 * BinaryFloatDiv
28 * float division with integer
29 */
30static long BinaryFloatDiv(long n1, long n2, int precision)
31{
32 int i = 0;
33 long result = 0;
34
35 while (i <= precision) {
36 if (n1 < n2) {
37 result *= 2;
38 n1 *= 2;
39 } else {
40 result = result * 2 + 1;
41 n1 = (n1 - n2) * 2;
42 }
43 i++;
44 }
45
46 return result;
47}
48
49/*
50 * stb0899_calc_srate
51 * Compute symbol rate
52 */
53static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
54{
55 u32 tmp, tmp2, mclk;
56
57 mclk = master_clk / 4096L; /* MasterClock * 10 / 2^20 */
58 tmp = (((u32) sfr[0] << 12) + ((u32) sfr[1] << 4)) / 16;
59
60 tmp *= mclk;
61 tmp /= 16;
62 tmp2 = ((u32) sfr[2] * mclk) / 256;
63 tmp += tmp2;
64
65 return tmp;
66}
67
68/*
69 * stb0899_get_srate
70 * Get the current symbol rate
71 */
72u32 stb0899_get_srate(struct stb0899_state *state)
73{
74 struct stb0899_internal *internal = &state->internal;
75 u8 sfr[4];
76
77 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
78
79 return stb0899_calc_srate(internal->master_clk, sfr);
80}
81
82/*
83 * stb0899_set_srate
84 * Set symbol frequency
85 * MasterClock: master clock frequency (hz)
86 * SymbolRate: symbol rate (bauds)
87 * return symbol frequency
88 */
89static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
90{
91 u32 tmp, tmp_up, srate_up;
92 u8 sfr_up[3], sfr[3];
93
94 srate_up = srate;
95 dprintk(state->verbose, FE_DEBUG, 1, "-->");
96 /*
97 * in order to have the maximum precision, the symbol rate entered into
98 * the chip is computed as the closest value of the "true value".
99 * In this purpose, the symbol rate value is rounded (1 is added on the bit
100 * below the LSB )
101 */
102 srate_up += (srate_up * 3) / 100;
103
104 tmp = BinaryFloatDiv(srate, master_clk, 20);
105 tmp_up = BinaryFloatDiv(srate_up, master_clk, 20);
106
107 sfr_up[0] = (tmp_up >> 12) & 0xff;
108 sfr_up[1] = (tmp_up >> 4) & 0xff;
109 sfr_up[2] = tmp_up & 0x0f;
110
111 sfr[0] = (tmp >> 12) & 0xff;
112 sfr[1] = (tmp >> 4) & 0xff;
113 sfr[2] = tmp & 0x0f;
114
115 stb0899_write_regs(state, STB0899_SFRUPH, sfr_up, 3);
116 stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
117
118 return srate;
119}
120
121/*
122 * stb0899_calc_loop_time
123 * Compute the amount of time needed by the timing loop to lock
124 * SymbolRate: Symbol rate
125 * return: timing loop time constant (ms)
126 */
127static long stb0899_calc_loop_time(long srate)
128{
129 if (srate > 0)
130 return (100000 / (srate / 1000));
131 else
132 return 0;
133}
134
135/*
136 * stb0899_calc_derot_time
137 * Compute the amount of time needed by the derotator to lock
138 * SymbolRate: Symbol rate
139 * return: derotator time constant (ms)
140 */
141static long stb0899_calc_derot_time(long srate)
142{
143 if (srate > 0)
144 return (100000 / (srate / 1000));
145 else
146 return 0;
147}
148
149/*
150 * stb0899_carr_width
151 * Compute the width of the carrier
152 * return: width of carrier (kHz or Mhz)
153 */
154long stb0899_carr_width(struct stb0899_state *state)
155{
156 struct stb0899_internal *internal = &state->internal;
157
158 return (internal->srate + (internal->srate * internal->rolloff) / 100);
159}
160
161/*
162 * stb0899_first_subrange
163 * Compute the first subrange of the search
164 */
165static void stb0899_first_subrange(struct stb0899_state *state)
166{
167 struct stb0899_internal *internal = &state->internal;
168 struct stb0899_params *params = &state->params;
169 struct stb0899_config *config = state->config;
170
171 int range = 0;
172 u32 bandwidth = 0;
173
174 if (config->tuner_get_bandwidth) {
175 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
176 range = bandwidth - stb0899_carr_width(state) / 2;
177 }
178
179 if (range > 0)
180 internal->sub_range = MIN(internal->srch_range, range);
181 else
182 internal->sub_range = 0;
183
184 internal->freq = params->freq;
185 internal->tuner_offst = 0L;
186 internal->sub_dir = 1;
187}
188
189/*
190 * stb0899_check_tmg
191 * check for timing lock
192 * internal.Ttiming: time to wait for loop lock
193 */
194static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
195{
196 struct stb0899_internal *internal = &state->internal;
197 int lock, timing;
198 u8 reg;
199
200 msleep(internal->t_timing);
201
202 reg = stb0899_read_reg(state, STB0899_RTF);
203 STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0xf2);
204 stb0899_write_reg(state, STB0899_RTF, reg);
205 reg = stb0899_read_reg(state, STB0899_TLIR);
206 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
207 timing = stb0899_read_reg(state, STB0899_RTF);
208
209 if (lock >= 42) {
210 if ((lock > 48) && (timing >= 110)) {
211 internal->status = ANALOGCARRIER;
212 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
213 } else {
214 internal->status = TIMINGOK;
215 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
216 }
217 } else {
218 internal->status = NOTIMING;
219 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
220 }
221 return internal->status;
222}
223
224/*
225 * stb0899_search_tmg
226 * perform a fs/2 zig-zag to find timing
227 */
228static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
229{
230 struct stb0899_internal *internal = &state->internal;
231 struct stb0899_params *params = &state->params;
232
233 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
234 int index = 0;
235 u8 cfr[2];
236
237 internal->status = NOTIMING;
238
239 /* timing loop computation & symbol rate optimisation */
240 derot_limit = (internal->sub_range / 2L) / internal->mclk;
241 derot_step = (params->srate / 2L) / internal->mclk;
242
243 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
244 index++;
245 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
246
247 if (ABS(derot_freq) > derot_limit)
248 next_loop--;
249
250 if (next_loop) {
251 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
252 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
253 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
254 }
255 internal->direction = -internal->direction; /* Change zigzag direction */
256 }
257
258 if (internal->status == TIMINGOK) {
259 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
260 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
261 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
262 }
263
264 return internal->status;
265}
266
267/*
268 * stb0899_check_carrier
269 * Check for carrier found
270 */
271static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
272{
273 struct stb0899_internal *internal = &state->internal;
274 u8 reg;
275
276 msleep(internal->t_derot); /* wait for derotator ok */
277
278 reg = stb0899_read_reg(state, STB0899_CFD);
279 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
280 stb0899_write_reg(state, STB0899_RTF, reg);
281
282 reg = stb0899_read_reg(state, STB0899_DSTATUS);
283 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
284 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
285 internal->status = CARRIEROK;
286 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
287 } else {
288 internal->status = NOCARRIER;
289 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
290 }
291
292 return internal->status;
293}
294
295/*
296 * stb0899_search_carrier
297 * Search for a QPSK carrier with the derotator
298 */
299static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
300{
301 struct stb0899_internal *internal = &state->internal;
302
303 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
304 int index = 0;
305 u8 cfr[2];
306 u8 reg;
307
308 internal->status = NOCARRIER;
309 derot_limit = (internal->sub_range / 2L) / internal->mclk;
310 derot_freq = internal->derot_freq;
311
312 reg = stb0899_read_reg(state, STB0899_CFD);
313 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
314 stb0899_write_reg(state, STB0899_RTF, reg);
315
316 do {
317 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
318 if (stb0899_check_carrier(state) == NOCARRIER) {
319 index++;
320 last_derot_freq = derot_freq;
321 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
322
323 if(ABS(derot_freq) > derot_limit)
324 next_loop--;
325
326 if (next_loop) {
327 reg = stb0899_read_reg(state, STB0899_CFD);
328 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
329 stb0899_write_reg(state, STB0899_RTF, reg);
330
331 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
332 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
333 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
334 }
335 }
336
337 internal->direction = -internal->direction; /* Change zigzag direction */
338 } while ((internal->status != CARRIEROK) && next_loop);
339
340 if (internal->status == CARRIEROK) {
341 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
342 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
343 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
344 } else {
345 internal->derot_freq = last_derot_freq;
346 }
347
348 return internal->status;
349}
350
351/*
352 * stb0899_check_data
353 * Check for data found
354 */
355static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
356{
357 struct stb0899_internal *internal = &state->internal;
358 struct stb0899_params *params = &state->params;
359
360 int lock = 0, index = 0, dataTime = 500, loop;
361 u8 reg;
362
363 internal->status = NODATA;
364
365 /* RESET FEC */
366 reg = stb0899_read_reg(state, STB0899_TSTRES);
367 STB0899_SETFIELD_VAL(FRESACS, reg, 1);
368 stb0899_write_reg(state, STB0899_TSTRES, reg);
369 msleep(1);
370 reg = stb0899_read_reg(state, STB0899_TSTRES);
371 STB0899_SETFIELD_VAL(FRESACS, reg, 0);
372 stb0899_write_reg(state, STB0899_TSTRES, reg);
373
374 if (params->srate <= 2000000)
375 dataTime = 2000;
376 else if (params->srate <= 5000000)
377 dataTime = 1500;
378 else if (params->srate <= 15000000)
379 dataTime = 1000;
380 else
381 dataTime = 500;
382
383 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
384 while (1) {
385 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
386 reg = stb0899_read_reg(state, STB0899_VSTATUS);
387 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
388 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
389
390 if (lock || loop || (index > dataTime))
391 break;
392 index++;
393 }
394
395 if (lock) { /* DATA LOCK indicator */
396 internal->status = DATAOK;
397 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
398 }
399
400 return internal->status;
401}
402
403/*
404 * stb0899_search_data
405 * Search for a QPSK carrier with the derotator
406 */
407static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
408{
409 short int derot_freq, derot_step, derot_limit, next_loop = 3;
410 u8 cfr[2];
411 u8 reg;
412 int index = 1;
413
414 struct stb0899_internal *internal = &state->internal;
415 struct stb0899_params *params = &state->params;
416
417 derot_step = (params->srate / 4L) / internal->mclk;
418 derot_limit = (internal->sub_range / 2L) / internal->mclk;
419 derot_freq = internal->derot_freq;
420
421 do {
422 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
423
424 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
425 if (ABS(derot_freq) > derot_limit)
426 next_loop--;
427
428 if (next_loop) {
429 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
430 reg = stb0899_read_reg(state, STB0899_CFD);
431 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
432 stb0899_write_reg(state, STB0899_RTF, reg);
433
434 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
435 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
436 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
437
438 stb0899_check_carrier(state);
439 index++;
440 }
441 }
442 internal->direction = -internal->direction; /* change zig zag direction */
443 } while ((internal->status != DATAOK) && next_loop);
444
445 if (internal->status == DATAOK) {
446 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
447 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
448 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
449 }
450
451 return internal->status;
452}
453
454/*
455 * stb0899_check_range
456 * check if the found frequency is in the correct range
457 */
458static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
459{
460 struct stb0899_internal *internal = &state->internal;
461 struct stb0899_params *params = &state->params;
462
463 int range_offst, tp_freq;
464
465 range_offst = internal->srch_range / 2000;
466 tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
467
468 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
469 internal->status = RANGEOK;
470 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
471 } else {
472 internal->status = OUTOFRANGE;
473 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
474 }
475
476 return internal->status;
477}
478
479/*
480 * NextSubRange
481 * Compute the next subrange of the search
482 */
483static void next_sub_range(struct stb0899_state *state)
484{
485 struct stb0899_internal *internal = &state->internal;
486 struct stb0899_params *params = &state->params;
487
488 long old_sub_range;
489
490 if (internal->sub_dir > 0) {
491 old_sub_range = internal->sub_range;
492 internal->sub_range = MIN((internal->srch_range / 2) -
493 (internal->tuner_offst + internal->sub_range / 2),
494 internal->sub_range);
495
496 if (internal->sub_range < 0)
497 internal->sub_range = 0;
498
499 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
500 }
501
502 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
503 internal->sub_dir = -internal->sub_dir;
504}
505
506/*
507 * stb0899_dvbs_algo
508 * Search for a signal, timing, carrier and data for a
509 * given frequency in a given range
510 */
511enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
512{
513 struct stb0899_params *params = &state->params;
514 struct stb0899_internal *internal = &state->internal;
515 struct stb0899_config *config = state->config;
516
517 u8 bclc, reg;
518 u8 cfr[1];
519 u8 eq_const[10];
520 s32 clnI = 3;
521 u32 bandwidth = 0;
522
523 /* BETA values rated @ 99MHz */
524 s32 betaTab[5][4] = {
525 /* 5 10 20 30MBps */
526 { 37, 34, 32, 31 }, /* QPSK 1/2 */
527 { 37, 35, 33, 31 }, /* QPSK 2/3 */
528 { 37, 35, 33, 31 }, /* QPSK 3/4 */
529 { 37, 36, 33, 32 }, /* QPSK 5/6 */
530 { 37, 36, 33, 32 } /* QPSK 7/8 */
531 };
532
533 internal->direction = 1;
534
535 stb0899_set_srate(state, internal->master_clk, params->srate);
536 /* Carrier loop optimization versus symbol rate for acquisition*/
537 if (params->srate <= 5000000) {
538 stb0899_write_reg(state, STB0899_ACLC, 0x89);
539 bclc = stb0899_read_reg(state, STB0899_BCLC);
540 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
541 stb0899_write_reg(state, STB0899_BCLC, bclc);
542 clnI = 0;
543 } else if (params->srate <= 15000000) {
544 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
545 bclc = stb0899_read_reg(state, STB0899_BCLC);
546 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
547 stb0899_write_reg(state, STB0899_BCLC, bclc);
548 clnI = 1;
549 } else if(params->srate <= 25000000) {
550 stb0899_write_reg(state, STB0899_ACLC, 0x89);
551 bclc = stb0899_read_reg(state, STB0899_BCLC);
552 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
553 stb0899_write_reg(state, STB0899_BCLC, bclc);
554 clnI = 2;
555 } else {
556 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
557 bclc = stb0899_read_reg(state, STB0899_BCLC);
558 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
559 stb0899_write_reg(state, STB0899_BCLC, bclc);
560 clnI = 3;
561 }
562
563 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
564 /* Set the timing loop to acquisition */
565 stb0899_write_reg(state, STB0899_RTC, 0x46);
566 stb0899_write_reg(state, STB0899_CFD, 0xee);
567
568 /* !! WARNING !!
569 * Do not read any status variables while acquisition,
570 * If any needed, read before the acquisition starts
571 * querying status while acquiring causes the
572 * acquisition to go bad and hence no locks.
573 */
574 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
575 internal->derot_percent, params->srate, internal->mclk);
576
577 /* Initial calculations */
578 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
579 internal->t_timing = stb0899_calc_loop_time(params->srate);
580 internal->t_derot = stb0899_calc_derot_time(params->srate);
581 internal->t_data = 500;
582
583 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
584 /* RESET Stream merger */
585 reg = stb0899_read_reg(state, STB0899_TSTRES);
586 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
587 stb0899_write_reg(state, STB0899_TSTRES, reg);
588
589 /*
590 * Set KDIVIDER to an intermediate value between
591 * 1/2 and 7/8 for acquisition
592 */
593 reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
594 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
595 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
596
597 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
598 stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
599
600 stb0899_first_subrange(state);
601 do {
602 /* Initialisations */
603 cfr[0] = cfr[1] = 0;
604 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
605
606 reg = stb0899_read_reg(state, STB0899_RTF);
607 STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0);
608 stb0899_write_reg(state, STB0899_RTF, reg);
609 reg = stb0899_read_reg(state, STB0899_CFD);
610 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
611 stb0899_write_reg(state, STB0899_RTF, reg);
612
613 internal->derot_freq = 0;
614 internal->status = NOAGC1;
615
616 /* Move tuner to frequency */
617 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
618 if (state->config->tuner_set_frequency)
619 state->config->tuner_set_frequency(&state->frontend, internal->freq);
620
621 msleep(100);
622
623 if (state->config->tuner_get_frequency)
624 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
625
626 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_timing); /* AGC1, AGC2 and timing loop */
627 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
628 internal->status = AGC1OK;
629
630 /* There is signal in the band */
631 if (config->tuner_get_bandwidth)
632 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
633 if (params->srate <= bandwidth / 2)
634 stb0899_search_tmg(state); /* For low rates (SCPC) */
635 else
636 stb0899_check_tmg(state); /* For high rates (MCPC) */
637
638 if (internal->status == TIMINGOK) {
639 dprintk(state->verbose, FE_DEBUG, 1,
640 "TIMING OK ! Derot freq=%d, mclk=%d",
641 internal->derot_freq, internal->mclk);
642
643 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
644 dprintk(state->verbose, FE_DEBUG, 1,
645 "CARRIER OK ! Derot freq=%d, mclk=%d",
646 internal->derot_freq, internal->mclk);
647
648 if (stb0899_search_data(state) == DATAOK) { /* Check for data */
649 dprintk(state->verbose, FE_DEBUG, 1,
650 "DATA OK ! Derot freq=%d, mclk=%d",
651 internal->derot_freq, internal->mclk);
652
653 if (stb0899_check_range(state) == RANGEOK) {
654 dprintk(state->verbose, FE_DEBUG, 1,
655 "RANGE OK ! derot freq=%d, mclk=%d",
656 internal->derot_freq, internal->mclk);
657
658 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
659 reg = stb0899_read_reg(state, STB0899_PLPARM);
660 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
661 dprintk(state->verbose, FE_DEBUG, 1,
662 "freq=%d, internal resultant freq=%d",
663 params->freq, internal->freq);
664
665 dprintk(state->verbose, FE_DEBUG, 1,
666 "internal puncture rate=%d",
667 internal->fecrate);
668 }
669 }
670 }
671 }
672 if (internal->status != RANGEOK)
673 next_sub_range(state);
674
675 } while (internal->sub_range && internal->status != RANGEOK);
676
677 /* Set the timing loop to tracking */
678 stb0899_write_reg(state, STB0899_RTC, 0x33);
679 stb0899_write_reg(state, STB0899_CFD, 0xf7);
680 reg = 0;
681 /* if locked and range ok, set Kdiv */
682 if (internal->status == RANGEOK) {
683 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
684 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
685 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
686
687 /*
688 * Carrier loop optimization versus
689 * symbol Rate/Puncture Rate for Tracking
690 */
691 switch (internal->fecrate) {
692 case STB0899_FEC_1_2: /* 13 */
693 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 0x1a);
694 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
695 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
696 stb0899_write_reg(state, STB0899_BCLC, reg);
697 break;
698 case STB0899_FEC_2_3: /* 18 */
699 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 44);
700 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
701 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
702 stb0899_write_reg(state, STB0899_BCLC, reg);
703 break;
704 case STB0899_FEC_3_4: /* 21 */
705 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
706 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
707 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
708 stb0899_write_reg(state, STB0899_BCLC, reg);
709 break;
710 case STB0899_FEC_5_6: /* 24 */
711 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 75);
712 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
713 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
714 stb0899_write_reg(state, STB0899_BCLC, reg);
715 break;
716 case STB0899_FEC_6_7: /* 25 */
717 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 88);
718 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
719 stb0899_write_reg(state, STB0899_ACLC, 0x88);
720 stb0899_write_reg(state, STB0899_BCLC, 0x9a);
721 break;
722 case STB0899_FEC_7_8: /* 26 */
723 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 94);
724 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
725 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
726 stb0899_write_reg(state, STB0899_BCLC, reg);
727 break;
728 default:
729 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
730 break;
731 }
732 /* release stream merger RESET */
733 reg = stb0899_read_reg(state, STB0899_TSTRES);
734 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
735 stb0899_write_reg(state, STB0899_TSTRES, reg);
736
737 /* disable carrier detector */
738 reg = stb0899_read_reg(state, STB0899_CFD);
739 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
740 stb0899_write_reg(state, STB0899_RTF, reg);
741
742 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
743 }
744
745 return internal->status;
746}
747
748/*
749 * stb0899_dvbs2_config_uwp
750 * Configure UWP state machine
751 */
752static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
753{
754 struct stb0899_internal *internal = &state->internal;
755 struct stb0899_config *config = state->config;
756 u32 uwp1, uwp2, uwp3, reg;
757
758 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
759 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
760 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
761
762 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
763 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
764 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
765
766 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
767 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
768 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
769
770 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
771 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
772
773 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
774 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
775 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
776
777 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
778 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
779 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
780}
781
782/*
783 * stb0899_dvbs2_config_csm_auto
784 * Set CSM to AUTO mode
785 */
786static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
787{
788 u32 reg;
789
790 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
791 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
792 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
793}
794
795long Log2Int(int number)
796{
797 int i;
798
799 i = 0;
800 while ((1 << i) <= ABS(number))
801 i++;
802
803 if (number == 0)
804 i = 1;
805
806 return i - 1;
807}
808
809/*
810 * stb0899_dvbs2_calc_srate
811 * compute BTR_NOM_FREQ for the symbol rate
812 */
813static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
814{
815 struct stb0899_internal *internal = &state->internal;
816 struct stb0899_config *config = state->config;
817
818 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
819 u32 master_clk, srate;
820
821 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
822 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
823 dec_rate = Log2Int(dec_ratio);
824 decim = 1 << dec_rate;
825 master_clk = internal->master_clk / 1000;
826 srate = internal->srate / 1000;
827
828 if (decim <= 4) {
829 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
830 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
831 } else {
832 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
833 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
834 }
835 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
836
837 return btr_nom_freq;
838}
839
840/*
841 * stb0899_dvbs2_calc_dev
842 * compute the correction to be applied to symbol rate
843 */
844static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
845{
846 struct stb0899_internal *internal = &state->internal;
847 u32 dec_ratio, correction, master_clk, srate;
848
849 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
850 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
851
852 master_clk = internal->master_clk / 1000; /* for integer Caculation*/
853 srate = internal->srate / 1000; /* for integer Caculation*/
854 correction = (512 * master_clk) / (2 * dec_ratio * srate);
855
856 return correction;
857}
858
859/*
860 * stb0899_dvbs2_set_srate
861 * Set DVBS2 symbol rate
862 */
863static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
864{
865 struct stb0899_internal *internal = &state->internal;
866
867 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
868 u32 correction, freq_adj, band_lim, decim_cntrl, reg;
869 u8 anti_alias;
870
871 /*set decimation to 1*/
872 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
873 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
874 dec_rate = Log2Int(dec_ratio);
875
876 win_sel = 0;
877 if (dec_rate >= 5)
878 win_sel = dec_rate - 4;
879
880 decim = (1 << dec_rate);
881 /* (FSamp/Fsymbol *100) for integer Caculation */
882 f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
883
884 if (f_sym <= 2250) /* don't band limit signal going into btr block*/
885 band_lim = 1;
886 else
887 band_lim = 0; /* band limit signal going into btr block*/
888
889 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
890 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
891
892 if (f_sym <= 3450)
893 anti_alias = 0;
894 else if (f_sym <= 4250)
895 anti_alias = 1;
896 else
897 anti_alias = 2;
898
899 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
900 btr_nom_freq = stb0899_dvbs2_calc_srate(state);
901 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
902
903 correction = stb0899_dvbs2_calc_dev(state);
904 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
905 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
906 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
907
908 /* scale UWP+CSM frequency to sample rate*/
909 freq_adj = internal->srate / (internal->master_clk / 4096);
910 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
911}
912
913/*
914 * stb0899_dvbs2_set_btr_loopbw
915 * set bit timing loop bandwidth as a percentage of the symbol rate
916 */
917static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
918{
919 struct stb0899_internal *internal = &state->internal;
920 struct stb0899_config *config = state->config;
921
922 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
923 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
924 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
925 u32 decim, K, wn, k_direct, k_indirect;
926 u32 reg;
927
928 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
929 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
930 dec_rate = Log2Int(dec_ratio);
931 decim = (1 << dec_rate);
932
933 sym_peak *= 576000;
934 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
935 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
936 K = sym_peak / K;
937
938 if (K != 0) {
939 wn = (4 * zeta * zeta) + 1000000;
940 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
941
942 k_indirect = (wn * wn) / K;
943 k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/
944 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
945 k_direct *= 100;
946
947 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
948 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
949 k_btr1 = k_direct / (1 << k_direct_shift);
950 k_btr1 /= 10000;
951
952 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
953 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
954 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
955 k_btr0 /= 1000000;
956
957 k_btr2_rshft = 0;
958 if (k_btr0_rshft > 15) {
959 k_btr2_rshft = k_btr0_rshft - 15;
960 k_btr0_rshft = 15;
961 }
962 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
963 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
964 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
965 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
966 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
967 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
968 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
969 } else
970 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
971}
972
973/*
974 * stb0899_dvbs2_set_carr_freq
975 * set nominal frequency for carrier search
976 */
977static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
978{
979 struct stb0899_config *config = state->config;
980 s32 crl_nom_freq;
981 u32 reg;
982
983 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
984 crl_nom_freq *= carr_freq;
985 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
986 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
987 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
988}
989
990/*
991 * stb0899_dvbs2_init_calc
992 * Initialize DVBS2 UWP, CSM, carrier and timing loops
993 */
994static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
995{
996 struct stb0899_internal *internal = &state->internal;
997 s32 steps, step_size;
998 u32 range, reg;
999
1000 /* config uwp and csm */
1001 stb0899_dvbs2_config_uwp(state);
1002 stb0899_dvbs2_config_csm_auto(state);
1003
1004 /* initialize BTR */
1005 stb0899_dvbs2_set_srate(state);
1006 stb0899_dvbs2_set_btr_loopbw(state);
1007
1008 if (internal->srate / 1000000 >= 15)
1009 step_size = (1 << 17) / 5;
1010 else if (internal->srate / 1000000 >= 10)
1011 step_size = (1 << 17) / 7;
1012 else if (internal->srate / 1000000 >= 5)
1013 step_size = (1 << 17) / 10;
1014 else
1015 step_size = (1 << 17) / 4;
1016
1017 range = internal->srch_range / 1000000;
1018 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
1019 steps = (steps + 6) / 10;
1020 steps = (steps == 0) ? 1 : steps;
1021 if (steps % 2 == 0)
1022 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1023 (internal->step_size * (internal->srate / 20000000)),
1024 (internal->master_clk) / 1000000);
1025 else
1026 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1027
1028 /*Set Carrier Search params (zigzag, num steps and freq step size*/
1029 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1030 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1031 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1032 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1033 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1034}
1035
1036/*
1037 * stb0899_dvbs2_btr_init
1038 * initialize the timing loop
1039 */
1040static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1041{
1042 u32 reg;
1043
1044 /* set enable BTR loopback */
1045 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1046 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1047 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1048 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1049
1050 /* fix btr freq accum at 0 */
1051 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1052 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1053
1054 /* fix btr freq accum at 0 */
1055 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1056 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1057}
1058
1059/*
1060 * stb0899_dvbs2_reacquire
1061 * trigger a DVB-S2 acquisition
1062 */
1063static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1064{
1065 u32 reg = 0;
1066
1067 /* demod soft reset */
1068 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1069 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1070
1071 /*Reset Timing Loop */
1072 stb0899_dvbs2_btr_init(state);
1073
1074 /* reset Carrier loop */
1075 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1076 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1077 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1078 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1079 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1080
1081 /*release demod soft reset */
1082 reg = 0;
1083 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1084 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1085
1086 /* start acquisition process */
1087 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1088 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1089
1090 /* equalizer Init */
1091 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1092
1093 /*Start equilizer */
1094 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1095
1096 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1097 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1098 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1099 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1100 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1101 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1102
1103 /* RESET Packet delineator */
1104 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1105}
1106
1107/*
1108 * stb0899_dvbs2_get_dmd_status
1109 * get DVB-S2 Demod LOCK status
1110 */
1111static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1112{
1113 int time = -10, lock = 0, uwp, csm;
1114 u32 reg;
1115
1116 do {
1117 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1118 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1119 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1120 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1121 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1122 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1123 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1124 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1125 if (uwp && csm)
1126 lock = 1;
1127
1128 time += 10;
1129 msleep(10);
1130
1131 } while ((!lock) && (time <= timeout));
1132
1133 if (lock) {
1134 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1135 return DVBS2_DEMOD_LOCK;
1136 } else {
1137 return DVBS2_DEMOD_NOLOCK;
1138 }
1139}
1140
1141/*
1142 * stb0899_dvbs2_get_data_lock
1143 * get FEC status
1144 */
1145static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1146{
1147 int time = 0, lock = 0;
1148 u8 reg;
1149
1150 while ((!lock) && (time < timeout)) {
1151 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1152 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1153 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1154 time++;
1155 }
1156
1157 return lock;
1158}
1159
1160/*
1161 * stb0899_dvbs2_get_fec_status
1162 * get DVB-S2 FEC LOCK status
1163 */
1164static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1165{
1166 int time = 0, Locked;
1167
1168 do {
1169 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1170 time++;
1171 msleep(1);
1172
1173 } while ((!Locked) && (time < timeout));
1174
1175 if (Locked) {
1176 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1177 return DVBS2_FEC_LOCK;
1178 } else {
1179 return DVBS2_FEC_NOLOCK;
1180 }
1181}
1182
1183
1184/*
1185 * stb0899_dvbs2_init_csm
1186 * set parameters for manual mode
1187 */
1188static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1189{
1190 struct stb0899_internal *internal = &state->internal;
1191
1192 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1193 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1194 u32 csm1, csm2, csm3, csm4;
1195
1196 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1197 switch (modcod) {
1198 case STB0899_QPSK_12:
1199 gamma_acq = 25;
1200 gamma_rho_acq = 2700;
1201 gamma_trk = 12;
1202 gamma_rho_trk = 180;
1203 lock_count_thr = 8;
1204 break;
1205 case STB0899_QPSK_35:
1206 gamma_acq = 38;
1207 gamma_rho_acq = 7182;
1208 gamma_trk = 14;
1209 gamma_rho_trk = 308;
1210 lock_count_thr = 8;
1211 break;
1212 case STB0899_QPSK_23:
1213 gamma_acq = 42;
1214 gamma_rho_acq = 9408;
1215 gamma_trk = 17;
1216 gamma_rho_trk = 476;
1217 lock_count_thr = 8;
1218 break;
1219 case STB0899_QPSK_34:
1220 gamma_acq = 53;
1221 gamma_rho_acq = 16642;
1222 gamma_trk = 19;
1223 gamma_rho_trk = 646;
1224 lock_count_thr = 8;
1225 break;
1226 case STB0899_QPSK_45:
1227 gamma_acq = 53;
1228 gamma_rho_acq = 17119;
1229 gamma_trk = 22;
1230 gamma_rho_trk = 880;
1231 lock_count_thr = 8;
1232 break;
1233 case STB0899_QPSK_56:
1234 gamma_acq = 55;
1235 gamma_rho_acq = 19250;
1236 gamma_trk = 23;
1237 gamma_rho_trk = 989;
1238 lock_count_thr = 8;
1239 break;
1240 case STB0899_QPSK_89:
1241 gamma_acq = 60;
1242 gamma_rho_acq = 24240;
1243 gamma_trk = 24;
1244 gamma_rho_trk = 1176;
1245 lock_count_thr = 8;
1246 break;
1247 case STB0899_QPSK_910:
1248 gamma_acq = 66;
1249 gamma_rho_acq = 29634;
1250 gamma_trk = 24;
1251 gamma_rho_trk = 1176;
1252 lock_count_thr = 8;
1253 break;
1254 default:
1255 gamma_acq = 66;
1256 gamma_rho_acq = 29634;
1257 gamma_trk = 24;
1258 gamma_rho_trk = 1176;
1259 lock_count_thr = 8;
1260 break;
1261 }
1262
1263 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1264 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1265 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1266
1267 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1268 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1269 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1270 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1271
1272 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1273 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1274 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1275 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1276 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1277 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1278 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1279 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1280 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1281 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1282 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1283
1284 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1285 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1286 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1287 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1288 }
1289}
1290
1291/*
1292 * stb0899_dvbs2_get_srate
1293 * get DVB-S2 Symbol Rate
1294 */
1295static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1296{
1297 struct stb0899_internal *internal = &state->internal;
1298 struct stb0899_config *config = state->config;
1299
1300 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1301 int div1, div2, rem1, rem2;
1302
1303 div1 = config->btr_nco_bits / 2;
1304 div2 = config->btr_nco_bits - div1 - 1;
1305
1306 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1307
1308 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1309 decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1310 decimRate = (1 << decimRate);
1311
1312 intval1 = internal->master_clk / (1 << div1);
1313 intval2 = bTrNomFreq / (1 << div2);
1314
1315 rem1 = internal->master_clk % (1 << div1);
1316 rem2 = bTrNomFreq % (1 << div2);
1317 /* only for integer calculation */
1318 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1319 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1320
1321 return srate;
1322}
1323
1324/*
1325 * stb0899_dvbs2_algo
1326 * Search for signal, timing, carrier and data for a given
1327 * frequency in a given range
1328 */
1329enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1330{
1331 struct stb0899_internal *internal = &state->internal;
1332 enum stb0899_modcod modcod;
1333
1334 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1335 int i = 0;
1336 u32 reg, csm1;
1337
1338 if (internal->srate <= 2000000) {
1339 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
1340 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
1341 } else if (internal->srate <= 5000000) {
1342 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
1343 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
1344 } else if (internal->srate <= 10000000) {
1345 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
1346 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
1347 } else if (internal->srate <= 15000000) {
1348 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
1349 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
1350 } else if (internal->srate <= 20000000) {
1351 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
1352 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
1353 } else if (internal->srate <= 25000000) {
1354 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
1355 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1356 } else {
1357 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
1358 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1359 }
1360
1361 /* Maintain Stream Merger in reset during acquisition */
1362 reg = stb0899_read_reg(state, STB0899_TSTRES);
1363 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1364 stb0899_write_reg(state, STB0899_TSTRES, reg);
1365
1366 /* Move tuner to frequency */
1367 if (state->config->tuner_set_frequency)
1368 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1369 if (state->config->tuner_get_frequency)
1370 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1371
1372 /* Set IF AGC to acquisition */
1373 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1374 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
1375 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1376 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1377
1378 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1379 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1380 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1381
1382 /* Initialisation */
1383 stb0899_dvbs2_init_calc(state);
1384
1385 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1386 switch (internal->inversion) {
1387 case IQ_SWAP_OFF:
1388 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1389 break;
1390 case IQ_SWAP_ON:
1391 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1392 break;
1393 case IQ_SWAP_AUTO: /* use last successful search first */
1394 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1395 break;
1396 }
1397 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1398 stb0899_dvbs2_reacquire(state);
1399
1400 /* Wait for demod lock (UWP and CSM) */
1401 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1402
1403 if (internal->status == DVBS2_DEMOD_LOCK) {
1404 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1405 i = 0;
1406 /* Demod Locked, check FEC status */
1407 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1408
1409 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1410 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1411 /* Read the frequency offset*/
1412 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1413
1414 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1415 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1416 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1417 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, offsetfreq);
1418 stb0899_dvbs2_reacquire(state);
1419 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1420 i++;
1421 }
1422 }
1423
1424 if (internal->status != DVBS2_FEC_LOCK) {
1425 if (internal->inversion == IQ_SWAP_AUTO) {
1426 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1427 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1428 /* IQ Spectrum Inversion */
1429 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1430 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1431 /* start acquistion process */
1432 stb0899_dvbs2_reacquire(state);
1433
1434 /* Wait for demod lock (UWP and CSM) */
1435 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1436 if (internal->status == DVBS2_DEMOD_LOCK) {
1437 i = 0;
1438 /* Demod Locked, check FEC */
1439 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1440 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */
1441 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1442 /* Read the frequency offset*/
1443 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1444
1445 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1446 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1447 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1448 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, offsetfreq);
1449
1450 stb0899_dvbs2_reacquire(state);
1451 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1452 i++;
1453 }
1454 }
1455/*
1456 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1457 pParams->IQLocked = !iqSpectrum;
1458*/
1459 }
1460 }
1461 if (internal->status == DVBS2_FEC_LOCK) {
1462 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1463 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1464 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1465 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1466
1467 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1468 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1469 (pilots == 1)) {
1470
1471 stb0899_dvbs2_init_csm(state, pilots, modcod);
1472 /* Wait for UWP,CSM and data LOCK 20ms max */
1473 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1474
1475 i = 0;
1476 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1477 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1478 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1479 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1480 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1481 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1482 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1483
1484 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1485 i++;
1486 }
1487 }
1488
1489 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1490 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1491 (pilots == 1)) {
1492
1493 /* Equalizer Disable update */
1494 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1495 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1496 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1497 }
1498
1499 /* slow down the Equalizer once locked */
1500 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1501 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1502 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1503
1504 /* Store signal parameters */
1505 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1506
1507 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1508 offsetfreq *= (internal->master_clk / 1000000);
1509 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1510 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1511 offsetfreq *= -1;
1512
1513 internal->freq = internal->freq - offsetfreq;
1514 internal->srate = stb0899_dvbs2_get_srate(state);
1515
1516 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1517 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1518 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1519 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1520
1521 /* Set IF AGC to tracking */
1522 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1523 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
1524
1525 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1526 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1527 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1528
1529 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1530
1531 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1532 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1533 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1534 }
1535
1536 /* Release Stream Merger Reset */
1537 reg = stb0899_read_reg(state, STB0899_TSTRES);
1538 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1539 stb0899_write_reg(state, STB0899_TSTRES, reg);
1540
1541 return internal->status;
1542}
diff --git a/drivers/media/dvb/frontends/stb0899_drv.c b/drivers/media/dvb/frontends/stb0899_drv.c
new file mode 100644
index 00000000000..3cb9b48bac7
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_drv.c
@@ -0,0 +1,1963 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26
27#include <linux/dvb/frontend.h>
28#include "dvb_frontend.h"
29
30#include "stb0899_drv.h"
31#include "stb0899_priv.h"
32#include "stb0899_reg.h"
33
34static unsigned int verbose = 5;
35module_param(verbose, int, 0644);
36
37/* C/N in dB/10, NIRM/NIRL */
38static const struct stb0899_tab stb0899_cn_tab[] = {
39 { 200, 2600 },
40 { 190, 2700 },
41 { 180, 2860 },
42 { 170, 3020 },
43 { 160, 3210 },
44 { 150, 3440 },
45 { 140, 3710 },
46 { 130, 4010 },
47 { 120, 4360 },
48 { 110, 4740 },
49 { 100, 5190 },
50 { 90, 5670 },
51 { 80, 6200 },
52 { 70, 6770 },
53 { 60, 7360 },
54 { 50, 7970 },
55 { 40, 8250 },
56 { 30, 9000 },
57 { 20, 9450 },
58 { 15, 9600 },
59};
60
61/* DVB-S AGCIQ_VALUE vs. signal level in dBm/10.
62 * As measured, connected to a modulator.
63 * -8.0 to -50.0 dBm directly connected,
64 * -52.0 to -74.8 with extra attenuation.
65 * Cut-off to AGCIQ_VALUE = 0x80 below -74.8dBm.
66 * Crude linear extrapolation below -84.8dBm and above -8.0dBm.
67 */
68static const struct stb0899_tab stb0899_dvbsrf_tab[] = {
69 { -950, -128 },
70 { -748, -94 },
71 { -745, -92 },
72 { -735, -90 },
73 { -720, -87 },
74 { -670, -77 },
75 { -640, -70 },
76 { -610, -62 },
77 { -600, -60 },
78 { -590, -56 },
79 { -560, -41 },
80 { -540, -25 },
81 { -530, -17 },
82 { -520, -11 },
83 { -500, 1 },
84 { -490, 6 },
85 { -480, 10 },
86 { -440, 22 },
87 { -420, 27 },
88 { -400, 31 },
89 { -380, 34 },
90 { -340, 40 },
91 { -320, 43 },
92 { -280, 48 },
93 { -250, 52 },
94 { -230, 55 },
95 { -180, 61 },
96 { -140, 66 },
97 { -90, 73 },
98 { -80, 74 },
99 { 500, 127 }
100};
101
102/* DVB-S2 IF_AGC_GAIN vs. signal level in dBm/10.
103 * As measured, connected to a modulator.
104 * -8.0 to -50.1 dBm directly connected,
105 * -53.0 to -76.6 with extra attenuation.
106 * Cut-off to IF_AGC_GAIN = 0x3fff below -76.6dBm.
107 * Crude linear extrapolation below -76.6dBm and above -8.0dBm.
108 */
109static const struct stb0899_tab stb0899_dvbs2rf_tab[] = {
110 { 700, 0 },
111 { -80, 3217 },
112 { -150, 3893 },
113 { -190, 4217 },
114 { -240, 4621 },
115 { -280, 4945 },
116 { -320, 5273 },
117 { -350, 5545 },
118 { -370, 5741 },
119 { -410, 6147 },
120 { -450, 6671 },
121 { -490, 7413 },
122 { -501, 7665 },
123 { -530, 8767 },
124 { -560, 10219 },
125 { -580, 10939 },
126 { -590, 11518 },
127 { -600, 11723 },
128 { -650, 12659 },
129 { -690, 13219 },
130 { -730, 13645 },
131 { -750, 13909 },
132 { -766, 14153 },
133 { -999, 16383 }
134};
135
136/* DVB-S2 Es/N0 quant in dB/100 vs read value * 100*/
137struct stb0899_tab stb0899_quant_tab[] = {
138 { 0, 0 },
139 { 0, 100 },
140 { 600, 200 },
141 { 950, 299 },
142 { 1200, 398 },
143 { 1400, 501 },
144 { 1560, 603 },
145 { 1690, 700 },
146 { 1810, 804 },
147 { 1910, 902 },
148 { 2000, 1000 },
149 { 2080, 1096 },
150 { 2160, 1202 },
151 { 2230, 1303 },
152 { 2350, 1496 },
153 { 2410, 1603 },
154 { 2460, 1698 },
155 { 2510, 1799 },
156 { 2600, 1995 },
157 { 2650, 2113 },
158 { 2690, 2213 },
159 { 2720, 2291 },
160 { 2760, 2399 },
161 { 2800, 2512 },
162 { 2860, 2692 },
163 { 2930, 2917 },
164 { 2960, 3020 },
165 { 3010, 3199 },
166 { 3040, 3311 },
167 { 3060, 3388 },
168 { 3120, 3631 },
169 { 3190, 3936 },
170 { 3400, 5012 },
171 { 3610, 6383 },
172 { 3800, 7943 },
173 { 4210, 12735 },
174 { 4500, 17783 },
175 { 4690, 22131 },
176 { 4810, 25410 }
177};
178
179/* DVB-S2 Es/N0 estimate in dB/100 vs read value */
180struct stb0899_tab stb0899_est_tab[] = {
181 { 0, 0 },
182 { 0, 1 },
183 { 301, 2 },
184 { 1204, 16 },
185 { 1806, 64 },
186 { 2408, 256 },
187 { 2709, 512 },
188 { 3010, 1023 },
189 { 3311, 2046 },
190 { 3612, 4093 },
191 { 3823, 6653 },
192 { 3913, 8185 },
193 { 4010, 10233 },
194 { 4107, 12794 },
195 { 4214, 16368 },
196 { 4266, 18450 },
197 { 4311, 20464 },
198 { 4353, 22542 },
199 { 4391, 24604 },
200 { 4425, 26607 },
201 { 4457, 28642 },
202 { 4487, 30690 },
203 { 4515, 32734 },
204 { 4612, 40926 },
205 { 4692, 49204 },
206 { 4816, 65464 },
207 { 4913, 81846 },
208 { 4993, 98401 },
209 { 5060, 114815 },
210 { 5118, 131220 },
211 { 5200, 158489 },
212 { 5300, 199526 },
213 { 5400, 251189 },
214 { 5500, 316228 },
215 { 5600, 398107 },
216 { 5720, 524807 },
217 { 5721, 526017 },
218};
219
220int _stb0899_read_reg(struct stb0899_state *state, unsigned int reg)
221{
222 int ret;
223
224 u8 b0[] = { reg >> 8, reg & 0xff };
225 u8 buf;
226
227 struct i2c_msg msg[] = {
228 {
229 .addr = state->config->demod_address,
230 .flags = 0,
231 .buf = b0,
232 .len = 2
233 },{
234 .addr = state->config->demod_address,
235 .flags = I2C_M_RD,
236 .buf = &buf,
237 .len = 1
238 }
239 };
240
241 ret = i2c_transfer(state->i2c, msg, 2);
242 if (ret != 2) {
243 if (ret != -ERESTARTSYS)
244 dprintk(verbose, FE_ERROR, 1,
245 "Read error, Reg=[0x%02x], Status=%d",
246 reg, ret);
247
248 return ret < 0 ? ret : -EREMOTEIO;
249 }
250 if (unlikely(verbose >= FE_DEBUGREG))
251 dprintk(verbose, FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
252 reg, buf);
253
254
255 return (unsigned int)buf;
256}
257
258int stb0899_read_reg(struct stb0899_state *state, unsigned int reg)
259{
260 int result;
261
262 result = _stb0899_read_reg(state, reg);
263 /*
264 * Bug ID 9:
265 * access to 0xf2xx/0xf6xx
266 * must be followed by read from 0xf2ff/0xf6ff.
267 */
268 if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
269 (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
270 _stb0899_read_reg(state, (reg | 0x00ff));
271
272 return result;
273}
274
275u32 _stb0899_read_s2reg(struct stb0899_state *state,
276 u32 stb0899_i2cdev,
277 u32 stb0899_base_addr,
278 u16 stb0899_reg_offset)
279{
280 int status;
281 u32 data;
282 u8 buf[7] = { 0 };
283 u16 tmpaddr;
284
285 u8 buf_0[] = {
286 GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */
287 GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */
288 GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */
289 GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */
290 GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */
291 GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */
292 };
293 u8 buf_1[] = {
294 0x00, /* 0xf3 Reg Offset */
295 0x00, /* 0x44 Reg Offset */
296 };
297
298 struct i2c_msg msg_0 = {
299 .addr = state->config->demod_address,
300 .flags = 0,
301 .buf = buf_0,
302 .len = 6
303 };
304
305 struct i2c_msg msg_1 = {
306 .addr = state->config->demod_address,
307 .flags = 0,
308 .buf = buf_1,
309 .len = 2
310 };
311
312 struct i2c_msg msg_r = {
313 .addr = state->config->demod_address,
314 .flags = I2C_M_RD,
315 .buf = buf,
316 .len = 4
317 };
318
319 tmpaddr = stb0899_reg_offset & 0xff00;
320 if (!(stb0899_reg_offset & 0x8))
321 tmpaddr = stb0899_reg_offset | 0x20;
322
323 buf_1[0] = GETBYTE(tmpaddr, BYTE1);
324 buf_1[1] = GETBYTE(tmpaddr, BYTE0);
325
326 status = i2c_transfer(state->i2c, &msg_0, 1);
327 if (status < 1) {
328 if (status != -ERESTARTSYS)
329 printk(KERN_ERR "%s ERR(1), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
330 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
331
332 goto err;
333 }
334
335 /* Dummy */
336 status = i2c_transfer(state->i2c, &msg_1, 1);
337 if (status < 1)
338 goto err;
339
340 status = i2c_transfer(state->i2c, &msg_r, 1);
341 if (status < 1)
342 goto err;
343
344 buf_1[0] = GETBYTE(stb0899_reg_offset, BYTE1);
345 buf_1[1] = GETBYTE(stb0899_reg_offset, BYTE0);
346
347 /* Actual */
348 status = i2c_transfer(state->i2c, &msg_1, 1);
349 if (status < 1) {
350 if (status != -ERESTARTSYS)
351 printk(KERN_ERR "%s ERR(2), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
352 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
353 goto err;
354 }
355
356 status = i2c_transfer(state->i2c, &msg_r, 1);
357 if (status < 1) {
358 if (status != -ERESTARTSYS)
359 printk(KERN_ERR "%s ERR(3), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
360 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
361 return status < 0 ? status : -EREMOTEIO;
362 }
363
364 data = MAKEWORD32(buf[3], buf[2], buf[1], buf[0]);
365 if (unlikely(state->verbose >= FE_DEBUGREG))
366 printk(KERN_DEBUG "%s Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n",
367 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, data);
368
369 return data;
370
371err:
372 return status < 0 ? status : -EREMOTEIO;
373}
374
375int stb0899_write_s2reg(struct stb0899_state *state,
376 u32 stb0899_i2cdev,
377 u32 stb0899_base_addr,
378 u16 stb0899_reg_offset,
379 u32 stb0899_data)
380{
381 int status;
382
383 /* Base Address Setup */
384 u8 buf_0[] = {
385 GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */
386 GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */
387 GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */
388 GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */
389 GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */
390 GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */
391 };
392 u8 buf_1[] = {
393 0x00, /* 0xf3 Reg Offset */
394 0x00, /* 0x44 Reg Offset */
395 0x00, /* data */
396 0x00, /* data */
397 0x00, /* data */
398 0x00, /* data */
399 };
400
401 struct i2c_msg msg_0 = {
402 .addr = state->config->demod_address,
403 .flags = 0,
404 .buf = buf_0,
405 .len = 6
406 };
407
408 struct i2c_msg msg_1 = {
409 .addr = state->config->demod_address,
410 .flags = 0,
411 .buf = buf_1,
412 .len = 6
413 };
414
415 buf_1[0] = GETBYTE(stb0899_reg_offset, BYTE1);
416 buf_1[1] = GETBYTE(stb0899_reg_offset, BYTE0);
417 buf_1[2] = GETBYTE(stb0899_data, BYTE0);
418 buf_1[3] = GETBYTE(stb0899_data, BYTE1);
419 buf_1[4] = GETBYTE(stb0899_data, BYTE2);
420 buf_1[5] = GETBYTE(stb0899_data, BYTE3);
421
422 if (unlikely(state->verbose >= FE_DEBUGREG))
423 printk(KERN_DEBUG "%s Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n",
424 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data);
425
426 status = i2c_transfer(state->i2c, &msg_0, 1);
427 if (unlikely(status < 1)) {
428 if (status != -ERESTARTSYS)
429 printk(KERN_ERR "%s ERR (1), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n",
430 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data, status);
431 goto err;
432 }
433 status = i2c_transfer(state->i2c, &msg_1, 1);
434 if (unlikely(status < 1)) {
435 if (status != -ERESTARTSYS)
436 printk(KERN_ERR "%s ERR (2), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n",
437 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data, status);
438
439 return status < 0 ? status : -EREMOTEIO;
440 }
441
442 return 0;
443
444err:
445 return status < 0 ? status : -EREMOTEIO;
446}
447
448int stb0899_read_regs(struct stb0899_state *state, unsigned int reg, u8 *buf, size_t count)
449{
450 int status;
451
452 u8 b0[] = { reg >> 8, reg & 0xff };
453
454 struct i2c_msg msg[] = {
455 {
456 .addr = state->config->demod_address,
457 .flags = 0,
458 .buf = b0,
459 .len = 2
460 },{
461 .addr = state->config->demod_address,
462 .flags = I2C_M_RD,
463 .buf = buf,
464 .len = count
465 }
466 };
467
468 status = i2c_transfer(state->i2c, msg, 2);
469 if (status != 2) {
470 if (status != -ERESTARTSYS)
471 printk(KERN_ERR "%s Read error, Reg=[0x%04x], Count=%u, Status=%d\n",
472 __func__, reg, count, status);
473 goto err;
474 }
475 /*
476 * Bug ID 9:
477 * access to 0xf2xx/0xf6xx
478 * must be followed by read from 0xf2ff/0xf6ff.
479 */
480 if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
481 (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
482 _stb0899_read_reg(state, (reg | 0x00ff));
483
484 if (unlikely(state->verbose >= FE_DEBUGREG)) {
485 int i;
486
487 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
488 for (i = 0; i < count; i++) {
489 printk(" %02x", buf[i]);
490 }
491 printk("\n");
492 }
493
494 return 0;
495err:
496 return status < 0 ? status : -EREMOTEIO;
497}
498
499int stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, size_t count)
500{
501 int ret;
502 u8 buf[2 + count];
503 struct i2c_msg i2c_msg = {
504 .addr = state->config->demod_address,
505 .flags = 0,
506 .buf = buf,
507 .len = 2 + count
508 };
509
510 buf[0] = reg >> 8;
511 buf[1] = reg & 0xff;
512 memcpy(&buf[2], data, count);
513
514 if (unlikely(state->verbose >= FE_DEBUGREG)) {
515 int i;
516
517 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
518 for (i = 0; i < count; i++)
519 printk(" %02x", data[i]);
520 printk("\n");
521 }
522 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
523
524 /*
525 * Bug ID 9:
526 * access to 0xf2xx/0xf6xx
527 * must be followed by read from 0xf2ff/0xf6ff.
528 */
529 if ((((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
530 stb0899_read_reg(state, (reg | 0x00ff));
531
532 if (ret != 1) {
533 if (ret != -ERESTARTSYS)
534 dprintk(verbose, FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
535 reg, data[0], count, ret);
536 return ret < 0 ? ret : -EREMOTEIO;
537 }
538
539 return 0;
540}
541
542int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data)
543{
544 return stb0899_write_regs(state, reg, &data, 1);
545}
546
547/*
548 * stb0899_get_mclk
549 * Get STB0899 master clock frequency
550 * ExtClk: external clock frequency (Hz)
551 */
552static u32 stb0899_get_mclk(struct stb0899_state *state)
553{
554 u32 mclk = 90000000, div = 0;
555
556 div = stb0899_read_reg(state, STB0899_NCOARSE);
557 mclk = (div + 1) * state->config->xtal_freq / 6;
558 dprintk(verbose, FE_DEBUG, 1, "div=%d, mclk=%d", div, mclk);
559
560 return mclk;
561}
562
563/*
564 * stb0899_set_mclk
565 * Set STB0899 master Clock frequency
566 * Mclk: demodulator master clock
567 * ExtClk: external clock frequency (Hz)
568 */
569static void stb0899_set_mclk(struct stb0899_state *state, u32 Mclk)
570{
571 struct stb0899_internal *internal = &state->internal;
572 u8 mdiv = 0;
573
574 dprintk(verbose, FE_DEBUG, 1, "state->config=%p", state->config);
575 mdiv = ((6 * Mclk) / state->config->xtal_freq) - 1;
576 dprintk(verbose, FE_DEBUG, 1, "mdiv=%d", mdiv);
577
578 stb0899_write_reg(state, STB0899_NCOARSE, mdiv);
579 internal->master_clk = stb0899_get_mclk(state);
580
581 dprintk(verbose, FE_DEBUG, 1, "MasterCLOCK=%d", internal->master_clk);
582}
583
584static void stb0899_release(struct dvb_frontend *fe)
585{
586 struct stb0899_state *state = fe->demodulator_priv;
587
588 dprintk(verbose, FE_DEBUG, 1, "Release Frontend");
589 kfree(state);
590}
591
592/*
593 * stb0899_get_alpha
594 * return: rolloff
595 */
596static int stb0899_get_alpha(struct stb0899_state *state)
597{
598 u8 mode_coeff;
599
600 mode_coeff = stb0899_read_reg(state, STB0899_DEMOD);
601
602 if (STB0899_GETFIELD(MODECOEFF, mode_coeff) == 1)
603 return 20;
604 else
605 return 35;
606}
607
608/*
609 * stb0899_init_calc
610 */
611static void stb0899_init_calc(struct stb0899_state *state)
612{
613 struct stb0899_internal *internal = &state->internal;
614 int master_clk;
615 u8 agc[1];
616 u8 agc1cn;
617 u32 reg;
618
619 /* Read registers (in burst mode) */
620 agc1cn = stb0899_read_reg(state, STB0899_AGC1CN);
621 stb0899_read_regs(state, STB0899_AGC1REF, agc, 2); /* AGC1R and AGC2O */
622
623 /* Initial calculations */
624 master_clk = stb0899_get_mclk(state);
625 internal->t_agc1 = 0;
626 internal->t_agc2 = 0;
627 internal->master_clk = master_clk;
628 internal->mclk = master_clk / 65536L;
629 internal->rolloff = stb0899_get_alpha(state);
630
631 /* DVBS2 Initial calculations */
632 /* Set AGC value to the middle */
633 internal->agc_gain = 8154;
634 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
635 STB0899_SETFIELD_VAL(IF_GAIN_INIT, reg, internal->agc_gain);
636 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
637
638 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, RRC_ALPHA);
639 internal->rrc_alpha = STB0899_GETFIELD(RRC_ALPHA, reg);
640
641 internal->center_freq = 0;
642 internal->av_frame_coarse = 10;
643 internal->av_frame_fine = 20;
644 internal->step_size = 2;
645/*
646 if ((pParams->SpectralInv == FE_IQ_NORMAL) || (pParams->SpectralInv == FE_IQ_AUTO))
647 pParams->IQLocked = 0;
648 else
649 pParams->IQLocked = 1;
650*/
651}
652
653static int stb0899_wait_diseqc_fifo_empty(struct stb0899_state *state, int timeout)
654{
655 u8 reg = 0;
656 unsigned long start = jiffies;
657
658 while (1) {
659 reg = stb0899_read_reg(state, STB0899_DISSTATUS);
660 if (!STB0899_GETFIELD(FIFOFULL, reg))
661 break;
662 if ((jiffies - start) > timeout) {
663 dprintk(verbose, FE_ERROR, 1, "timed out !!");
664 return -ETIMEDOUT;
665 }
666 }
667
668 return 0;
669}
670
671static int stb0899_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
672{
673 struct stb0899_state *state = fe->demodulator_priv;
674 u8 reg, i;
675
676 if (cmd->msg_len > 8)
677 return -EINVAL;
678
679 /* enable FIFO precharge */
680 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
681 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 1);
682 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
683 for (i = 0; i < cmd->msg_len; i++) {
684 /* wait for FIFO empty */
685 if (stb0899_wait_diseqc_fifo_empty(state, 10) < 0)
686 return -ETIMEDOUT;
687
688 stb0899_write_reg(state, STB0899_DISFIFO, cmd->msg[i]);
689 }
690 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
691 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0);
692 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
693
694 return 0;
695}
696
697static int stb0899_wait_diseqc_rxidle(struct stb0899_state *state, int timeout)
698{
699 u8 reg = 0;
700 unsigned long start = jiffies;
701
702 while (!STB0899_GETFIELD(RXEND, reg)) {
703 reg = stb0899_read_reg(state, STB0899_DISRX_ST0);
704 if (jiffies - start > timeout) {
705 dprintk(verbose, FE_ERROR, 1, "timed out!!");
706 return -ETIMEDOUT;
707 }
708 msleep(10);
709 }
710
711 return 0;
712}
713
714static int stb0899_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
715{
716 struct stb0899_state *state = fe->demodulator_priv;
717 u8 reg, length = 0, i;
718 int result;
719
720 if (stb0899_wait_diseqc_rxidle(state, 100) < 0)
721 return -ETIMEDOUT;
722
723 reg = stb0899_read_reg(state, STB0899_DISRX_ST0);
724 if (STB0899_GETFIELD(RXEND, reg)) {
725
726 reg = stb0899_read_reg(state, STB0899_DISRX_ST1);
727 length = STB0899_GETFIELD(FIFOBYTENBR, reg);
728
729 if (length > sizeof (reply->msg)) {
730 result = -EOVERFLOW;
731 goto exit;
732 }
733 reply->msg_len = length;
734
735 /* extract data */
736 for (i = 0; i < length; i++)
737 reply->msg[i] = stb0899_read_reg(state, STB0899_DISFIFO);
738 }
739
740 return 0;
741exit:
742
743 return result;
744}
745
746static int stb0899_wait_diseqc_txidle(struct stb0899_state *state, int timeout)
747{
748 u8 reg = 0;
749 unsigned long start = jiffies;
750
751 while (!STB0899_GETFIELD(TXIDLE, reg)) {
752 reg = stb0899_read_reg(state, STB0899_DISSTATUS);
753 if (jiffies - start > timeout) {
754 dprintk(verbose, FE_ERROR, 1, "timed out!!");
755 return -ETIMEDOUT;
756 }
757 msleep(10);
758 }
759 return 0;
760}
761
762static int stb0899_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
763{
764 struct stb0899_state *state = fe->demodulator_priv;
765 u8 reg, old_state;
766
767 /* wait for diseqc idle */
768 if (stb0899_wait_diseqc_txidle(state, 100) < 0)
769 return -ETIMEDOUT;
770
771 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
772 old_state = reg;
773 /* set to burst mode */
774 STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x02);
775 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01);
776 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
777 switch (burst) {
778 case SEC_MINI_A:
779 /* unmodulated */
780 stb0899_write_reg(state, STB0899_DISFIFO, 0x00);
781 break;
782 case SEC_MINI_B:
783 /* modulated */
784 stb0899_write_reg(state, STB0899_DISFIFO, 0xff);
785 break;
786 }
787 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
788 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x00);
789 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
790 /* wait for diseqc idle */
791 if (stb0899_wait_diseqc_txidle(state, 100) < 0)
792 return -ETIMEDOUT;
793
794 /* restore state */
795 stb0899_write_reg(state, STB0899_DISCNTRL1, old_state);
796
797 return 0;
798}
799
800
801static int stb0899_sleep(struct dvb_frontend *fe)
802{
803 struct stb0899_state *state = fe->demodulator_priv;
804 u8 reg;
805
806 dprintk(verbose, FE_DEBUG, 1, "Going to Sleep .. (Really tired .. :-))");
807
808 reg = stb0899_read_reg(state, STB0899_SYNTCTRL);
809 STB0899_SETFIELD_VAL(STANDBY, reg, 1);
810 stb0899_write_reg(state, STB0899_SYNTCTRL, reg);
811
812 return 0;
813}
814
815static int stb0899_wakeup(struct dvb_frontend *fe)
816{
817 int rc;
818 struct stb0899_state *state = fe->demodulator_priv;
819
820 if ((rc = stb0899_write_reg(state, STB0899_SYNTCTRL, STB0899_SELOSCI)))
821 return rc;
822 /* Activate all clocks; DVB-S2 registers are inaccessible otherwise. */
823 if ((rc = stb0899_write_reg(state, STB0899_STOPCLK1, 0x00)))
824 return rc;
825 if ((rc = stb0899_write_reg(state, STB0899_STOPCLK2, 0x00)))
826 return rc;
827
828 return 0;
829}
830
831static int stb0899_init(struct dvb_frontend *fe)
832{
833 int i;
834 struct stb0899_state *state = fe->demodulator_priv;
835 struct stb0899_config *config = state->config;
836
837 dprintk(verbose, FE_DEBUG, 1, "Initializing STB0899 ... ");
838// mutex_init(&state->search_lock);
839
840 /* init device */
841 dprintk(verbose, FE_DEBUG, 1, "init device");
842 for (i = 0; config->init_dev[i].address != 0xffff; i++)
843 stb0899_write_reg(state, config->init_dev[i].address, config->init_dev[i].data);
844
845 dprintk(verbose, FE_DEBUG, 1, "init S2 demod");
846 /* init S2 demod */
847 for (i = 0; config->init_s2_demod[i].offset != 0xffff; i++)
848 stb0899_write_s2reg(state, STB0899_S2DEMOD,
849 config->init_s2_demod[i].base_address,
850 config->init_s2_demod[i].offset,
851 config->init_s2_demod[i].data);
852
853 dprintk(verbose, FE_DEBUG, 1, "init S1 demod");
854 /* init S1 demod */
855 for (i = 0; config->init_s1_demod[i].address != 0xffff; i++)
856 stb0899_write_reg(state, config->init_s1_demod[i].address, config->init_s1_demod[i].data);
857
858 dprintk(verbose, FE_DEBUG, 1, "init S2 FEC");
859 /* init S2 fec */
860 for (i = 0; config->init_s2_fec[i].offset != 0xffff; i++)
861 stb0899_write_s2reg(state, STB0899_S2FEC,
862 config->init_s2_fec[i].base_address,
863 config->init_s2_fec[i].offset,
864 config->init_s2_fec[i].data);
865
866 dprintk(verbose, FE_DEBUG, 1, "init TST");
867 /* init test */
868 for (i = 0; config->init_tst[i].address != 0xffff; i++)
869 stb0899_write_reg(state, config->init_tst[i].address, config->init_tst[i].data);
870
871 stb0899_init_calc(state);
872// stb0899_diseqc_init(state);
873
874 return 0;
875}
876
877static int stb0899_table_lookup(const struct stb0899_tab *tab, int max, int val)
878{
879 int res = 0;
880 int min = 0, med;
881
882 if (val < tab[min].read)
883 res = tab[min].real;
884 else if (val >= tab[max].read)
885 res = tab[max].real;
886 else {
887 while ((max - min) > 1) {
888 med = (max + min) / 2;
889 if (val >= tab[min].read && val < tab[med].read)
890 max = med;
891 else
892 min = med;
893 }
894 res = ((val - tab[min].read) *
895 (tab[max].real - tab[min].real) /
896 (tab[max].read - tab[min].read)) +
897 tab[min].real;
898 }
899
900 return res;
901}
902
903static int stb0899_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
904{
905 struct stb0899_state *state = fe->demodulator_priv;
906 struct stb0899_internal *internal = &state->internal;
907
908 int val;
909 u32 reg;
910 switch (state->delsys) {
911 case DVBFE_DELSYS_DVBS:
912 case DVBFE_DELSYS_DSS:
913 if (internal->lock) {
914 reg = stb0899_read_reg(state, STB0899_VSTATUS);
915 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
916
917 reg = stb0899_read_reg(state, STB0899_AGCIQIN);
918 val = (s32)(s8)STB0899_GETFIELD(AGCIQVALUE, reg);
919
920 *strength = stb0899_table_lookup(stb0899_dvbsrf_tab, ARRAY_SIZE(stb0899_dvbsrf_tab) - 1, val);
921 *strength += 750;
922 dprintk(verbose, FE_DEBUG, 1, "AGCIQVALUE = 0x%02x, C = %d * 0.1 dBm",
923 val & 0xff, *strength);
924 }
925 }
926 break;
927 case DVBFE_DELSYS_DVBS2:
928 if (internal->lock) {
929 reg = STB0899_READ_S2REG(STB0899_DEMOD, IF_AGC_GAIN);
930 val = STB0899_GETFIELD(IF_AGC_GAIN, reg);
931
932 *strength = stb0899_table_lookup(stb0899_dvbs2rf_tab, ARRAY_SIZE(stb0899_dvbs2rf_tab) - 1, val);
933 *strength += 750;
934 dprintk(verbose, FE_DEBUG, 1, "IF_AGC_GAIN = 0x%04x, C = %d * 0.1 dBm",
935 val & 0x3fff, *strength);
936 }
937 break;
938 default:
939 dprintk(verbose, FE_DEBUG, 1, "Unsupported delivery system");
940 break;
941 }
942
943 return 0;
944}
945
946static int stb0899_read_snr(struct dvb_frontend *fe, u16 *snr)
947{
948 struct stb0899_state *state = fe->demodulator_priv;
949 struct stb0899_internal *internal = &state->internal;
950
951 unsigned int val, quant, quantn = -1, est, estn = -1;
952 u8 buf[2];
953 u32 reg;
954
955 reg = stb0899_read_reg(state, STB0899_VSTATUS);
956 switch (state->delsys) {
957 case DVBFE_DELSYS_DVBS:
958 case DVBFE_DELSYS_DSS:
959 if (internal->lock) {
960 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
961
962 stb0899_read_regs(state, STB0899_NIRM, buf, 2);
963 val = MAKEWORD16(buf[0], buf[1]);
964
965 *snr = stb0899_table_lookup(stb0899_cn_tab, ARRAY_SIZE(stb0899_cn_tab) - 1, val);
966 dprintk(verbose, FE_DEBUG, 1, "NIR = 0x%02x%02x = %u, C/N = %d * 0.1 dBm\n",
967 buf[0], buf[1], val, *snr);
968 }
969 }
970 break;
971 case DVBFE_DELSYS_DVBS2:
972 if (internal->lock) {
973 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
974 quant = STB0899_GETFIELD(UWP_ESN0_QUANT, reg);
975 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
976 est = STB0899_GETFIELD(ESN0_EST, reg);
977 if (est == 1)
978 val = 301; /* C/N = 30.1 dB */
979 else if (est == 2)
980 val = 270; /* C/N = 27.0 dB */
981 else {
982 /* quantn = 100 * log(quant^2) */
983 quantn = stb0899_table_lookup(stb0899_quant_tab, ARRAY_SIZE(stb0899_quant_tab) - 1, quant * 100);
984 /* estn = 100 * log(est) */
985 estn = stb0899_table_lookup(stb0899_est_tab, ARRAY_SIZE(stb0899_est_tab) - 1, est);
986 /* snr(dBm/10) = -10*(log(est)-log(quant^2)) => snr(dBm/10) = (100*log(quant^2)-100*log(est))/10 */
987 val = (quantn - estn) / 10;
988 }
989 *snr = val;
990 dprintk(verbose, FE_DEBUG, 1, "Es/N0 quant = %d (%d) estimate = %u (%d), C/N = %d * 0.1 dBm",
991 quant, quantn, est, estn, val);
992 }
993 break;
994 default:
995 dprintk(verbose, FE_DEBUG, 1, "Unsupported delivery system");
996 break;
997 }
998
999 return 0;
1000}
1001
1002static int stb0899_read_status(struct dvb_frontend *fe, enum fe_status *status)
1003{
1004 struct stb0899_state *state = fe->demodulator_priv;
1005 struct stb0899_internal *internal = &state->internal;
1006 u8 reg;
1007 *status = 0;
1008
1009 switch (state->delsys) {
1010 case DVBFE_DELSYS_DVBS:
1011 case DVBFE_DELSYS_DSS:
1012 dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S/DSS");
1013 if (internal->lock) {
1014 reg = stb0899_read_reg(state, STB0899_VSTATUS);
1015 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
1016 dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_CARRIER | FE_HAS_LOCK");
1017 *status |= FE_HAS_CARRIER | FE_HAS_LOCK;
1018
1019 reg = stb0899_read_reg(state, STB0899_PLPARM);
1020 if (STB0899_GETFIELD(VITCURPUN, reg)) {
1021 dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_VITERBI | FE_HAS_SYNC");
1022 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
1023 }
1024 }
1025 }
1026 break;
1027 case DVBFE_DELSYS_DVBS2:
1028 dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S2");
1029 if (internal->lock) {
1030 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1031 if (STB0899_GETFIELD(UWP_LOCK, reg) && STB0899_GETFIELD(CSM_LOCK, reg)) {
1032 *status |= FE_HAS_CARRIER;
1033 dprintk(state->verbose, FE_DEBUG, 1,
1034 "UWP & CSM Lock ! ---> DVB-S2 FE_HAS_CARRIER");
1035
1036 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1037 if (STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg)) {
1038 *status |= FE_HAS_LOCK;
1039 dprintk(state->verbose, FE_DEBUG, 1,
1040 "Packet Delineator Locked ! -----> DVB-S2 FE_HAS_LOCK");
1041
1042 }
1043 if (STB0899_GETFIELD(CONTINUOUS_STREAM, reg)) {
1044 *status |= FE_HAS_VITERBI;
1045 dprintk(state->verbose, FE_DEBUG, 1,
1046 "Packet Delineator found VITERBI ! -----> DVB-S2 FE_HAS_VITERBI");
1047 }
1048 if (STB0899_GETFIELD(ACCEPTED_STREAM, reg)) {
1049 *status |= FE_HAS_SYNC;
1050 dprintk(state->verbose, FE_DEBUG, 1,
1051 "Packet Delineator found SYNC ! -----> DVB-S2 FE_HAS_SYNC");
1052 }
1053 }
1054 }
1055 break;
1056 default:
1057 dprintk(verbose, FE_DEBUG, 1, "Unsupported delivery system");
1058 break;
1059 }
1060 return 0;
1061}
1062
1063/*
1064 * stb0899_get_error
1065 * viterbi error for DVB-S/DSS
1066 * packet error for DVB-S2
1067 * Bit Error Rate or Packet Error Rate * 10 ^ 7
1068 */
1069static int stb0899_read_ber(struct dvb_frontend *fe, u32 *ber)
1070{
1071 struct stb0899_state *state = fe->demodulator_priv;
1072 struct stb0899_internal *internal = &state->internal;
1073
1074 u8 lsb, msb;
1075 u32 i;
1076
1077 *ber = 0;
1078
1079 switch (state->delsys) {
1080 case DVBFE_DELSYS_DVBS:
1081 case DVBFE_DELSYS_DSS:
1082 if (internal->lock) {
1083 /* average 5 BER values */
1084 for (i = 0; i < 5; i++) {
1085 msleep(100);
1086 lsb = stb0899_read_reg(state, STB0899_ECNT1L);
1087 msb = stb0899_read_reg(state, STB0899_ECNT1M);
1088 *ber += MAKEWORD16(msb, lsb);
1089 }
1090 *ber /= 5;
1091 /* Viterbi Check */
1092 if (STB0899_GETFIELD(VSTATUS_PRFVIT, internal->v_status)) {
1093 /* Error Rate */
1094 *ber *= 9766;
1095 /* ber = ber * 10 ^ 7 */
1096 *ber /= (-1 + (1 << (2 * STB0899_GETFIELD(NOE, internal->err_ctrl))));
1097 *ber /= 8;
1098 }
1099 }
1100 break;
1101 case DVBFE_DELSYS_DVBS2:
1102 if (internal->lock) {
1103 /* Average 5 PER values */
1104 for (i = 0; i < 5; i++) {
1105 msleep(100);
1106 lsb = stb0899_read_reg(state, STB0899_ECNT1L);
1107 msb = stb0899_read_reg(state, STB0899_ECNT1M);
1108 *ber += MAKEWORD16(msb, lsb);
1109 }
1110 /* ber = ber * 10 ^ 7 */
1111 *ber *= 10000000;
1112 *ber /= (-1 + (1 << (4 + 2 * STB0899_GETFIELD(NOE, internal->err_ctrl))));
1113 }
1114 break;
1115 default:
1116 dprintk(verbose, FE_DEBUG, 1, "Unsupported delivery system");
1117 }
1118
1119 return 0;
1120}
1121
1122static int stb0899_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
1123{
1124 struct stb0899_state *state = fe->demodulator_priv;
1125
1126 switch (voltage) {
1127 case SEC_VOLTAGE_13:
1128 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
1129 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
1130 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x00);
1131 break;
1132 case SEC_VOLTAGE_18:
1133 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x02);
1134 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
1135 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
1136 break;
1137 case SEC_VOLTAGE_OFF:
1138 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
1139 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x82);
1140 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
1141 break;
1142 default:
1143 return -EINVAL;
1144 }
1145
1146 return 0;
1147}
1148
1149static int stb0899_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1150{
1151 struct stb0899_state *state = fe->demodulator_priv;
1152 struct stb0899_internal *internal = &state->internal;
1153
1154 u8 div;
1155
1156 /* wait for diseqc idle */
1157 if (stb0899_wait_diseqc_txidle(state, 100) < 0)
1158 return -ETIMEDOUT;
1159
1160 switch (tone) {
1161 case SEC_TONE_ON:
1162 div = (internal->master_clk / 100) / 5632;
1163 div = (div + 5) / 10;
1164 stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x66);
1165 stb0899_write_reg(state, STB0899_ACRPRESC, 0x31);
1166 stb0899_write_reg(state, STB0899_ACRDIV1, div);
1167 break;
1168 case SEC_TONE_OFF:
1169 stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x20);
1170 break;
1171 default:
1172 break;
1173 }
1174 return 0;
1175}
1176
1177static int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
1178{
1179 int i2c_stat;
1180 struct stb0899_state *state = fe->demodulator_priv;
1181
1182 i2c_stat = stb0899_read_reg(state, STB0899_I2CRPT);
1183 if (i2c_stat < 0)
1184 goto err;
1185
1186 if (enable) {
1187 dprintk(state->verbose, FE_DEBUG, 1, "Enabling I2C Repeater ...");
1188 i2c_stat |= STB0899_I2CTON;
1189 if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
1190 goto err;
1191 }
1192 return 0;
1193err:
1194 dprintk(state->verbose, FE_ERROR, 1, "I2C Repeater enable failed");
1195 return -EREMOTEIO;
1196}
1197
1198
1199static inline void CONVERT32(u32 x, char *str)
1200{
1201 *str++ = (x >> 24) & 0xff;
1202 *str++ = (x >> 16) & 0xff;
1203 *str++ = (x >> 8) & 0xff;
1204 *str++ = (x >> 0) & 0xff;
1205 *str = '\0';
1206}
1207
1208int stb0899_get_dev_id(struct stb0899_state *state)
1209{
1210 u8 chip_id, release;
1211 u16 id;
1212 u32 demod_ver = 0, fec_ver = 0;
1213 char demod_str[4] = { 0 };
1214 char fec_str[4] = { 0 };
1215
1216 id = stb0899_read_reg(state, STB0899_DEV_ID);
1217 dprintk(state->verbose, FE_DEBUG, 1, "ID reg=[0x%02x]", id);
1218 chip_id = STB0899_GETFIELD(CHIP_ID, id);
1219 release = STB0899_GETFIELD(CHIP_REL, id);
1220
1221 dprintk(state->verbose, FE_ERROR, 1, "Device ID=[%d], Release=[%d]",
1222 chip_id, release);
1223
1224 CONVERT32(STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CORE_ID), (char *)&demod_str);
1225
1226 demod_ver = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_VERSION_ID);
1227 dprintk(state->verbose, FE_ERROR, 1, "Demodulator Core ID=[%s], Version=[%d]", (char *) &demod_str, demod_ver);
1228 CONVERT32(STB0899_READ_S2REG(STB0899_S2FEC, FEC_CORE_ID_REG), (char *)&fec_str);
1229 fec_ver = STB0899_READ_S2REG(STB0899_S2FEC, FEC_VER_ID_REG);
1230 if (! (chip_id > 0)) {
1231 dprintk(state->verbose, FE_ERROR, 1, "couldn't find a STB 0899");
1232
1233 return -ENODEV;
1234 }
1235 dprintk(state->verbose, FE_ERROR, 1, "FEC Core ID=[%s], Version=[%d]", (char*) &fec_str, fec_ver);
1236
1237 return 0;
1238}
1239
1240static const struct dvbfe_info dvbs_info = {
1241 .name = "STB0899 DVB-S",
1242 .delivery = DVBFE_DELSYS_DVBS,
1243 .delsys = {
1244 .dvbs.modulation = DVBFE_MOD_QPSK,
1245 .dvbs.fec = DVBFE_FEC_1_2 | DVBFE_FEC_2_3 |
1246 DVBFE_FEC_3_4 | DVBFE_FEC_5_6 |
1247 DVBFE_FEC_6_7
1248 },
1249
1250 .frequency_min = 950000,
1251 .frequency_max = 2150000,
1252 .frequency_step = 0,
1253 .symbol_rate_min = 1000000,
1254 .symbol_rate_max = 45000000,
1255 .symbol_rate_tolerance = 0
1256};
1257
1258static const struct dvbfe_info dss_info = {
1259 .name = "STB0899 DSS",
1260 .delivery = DVBFE_DELSYS_DSS,
1261 .delsys = {
1262 .dss.modulation = DVBFE_MOD_BPSK | DVBFE_MOD_QPSK,
1263 .dss.fec = DVBFE_FEC_1_2 | DVBFE_FEC_2_3 |
1264 DVBFE_FEC_3_4 | DVBFE_FEC_5_6 |
1265 DVBFE_FEC_6_7
1266 },
1267
1268 .frequency_min = 950000,
1269 .frequency_max = 2150000,
1270 .frequency_step = 0,
1271 .symbol_rate_min = 1000000,
1272 .symbol_rate_max = 45000000,
1273 .symbol_rate_tolerance = 0
1274};
1275
1276static const struct dvbfe_info dvbs2_info = {
1277 .name = "STB0899 DVB-S2",
1278 .delivery = DVBFE_DELSYS_DVBS2,
1279 .delsys = {
1280 .dvbs2.modulation = DVBFE_MOD_QPSK | DVBFE_MOD_8PSK |
1281 DVBFE_MOD_16APSK | DVBFE_MOD_32APSK,
1282
1283 .dvbs2.fec = DVBFE_FEC_1_4 | DVBFE_FEC_1_3 |
1284 DVBFE_FEC_2_5 | DVBFE_FEC_1_2 |
1285 DVBFE_FEC_3_5 | DVBFE_FEC_2_3 |
1286 DVBFE_FEC_3_4 | DVBFE_FEC_4_5 |
1287 DVBFE_FEC_5_6 | DVBFE_FEC_8_9 |
1288 DVBFE_FEC_9_10,
1289 },
1290
1291 .frequency_min = 950000,
1292 .frequency_max = 2150000,
1293 .frequency_step = 0,
1294 .symbol_rate_min = 1000000,
1295 .symbol_rate_max = 45000000,
1296 .symbol_rate_tolerance = 0
1297};
1298
1299static int stb0899_get_info(struct dvb_frontend *fe, struct dvbfe_info *fe_info)
1300{
1301 struct stb0899_state *state = fe->demodulator_priv;
1302
1303 dprintk(verbose, FE_DEBUG, 1, "Get Info");
1304
1305 state->delsys = fe_info->delivery;
1306 switch (state->delsys) {
1307 case DVBFE_DELSYS_DVBS:
1308 dprintk(verbose, FE_ERROR, 1, "Querying DVB-S info");
1309 memcpy(fe_info, &dvbs_info, sizeof (struct dvbfe_info));
1310 break;
1311 case DVBFE_DELSYS_DSS:
1312 dprintk(verbose, FE_ERROR, 1, "Querying DSS info");
1313 memcpy(fe_info, &dss_info, sizeof (struct dvbfe_info));
1314 break;
1315 case DVBFE_DELSYS_DVBS2:
1316 dprintk(verbose, FE_ERROR, 1, "Querying DVB-S2 info");
1317 memcpy(fe_info, &dvbs2_info, sizeof (struct dvbfe_info));
1318 break;
1319 default:
1320 dprintk(verbose, FE_ERROR, 1, "Unsupported delivery system");
1321 return -EINVAL;
1322 }
1323 dprintk(verbose, FE_DEBUG, 1, "delivery system=%d", state->delsys);
1324
1325 return 0;
1326}
1327
1328static int stb0899_get_delsys(struct dvb_frontend *fe, enum dvbfe_delsys *fe_delsys)
1329{
1330 *fe_delsys = DVBFE_DELSYS_DVBS | DVBFE_DELSYS_DSS | DVBFE_DELSYS_DVBS2;
1331
1332 return 0;
1333}
1334
1335void stb0899_set_delsys(struct stb0899_state *state)
1336{
1337 u8 reg;
1338 u8 stop_clk[2];
1339
1340 stop_clk[0] = stb0899_read_reg(state, STB0899_STOPCLK1);
1341 stop_clk[1] = stb0899_read_reg(state, STB0899_STOPCLK2);
1342
1343 switch (state->delsys) {
1344 case DVBFE_DELSYS_DVBS:
1345 dprintk(verbose, FE_DEBUG, 1, "Delivery System -- DVB-S");
1346 /* FECM/Viterbi ON */
1347 reg = stb0899_read_reg(state, STB0899_FECM);
1348 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0);
1349 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1);
1350 stb0899_write_reg(state, STB0899_FECM, reg);
1351
1352 stb0899_write_reg(state, STB0899_RSULC, 0xb1);
1353 stb0899_write_reg(state, STB0899_TSULC, 0x40);
1354 stb0899_write_reg(state, STB0899_RSLLC, 0x42);
1355 stb0899_write_reg(state, STB0899_TSLPL, 0x12);
1356
1357 reg = stb0899_read_reg(state, STB0899_TSTRES);
1358 STB0899_SETFIELD_VAL(FRESLDPC, reg, 1);
1359 stb0899_write_reg(state, STB0899_TSTRES, reg);
1360
1361 STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1362 STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 1);
1363 STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 1);
1364
1365 STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 1);
1366 STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 1);
1367
1368 STB0899_SETFIELD_VAL(STOP_CKINTBUF216, stop_clk[0], 1);
1369 STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 1);
1370
1371 STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 1);
1372 break;
1373 case DVBFE_DELSYS_DVBS2:
1374 /* FECM/Viterbi OFF */
1375 reg = stb0899_read_reg(state, STB0899_FECM);
1376 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0);
1377 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 0);
1378 stb0899_write_reg(state, STB0899_FECM, reg);
1379
1380 stb0899_write_reg(state, STB0899_RSULC, 0xb1);
1381 stb0899_write_reg(state, STB0899_TSULC, 0x42);
1382 stb0899_write_reg(state, STB0899_RSLLC, 0x40);
1383 stb0899_write_reg(state, STB0899_TSLPL, 0x02);
1384
1385 reg = stb0899_read_reg(state, STB0899_TSTRES);
1386 STB0899_SETFIELD_VAL(FRESLDPC, reg, 0);
1387 stb0899_write_reg(state, STB0899_TSTRES, reg);
1388
1389 STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1390 STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 0);
1391 STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 0);
1392
1393 STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 0);
1394 STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 0);
1395
1396 STB0899_SETFIELD_VAL(STOP_CKINTBUF216, stop_clk[0], 0);
1397 STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
1398
1399 STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 0);
1400 break;
1401 case DVBFE_DELSYS_DSS:
1402 /* FECM/Viterbi ON */
1403 reg = stb0899_read_reg(state, STB0899_FECM);
1404 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 1);
1405 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1);
1406 stb0899_write_reg(state, STB0899_FECM, reg);
1407
1408 stb0899_write_reg(state, STB0899_RSULC, 0xa1);
1409 stb0899_write_reg(state, STB0899_TSULC, 0x61);
1410 stb0899_write_reg(state, STB0899_RSLLC, 0x42);
1411
1412 reg = stb0899_read_reg(state, STB0899_TSTRES);
1413 STB0899_SETFIELD_VAL(FRESLDPC, reg, 1);
1414 stb0899_write_reg(state, STB0899_TSTRES, reg);
1415
1416 STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1417 STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 1);
1418 STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 1);
1419
1420 STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 1);
1421 STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 1);
1422
1423 STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
1424
1425 STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 1);
1426 break;
1427 default:
1428 dprintk(verbose, FE_ERROR, 1, "Unsupported delivery system");
1429 break;
1430 }
1431 STB0899_SETFIELD_VAL(STOP_CKADCI108, stop_clk[0], 0);
1432 stb0899_write_regs(state, STB0899_STOPCLK1, stop_clk, 2);
1433}
1434
1435/*
1436 * stb0899_set_iterations
1437 * set the LDPC iteration scale function
1438 */
1439static void stb0899_set_iterations(struct stb0899_state *state)
1440{
1441 struct stb0899_internal *internal = &state->internal;
1442 struct stb0899_config *config = state->config;
1443
1444 s32 iter_scale;
1445 u32 reg;
1446
1447 iter_scale = 17 * (internal->master_clk / 1000);
1448 iter_scale += 410000;
1449 iter_scale /= (internal->srate / 1000000);
1450 iter_scale /= 1000;
1451
1452 if (iter_scale > config->ldpc_max_iter)
1453 iter_scale = config->ldpc_max_iter;
1454
1455 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, MAX_ITER);
1456 STB0899_SETFIELD_VAL(MAX_ITERATIONS, reg, iter_scale);
1457 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg);
1458}
1459
1460static enum dvbfe_search stb0899_search(struct dvb_frontend *fe, struct dvbfe_params *params)
1461{
1462 struct stb0899_state *state = fe->demodulator_priv;
1463 struct stb0899_params *i_params = &state->params;
1464 struct stb0899_internal *internal = &state->internal;
1465
1466 u32 SearchRange, gain;
1467
1468 switch (state->delsys) {
1469 case DVBFE_DELSYS_DVBS:
1470 dprintk(verbose, FE_ERROR, 1, "set DVB-S params");
1471 i_params->freq = params->frequency;
1472 i_params->srate = params->delsys.dvbs.symbol_rate;
1473 break;
1474 case DVBFE_DELSYS_DSS:
1475 dprintk(verbose, FE_ERROR, 1, "set DSS params");
1476 i_params->freq = params->frequency;
1477 i_params->srate = params->delsys.dss.symbol_rate;
1478 break;
1479 case DVBFE_DELSYS_DVBS2:
1480 dprintk(verbose, FE_ERROR, 1, "set DVB-S2 params");
1481 i_params->freq = params->frequency;
1482 i_params->srate = params->delsys.dvbs2.symbol_rate;
1483 break;
1484 default:
1485 dprintk(verbose, FE_ERROR, 1, "Unsupported delivery system");
1486 return -EINVAL;
1487 }
1488 dprintk(verbose, FE_DEBUG, 1, "delivery system=%d", state->delsys);
1489
1490// SearchRange = 3000000; /* Search Bandwidth (3 Mhz, was initially 10 Mhz) */
1491 SearchRange = 10000000; /* Search Bandwidth (3 Mhz, was initially 10 Mhz) */
1492 dprintk(verbose, FE_DEBUG, 1, "Frequency=%d, Srate=%d", i_params->freq, i_params->srate);
1493 /* checking Search Range is meaningless for a fixed 3 Mhz */
1494 if (INRANGE(i_params->srate, 1000000, 45000000)) {
1495 dprintk(verbose, FE_DEBUG, 1, "Parameters IN RANGE");
1496 stb0899_set_delsys(state);
1497
1498 if (state->config->tuner_set_rfsiggain) {
1499 if (internal->srate > 15000000)
1500 gain = 8; /* 15Mb < srate < 45Mb, gain = 8dB */
1501 else if (internal->srate > 5000000)
1502 gain = 12; /* 5Mb < srate < 15Mb, gain = 12dB */
1503 else
1504 gain = 14; /* 1Mb < srate < 5Mb, gain = 14db */
1505 state->config->tuner_set_rfsiggain(fe, gain);
1506 }
1507
1508 if (i_params->srate <= 5000000)
1509 stb0899_set_mclk(state, 76500000);
1510 else
1511 stb0899_set_mclk(state, 99000000);
1512
1513 switch (state->delsys) {
1514 case DVBFE_DELSYS_DVBS:
1515 case DVBFE_DELSYS_DSS:
1516 dprintk(verbose, FE_DEBUG, 1, "DVB-S delivery system");
1517 internal->freq = i_params->freq;
1518 internal->srate = i_params->srate;
1519 /*
1520 * search = user search range +
1521 * 500Khz +
1522 * 2 * Tuner_step_size +
1523 * 10% of the symbol rate
1524 */
1525 internal->srch_range = SearchRange + 1500000 + (i_params->srate / 5);
1526 internal->derot_percent = 30;
1527
1528 /* What to do for tuners having no bandwidth setup ? */
1529 if (state->config->tuner_set_bandwidth)
1530 state->config->tuner_set_bandwidth(fe, (13 * (stb0899_carr_width(state) + 10000000)) / 10);
1531 if (state->config->tuner_get_bandwidth)
1532 state->config->tuner_get_bandwidth(fe, &internal->tuner_bw);
1533 /* Set DVB-S1 AGC */
1534 stb0899_write_reg(state, STB0899_AGCRFCFG, 0x11);
1535
1536 /* Run the search algorithm */
1537 dprintk(verbose, FE_DEBUG, 1, "running DVB-S search algo ..");
1538 if (stb0899_dvbs_algo(state) == RANGEOK) {
1539 internal->lock = 1;
1540 dprintk(verbose, FE_DEBUG, 1,
1541 "-------------------------------------> DVB-S LOCK !");
1542
1543// stb0899_write_reg(state, STB0899_ERRCTRL1, 0x3d); /* Viterbi Errors */
1544// internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS);
1545// internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1);
1546// dprintk(verbose, FE_DEBUG, 1, "VSTATUS=0x%02x", internal->v_status);
1547// dprintk(verbose, FE_DEBUG, 1, "ERR_CTRL=0x%02x", internal->err_ctrl);
1548
1549 return DVBFE_ALGO_SEARCH_SUCCESS;
1550 } else {
1551 internal->lock = 0;
1552
1553 return DVBFE_ALGO_SEARCH_FAILED;
1554 }
1555 break;
1556 case DVBFE_DELSYS_DVBS2:
1557 internal->freq = i_params->freq;
1558 internal->srate = i_params->srate;
1559 internal->srch_range = SearchRange;
1560
1561 if (state->config->tuner_set_bandwidth)
1562 state->config->tuner_set_bandwidth(fe, (stb0899_carr_width(state) + 10000000));
1563 if (state->config->tuner_get_bandwidth)
1564 state->config->tuner_get_bandwidth(fe, &internal->tuner_bw);
1565
1566// pParams->SpectralInv = pSearch->IQ_Inversion;
1567
1568 /* Set DVB-S2 AGC */
1569 stb0899_write_reg(state, STB0899_AGCRFCFG, 0x1c);
1570
1571 /* Set IterScale =f(MCLK,SYMB) */
1572 stb0899_set_iterations(state);
1573
1574 /* Run the search algorithm */
1575 dprintk(verbose, FE_DEBUG, 1, "running DVB-S2 search algo ..");
1576 if (stb0899_dvbs2_algo(state) == DVBS2_FEC_LOCK) {
1577 internal->lock = 1;
1578 dprintk(verbose, FE_DEBUG, 1,
1579 "-------------------------------------> DVB-S2 LOCK !");
1580
1581// stb0899_write_reg(state, STB0899_ERRCTRL1, 0xb6); /* Packet Errors */
1582// internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS);
1583// internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1);
1584
1585 return DVBFE_ALGO_SEARCH_SUCCESS;
1586 } else {
1587 internal->lock = 0;
1588
1589 return DVBFE_ALGO_SEARCH_FAILED;
1590 }
1591 break;
1592 default:
1593 dprintk(verbose, FE_ERROR, 1, "Unsupported delivery system");
1594 return DVBFE_ALGO_SEARCH_INVALID;
1595 }
1596 }
1597
1598 return DVBFE_ALGO_SEARCH_ERROR;
1599}
1600
1601static enum stb0899_status stb0899_track_carrier(struct stb0899_state *state)
1602{
1603 u8 reg;
1604
1605 reg = stb0899_read_reg(state, STB0899_DSTATUS);
1606 dprintk(verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
1607 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
1608 dprintk(verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
1609 return CARRIEROK;
1610 } else {
1611 dprintk(verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
1612 return NOCARRIER;
1613 }
1614
1615 return NOCARRIER;
1616}
1617
1618static enum stb0899_status stb0899_get_ifagc(struct stb0899_state *state)
1619{
1620 u8 reg;
1621
1622 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1623 dprintk(verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1624 if (STB0899_GETFIELD(IF_AGC_LOCK, reg)) {
1625 dprintk(verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1626 return AGC1OK;
1627 } else {
1628 dprintk(verbose, FE_DEBUG, 1, "------------->IF AGC LOCK LOST !");
1629 return NOAGC1;
1630 }
1631
1632 return NOAGC1;
1633}
1634
1635static int stb0899_get_s1fec(struct stb0899_internal *internal, enum dvbfe_fec *fec)
1636{
1637 switch (internal->fecrate) {
1638 case STB0899_FEC_1_2:
1639 *fec = DVBFE_FEC_1_2;
1640 break;
1641 case STB0899_FEC_2_3:
1642 *fec = DVBFE_FEC_2_3;
1643 break;
1644 case STB0899_FEC_3_4:
1645 *fec = DVBFE_FEC_3_4;
1646 break;
1647 case STB0899_FEC_5_6:
1648 *fec = DVBFE_FEC_5_6;
1649 break;
1650 case STB0899_FEC_6_7:
1651 *fec = DVBFE_FEC_6_7;
1652 break;
1653 case STB0899_FEC_7_8:
1654 *fec = DVBFE_FEC_7_8;
1655 break;
1656 default:
1657 return -EINVAL;
1658 }
1659
1660 return 0;
1661}
1662
1663static int stb0899_get_modcod(struct stb0899_internal *internal, struct dvbs2_params *params)
1664{
1665 switch (internal->modcod) {
1666 case STB0899_DUMMY_PLF:
1667 params->modulation = DVBFE_MOD_NONE;
1668 params->fec = DVBFE_FEC_NONE;
1669 break;
1670 case STB0899_QPSK_14:
1671 params->modulation = DVBFE_MOD_QPSK;
1672 params->fec = DVBFE_FEC_1_4;
1673 break;
1674 case STB0899_QPSK_13:
1675 params->modulation = DVBFE_MOD_QPSK;
1676 params->fec = DVBFE_FEC_1_3;
1677 break;
1678 case STB0899_QPSK_25:
1679 params->modulation = DVBFE_MOD_QPSK;
1680 params->fec = DVBFE_FEC_2_5;
1681 break;
1682 case STB0899_QPSK_12:
1683 params->modulation = DVBFE_MOD_QPSK;
1684 params->fec = DVBFE_FEC_1_2;
1685 break;
1686 case STB0899_QPSK_35:
1687 params->modulation = DVBFE_MOD_QPSK;
1688 params->fec = DVBFE_FEC_3_5;
1689 break;
1690 case STB0899_QPSK_23:
1691 params->modulation = DVBFE_MOD_QPSK;
1692 params->fec = DVBFE_FEC_2_3;
1693 break;
1694 case STB0899_QPSK_34:
1695 params->modulation = DVBFE_MOD_QPSK;
1696 params->fec = DVBFE_FEC_3_4;
1697 break;
1698 case STB0899_QPSK_45:
1699 params->modulation = DVBFE_MOD_QPSK;
1700 params->fec = DVBFE_FEC_4_5;
1701 break;
1702 case STB0899_QPSK_56:
1703 params->modulation = DVBFE_MOD_QPSK;
1704 params->fec = DVBFE_FEC_5_6;
1705 break;
1706 case STB0899_QPSK_89:
1707 params->modulation = DVBFE_MOD_QPSK;
1708 params->fec = DVBFE_FEC_8_9;
1709 break;
1710 case STB0899_QPSK_910:
1711 params->modulation = DVBFE_MOD_QPSK;
1712 params->fec = DVBFE_FEC_9_10;
1713 break;
1714 case STB0899_8PSK_35:
1715 params->modulation = DVBFE_MOD_8PSK;
1716 params->fec = DVBFE_FEC_3_5;
1717 break;
1718 case STB0899_8PSK_23:
1719 params->modulation = DVBFE_MOD_8PSK;
1720 params->fec = DVBFE_FEC_2_3;
1721 break;
1722 case STB0899_8PSK_34:
1723 params->modulation = DVBFE_MOD_8PSK;
1724 params->fec = DVBFE_FEC_3_4;
1725 break;
1726 case STB0899_8PSK_56:
1727 params->modulation = DVBFE_MOD_8PSK;
1728 params->fec = DVBFE_FEC_5_6;
1729 break;
1730 case STB0899_8PSK_89:
1731 params->modulation = DVBFE_MOD_8PSK;
1732 params->fec = DVBFE_FEC_8_9;
1733 break;
1734 case STB0899_8PSK_910:
1735 params->modulation = DVBFE_MOD_8PSK;
1736 params->fec = DVBFE_FEC_9_10;
1737 break;
1738 case STB0899_16APSK_23:
1739 params->modulation = DVBFE_MOD_16APSK;
1740 params->fec = DVBFE_FEC_2_3;
1741 break;
1742 case STB0899_16APSK_34:
1743 params->modulation = DVBFE_MOD_16APSK;
1744 params->fec = DVBFE_FEC_3_4;
1745 break;
1746 case STB0899_16APSK_45:
1747 params->modulation = DVBFE_MOD_16APSK;
1748 params->fec = DVBFE_FEC_4_5;
1749 break;
1750 case STB0899_16APSK_56:
1751 params->modulation = DVBFE_MOD_16APSK;
1752 params->fec = DVBFE_FEC_5_6;
1753 break;
1754 case STB0899_16APSK_89:
1755 params->modulation = DVBFE_MOD_16APSK;
1756 params->fec = DVBFE_FEC_8_9;
1757 break;
1758 case STB0899_16APSK_910:
1759 params->modulation = DVBFE_MOD_16APSK;
1760 params->fec = DVBFE_FEC_9_10;
1761 break;
1762 case STB0899_32APSK_34:
1763 params->modulation = DVBFE_MOD_32APSK;
1764 params->fec = DVBFE_FEC_3_4;
1765 break;
1766 case STB0899_32APSK_45:
1767 params->modulation = DVBFE_MOD_32APSK;
1768 params->fec = DVBFE_FEC_4_5;
1769 break;
1770 case STB0899_32APSK_56:
1771 params->modulation = DVBFE_MOD_32APSK;
1772 params->fec = DVBFE_FEC_5_6;
1773 break;
1774 case STB0899_32APSK_89:
1775 params->modulation = DVBFE_MOD_32APSK;
1776 params->fec = DVBFE_FEC_8_9;
1777 break;
1778 case STB0899_32APSK_910:
1779 params->modulation = DVBFE_MOD_32APSK;
1780 params->fec = DVBFE_FEC_9_10;
1781 break;
1782 default:
1783 return -EINVAL;
1784 }
1785
1786 return 0;
1787}
1788
1789/*
1790 * stb0899_track
1791 * periodically check the signal level against a specified
1792 * threshold level and perform derotator centering.
1793 * called once we have a lock from a succesful search
1794 * event.
1795 *
1796 * Will be called periodically called to maintain the
1797 * lock.
1798 *
1799 * Will be used to get parameters as well as info from
1800 * the decoded baseband header
1801 *
1802 * Once a new lock has established, the internal state
1803 * frequency (internal->freq) is updated
1804 */
1805static int stb0899_track(struct dvb_frontend *fe, struct dvbfe_params *params)
1806{
1807 struct stb0899_state *state = fe->demodulator_priv;
1808 struct stb0899_internal *internal = &state->internal;
1809
1810 switch (state->delsys) {
1811 case DVBFE_DELSYS_DVBS:
1812 dprintk(verbose, FE_DEBUG, 1, "Tracking DVB-S state");
1813 if (stb0899_track_carrier(state) == CARRIEROK) {
1814 params->frequency = internal->freq;
1815 params->inversion = internal->inversion;
1816 params->delivery = state->delsys;
1817 params->delsys.dvbs.symbol_rate = internal->srate;
1818 params->delsys.dvbs.modulation = DVBFE_MOD_QPSK;
1819 stb0899_get_s1fec(internal, &params->delsys.dvbs.fec);
1820 }
1821 break;
1822 case DVBFE_DELSYS_DSS:
1823 dprintk(verbose, FE_DEBUG, 1, "Tracking DSS state");
1824 if (stb0899_track_carrier(state) == CARRIEROK) {
1825 params->frequency = internal->freq;
1826 params->inversion = internal->inversion;
1827 params->delivery = state->delsys;
1828 params->delsys.dss.symbol_rate = internal->srate;
1829 params->delsys.dss.modulation = DVBFE_MOD_QPSK;
1830 stb0899_get_s1fec(internal, &params->delsys.dss.fec);
1831 }
1832 break;
1833 case DVBFE_DELSYS_DVBS2:
1834 dprintk(verbose, FE_DEBUG, 1, "Tracking DVB-S2 state");
1835 if (stb0899_get_ifagc(state) == AGC1OK) {
1836 params->frequency = internal->freq;
1837 params->inversion = internal->inversion;
1838 params->delivery = state->delsys;
1839 params->delsys.dvbs2.symbol_rate = internal->srate;
1840 stb0899_get_modcod(internal, &params->delsys.dvbs2);
1841 params->delsys.dvbs2.rolloff = internal->rolloff;
1842 params->delsys.dvbs2.matype_1 = stb0899_read_reg(state, STB0899_MATSTRL);
1843 params->delsys.dvbs2.matype_2 = stb0899_read_reg(state, STB0899_MATSTRM);
1844 params->delsys.dvbs2.upl_1 = stb0899_read_reg(state, STB0899_UPLSTRL);
1845 params->delsys.dvbs2.upl_2 = stb0899_read_reg(state, STB0899_UPLSTRM);
1846 params->delsys.dvbs2.dfl_1 = stb0899_read_reg(state, STB0899_DFLSTRL);
1847 params->delsys.dvbs2.dfl_2 = stb0899_read_reg(state, STB0899_DFLSTRM);
1848 params->delsys.dvbs2.sync = stb0899_read_reg(state, STB0899_SYNCSTR);
1849 params->delsys.dvbs2.syncd_1 = stb0899_read_reg(state, STB0899_SYNCDSTRL);
1850 params->delsys.dvbs2.syncd_2 = stb0899_read_reg(state, STB0899_SYNCDSTRM);
1851 }
1852 break;
1853 default:
1854 dprintk(verbose, FE_ERROR, 1, "Unsupported delivery system");
1855 return -EINVAL;
1856 }
1857
1858 return 0;
1859}
1860
1861static int stb0899_get_params(struct dvb_frontend *fe, struct dvbfe_params *params)
1862{
1863 struct stb0899_state *state = fe->demodulator_priv;
1864 struct stb0899_internal *internal = &state->internal;
1865
1866 params->frequency = internal->freq;
1867 params->inversion = internal->inversion;
1868 params->delivery = state->delsys;
1869 switch (state->delsys) {
1870 case DVBFE_DELSYS_DVBS:
1871 dprintk(verbose, FE_DEBUG, 1, "Get DVB-S params");
1872 params->delsys.dvbs.symbol_rate = internal->srate;
1873 params->delsys.dvbs.modulation = DVBFE_MOD_QPSK;
1874 break;
1875 case DVBFE_DELSYS_DSS:
1876 dprintk(verbose, FE_DEBUG, 1, "Get DSS params");
1877 params->delsys.dss.symbol_rate = internal->srate;
1878 params->delsys.dss.modulation = DVBFE_MOD_QPSK;
1879
1880 break;
1881 case DVBFE_DELSYS_DVBS2:
1882 dprintk(verbose, FE_DEBUG, 1, "Get DVB-S2 params");
1883 params->delsys.dvbs2.symbol_rate = internal->srate;
1884 break;
1885 default:
1886 dprintk(verbose, FE_ERROR, 1, "Unsupported delivery system");
1887 return -EINVAL;
1888 }
1889
1890 return 0;
1891}
1892
1893static enum dvbfe_algo stb0899_frontend_algo(struct dvb_frontend *fe)
1894{
1895 return DVBFE_ALGO_CUSTOM;
1896}
1897
1898static struct dvb_frontend_ops stb0899_ops = {
1899
1900 .info = {
1901 .name = "STB0899 Multistandard",
1902 },
1903
1904 .release = stb0899_release,
1905 .init = stb0899_init,
1906 .sleep = stb0899_sleep,
1907// .wakeup = stb0899_wakeup,
1908
1909 .i2c_gate_ctrl = stb0899_i2c_gate_ctrl,
1910 .get_info = stb0899_get_info,
1911 .get_delsys = stb0899_get_delsys,
1912
1913 .get_frontend_algo = stb0899_frontend_algo,
1914 .search = stb0899_search,
1915 .track = stb0899_track,
1916 .get_params = stb0899_get_params,
1917
1918 .read_status = stb0899_read_status,
1919 .read_snr = stb0899_read_snr,
1920 .read_signal_strength = stb0899_read_signal_strength,
1921 .read_status = stb0899_read_status,
1922 .read_ber = stb0899_read_ber,
1923
1924 .set_voltage = stb0899_set_voltage,
1925 .set_tone = stb0899_set_tone,
1926
1927 .diseqc_send_master_cmd = stb0899_send_diseqc_msg,
1928 .diseqc_recv_slave_reply = stb0899_recv_slave_reply,
1929 .diseqc_send_burst = stb0899_send_diseqc_burst,
1930};
1931
1932struct dvb_frontend *stb0899_attach(struct stb0899_config *config, struct i2c_adapter *i2c)
1933{
1934 struct stb0899_state *state = NULL;
1935
1936 state = kzalloc(sizeof (struct stb0899_state), GFP_KERNEL);
1937 if (state == NULL)
1938 goto error;
1939
1940 state->verbose = verbose;
1941 state->config = config;
1942 state->i2c = i2c;
1943 state->frontend.ops = stb0899_ops;
1944 state->frontend.demodulator_priv = state;
1945
1946 stb0899_wakeup(&state->frontend);
1947 if (stb0899_get_dev_id(state) == -ENODEV) {
1948 printk("%s: Exiting .. !\n", __func__);
1949 goto error;
1950 }
1951
1952 printk("%s: Attaching STB0899 \n", __func__);
1953 return &state->frontend;
1954
1955error:
1956 kfree(state);
1957 return NULL;
1958}
1959EXPORT_SYMBOL(stb0899_attach);
1960MODULE_PARM_DESC(verbose, "Set Verbosity level");
1961MODULE_AUTHOR("Manu Abraham");
1962MODULE_DESCRIPTION("STB0899 Multi-Std frontend");
1963MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stb0899_drv.h b/drivers/media/dvb/frontends/stb0899_drv.h
new file mode 100644
index 00000000000..52c2ce17f85
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_drv.h
@@ -0,0 +1,94 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STB0899_DRV_H
23#define __STB0899_DRV_H
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27
28#include "dvb_frontend.h"
29
30#define STB0899_TSMODE_SERIAL 1
31#define STB0899_CLKPOL_FALLING 2
32#define STB0899_CLKNULL_PARITY 3
33#define STB0899_SYNC_FORCED 4
34#define STB0899_FECMODE_DSS 5
35
36struct stb0899_s1_reg {
37 u16 address;
38 u8 data;
39};
40
41struct stb0899_s2_reg {
42 u16 offset;
43 u32 base_address;
44 u32 data;
45};
46
47struct stb0899_config {
48 const struct stb0899_s1_reg *init_dev;
49 const struct stb0899_s2_reg *init_s2_demod;
50 const struct stb0899_s1_reg *init_s1_demod;
51 const struct stb0899_s2_reg *init_s2_fec;
52 const struct stb0899_s1_reg *init_tst;
53
54 u32 xtal_freq;
55
56 u8 demod_address;
57 u8 ts_output_mode;
58 u8 block_sync_mode;
59 u8 ts_pfbit_toggle;
60
61 u8 clock_polarity;
62 u8 data_clk_parity;
63 u8 fec_mode;
64 u8 data_output_ctl;
65 u8 data_fifo_mode;
66 u8 out_rate_comp;
67 u8 i2c_repeater;
68 int inversion;
69
70 u32 esno_ave;
71 u32 esno_quant;
72 u32 avframes_coarse;
73 u32 avframes_fine;
74 u32 miss_threshold;
75 u32 uwp_threshold_acq;
76 u32 uwp_threshold_track;
77 u32 uwp_threshold_sof;
78 u32 sof_search_timeout;
79
80 u32 btr_nco_bits;
81 u32 btr_gain_shift_offset;
82 u32 crl_nco_bits;
83 u32 ldpc_max_iter;
84
85 int (*tuner_set_frequency)(struct dvb_frontend *fe, u32 frequency);
86 int (*tuner_get_frequency)(struct dvb_frontend *fe, u32 *frequency);
87 int (*tuner_set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth);
88 int (*tuner_get_bandwidth)(struct dvb_frontend *fe, u32 *bandwidth);
89 int (*tuner_set_rfsiggain)(struct dvb_frontend *fe, u32 rf_gain);
90};
91
92extern struct dvb_frontend *stb0899_attach(struct stb0899_config *config, struct i2c_adapter *i2c);
93
94#endif
diff --git a/drivers/media/dvb/frontends/stb0899_priv.h b/drivers/media/dvb/frontends/stb0899_priv.h
new file mode 100644
index 00000000000..47e533dd417
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_priv.h
@@ -0,0 +1,272 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STB0899_PRIV_H
23#define __STB0899_PRIV_H
24
25#include "dvb_frontend.h"
26#include "stb0899_drv.h"
27
28#define FE_ERROR 0
29#define FE_NOTICE 1
30#define FE_INFO 2
31#define FE_DEBUG 3
32#define FE_DEBUGREG 4
33
34#define dprintk(x, y, z, format, arg...) do { \
35 if (z) { \
36 if ((x > FE_ERROR) && (x > y)) \
37 printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
38 else if ((x > FE_NOTICE) && (x > y)) \
39 printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
40 else if ((x > FE_INFO) && (x > y)) \
41 printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
42 else if ((x > FE_DEBUG) && (x > y)) \
43 printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
44 } else { \
45 if (x > y) \
46 printk(format, ##arg); \
47 } \
48} while(0)
49
50#define INRANGE(val, x, y) (((x <= val) && (val <= y)) || \
51 ((y <= val) && (val <= x)) ? 1 : 0)
52
53#define BYTE0 0
54#define BYTE1 8
55#define BYTE2 16
56#define BYTE3 24
57
58#define GETBYTE(x, y) (((x) >> (y)) & 0xff)
59#define MAKEWORD32(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
60#define MAKEWORD16(a, b) (((a) << 8) | (b))
61
62#define MIN(x, y) ((x) <= (y) ? (x) : (y))
63#define MAX(x, y) ((x) >= (y) ? (x) : (y))
64#define ABS(x) ((x) >= 0 ? (x) : -(x))
65
66#define LSB(x) ((x & 0xff))
67#define MSB(y) ((y >> 8) & 0xff)
68
69
70#define STB0899_GETFIELD(bitf, val) ((val >> STB0899_OFFST_##bitf) & ((1 << STB0899_WIDTH_##bitf) - 1))
71
72
73#define STB0899_SETFIELD(mask, val, width, offset) (mask & (~(((1 << width) - 1) << \
74 offset))) | ((val & \
75 ((1 << width) - 1)) << offset)
76
77#define STB0899_SETFIELD_VAL(bitf, mask, val) (mask = (mask & (~(((1 << STB0899_WIDTH_##bitf) - 1) <<\
78 STB0899_OFFST_##bitf))) | \
79 (val << STB0899_OFFST_##bitf))
80
81
82enum stb0899_status {
83 NOAGC1 = 0,
84 AGC1OK,
85 NOTIMING,
86 ANALOGCARRIER,
87 TIMINGOK,
88 NOAGC2,
89 AGC2OK,
90 NOCARRIER,
91 CARRIEROK,
92 NODATA,
93 FALSELOCK,
94 DATAOK,
95 OUTOFRANGE,
96 RANGEOK,
97 DVBS2_DEMOD_LOCK,
98 DVBS2_DEMOD_NOLOCK,
99 DVBS2_FEC_LOCK,
100 DVBS2_FEC_NOLOCK
101};
102
103enum stb0899_modcod {
104 STB0899_DUMMY_PLF,
105 STB0899_QPSK_14,
106 STB0899_QPSK_13,
107 STB0899_QPSK_25,
108 STB0899_QPSK_12,
109 STB0899_QPSK_35,
110 STB0899_QPSK_23,
111 STB0899_QPSK_34,
112 STB0899_QPSK_45,
113 STB0899_QPSK_56,
114 STB0899_QPSK_89,
115 STB0899_QPSK_910,
116 STB0899_8PSK_35,
117 STB0899_8PSK_23,
118 STB0899_8PSK_34,
119 STB0899_8PSK_56,
120 STB0899_8PSK_89,
121 STB0899_8PSK_910,
122 STB0899_16APSK_23,
123 STB0899_16APSK_34,
124 STB0899_16APSK_45,
125 STB0899_16APSK_56,
126 STB0899_16APSK_89,
127 STB0899_16APSK_910,
128 STB0899_32APSK_34,
129 STB0899_32APSK_45,
130 STB0899_32APSK_56,
131 STB0899_32APSK_89,
132 STB0899_32APSK_910
133};
134
135enum stb0899_frame {
136 STB0899_LONG_FRAME,
137 STB0899_SHORT_FRAME
138};
139
140enum stb0899_inversion {
141 IQ_SWAP_OFF = 0,
142 IQ_SWAP_ON,
143 IQ_SWAP_AUTO
144};
145
146enum stb0899_alpha {
147 RRC_20,
148 RRC_25,
149 RRC_35
150};
151
152struct stb0899_tab {
153 s32 real;
154 s32 read;
155};
156
157enum stb0899_fec {
158 STB0899_FEC_1_2 = 13,
159 STB0899_FEC_2_3 = 18,
160 STB0899_FEC_3_4 = 21,
161 STB0899_FEC_5_6 = 24,
162 STB0899_FEC_6_7 = 25,
163 STB0899_FEC_7_8 = 26
164};
165
166struct stb0899_params {
167 u32 freq; /* Frequency */
168 u32 srate; /* Symbol rate */
169 enum dvbfe_fec fecrate;
170};
171
172struct stb0899_internal {
173 u32 master_clk;
174 u32 freq; /* Demod internal Frequency */
175 u32 srate; /* Demod internal Symbol rate */
176 enum stb0899_fec fecrate; /* Demod internal FEC rate */
177 u32 srch_range; /* Demod internal Search Range */
178 u32 sub_range; /* Demod current sub range (Hz) */
179 u32 tuner_step; /* Tuner step (Hz) */
180 u32 tuner_offst; /* Relative offset to carrier (Hz) */
181 u32 tuner_bw; /* Current bandwidth of the tuner (Hz) */
182
183 s32 mclk; /* Masterclock Divider factor (binary) */
184 s32 rolloff; /* Current RollOff of the filter (x100) */
185
186 s16 derot_freq; /* Current derotator frequency (Hz) */
187 s16 derot_percent;
188
189 s16 direction; /* Current derotator search direction */
190 s16 derot_step; /* Derotator step (binary value) */
191 s16 t_timing; /* Timing loop time constant (ms) */
192 s16 t_derot; /* Derotator time constant (ms) */
193 s16 t_data; /* Data recovery time constant (ms) */
194 s16 sub_dir; /* Direction of the next sub range */
195
196 s16 t_agc1; /* Agc1 time constant (ms) */
197 s16 t_agc2; /* Agc2 time constant (ms) */
198
199 u32 lock; /* Demod internal lock state */
200 enum stb0899_status status; /* Demod internal status */
201
202 /* DVB-S2 */
203 s32 agc_gain; /* RF AGC Gain */
204 s32 center_freq; /* Nominal carrier frequency */
205 s32 av_frame_coarse; /* Coarse carrier freq search frames */
206 s32 av_frame_fine; /* Fine carrier freq search frames */
207
208 s16 step_size; /* Carrier frequency search step size */
209
210 enum stb0899_alpha rrc_alpha;
211 enum stb0899_inversion inversion;
212 enum stb0899_modcod modcod;
213 u8 pilots; /* Pilots found */
214
215 enum stb0899_frame frame_length;
216 u8 v_status; /* VSTATUS */
217 u8 err_ctrl; /* ERRCTRLn */
218};
219
220struct stb0899_state {
221 struct i2c_adapter *i2c;
222 struct stb0899_config *config;
223 struct dvb_frontend frontend;
224
225 u32 verbose; /* Cached module verbosity level */
226
227 struct stb0899_internal internal; /* Device internal parameters */
228
229 /* cached params from API */
230 enum dvbfe_delsys delsys;
231 struct stb0899_params params;
232
233 u32 rx_freq; /* DiSEqC 2.0 receiver freq */
234 struct mutex search_lock;
235};
236/* stb0899.c */
237extern int stb0899_read_reg(struct stb0899_state *state,
238 unsigned int reg);
239
240extern u32 _stb0899_read_s2reg(struct stb0899_state *state,
241 u32 stb0899_i2cdev,
242 u32 stb0899_base_addr,
243 u16 stb0899_reg_offset);
244
245extern int stb0899_read_regs(struct stb0899_state *state,
246 unsigned int reg, u8 *buf,
247 size_t count);
248
249extern int stb0899_write_regs(struct stb0899_state *state,
250 unsigned int reg, u8 *data,
251 size_t count);
252
253extern int stb0899_write_reg(struct stb0899_state *state,
254 unsigned int reg,
255 u8 data);
256
257extern int stb0899_write_s2reg(struct stb0899_state *state,
258 u32 stb0899_i2cdev,
259 u32 stb0899_base_addr,
260 u16 stb0899_reg_offset,
261 u32 stb0899_data);
262
263
264#define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG))
265//#define STB0899_WRITE_S2REG(DEVICE, REG, DATA) (_stb0899_write_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG, DATA))
266
267/* stb0899_algo.c */
268extern enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state);
269extern enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state);
270extern long stb0899_carr_width(struct stb0899_state *state);
271
272#endif //__STB0899_PRIV_H
diff --git a/drivers/media/dvb/frontends/stb0899_reg.h b/drivers/media/dvb/frontends/stb0899_reg.h
new file mode 100644
index 00000000000..6d2dc790e22
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_reg.h
@@ -0,0 +1,2018 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STB0899_REG_H
23#define __STB0899_REG_H
24
25/* S1 */
26#define STB0899_DEV_ID 0xf000
27#define STB0899_CHIP_ID (0x0f << 4)
28#define STB0899_OFFST_CHIP_ID 4
29#define STB0899_WIDTH_CHIP_ID 4
30#define STB0899_CHIP_REL (0x0f << 0)
31#define STB0899_OFFST_CHIP_REL 0
32#define STB0899_WIDTH_CHIP_REL 4
33
34#define STB0899_DEMOD 0xf40e
35#define STB0899_MODECOEFF (0x01 << 0)
36#define STB0899_OFFST_MODECOEFF 0
37#define STB0899_WIDTH_MODECOEFF 1
38
39#define STB0899_RCOMPC 0xf410
40#define STB0899_AGC1CN 0xf412
41#define STB0899_AGC1REF 0xf413
42#define STB0899_RTC 0xf417
43#define STB0899_TMGCFG 0xf418
44#define STB0899_AGC2REF 0xf419
45#define STB0899_TLSR 0xf41a
46
47#define STB0899_CFD 0xf41b
48#define STB0899_CFD_ON (0x01 << 7)
49#define STB0899_OFFST_CFD_ON 7
50#define STB0899_WIDTH_CFD_ON 1
51
52#define STB0899_ACLC 0xf41c
53
54#define STB0899_BCLC 0xf41d
55#define STB0899_OFFST_ALGO 6
56#define STB0899_WIDTH_ALGO_QPSK2 2
57#define STB0899_ALGO_QPSK2 (2 << 6)
58#define STB0899_ALGO_QPSK1 (1 << 6)
59#define STB0899_ALGO_BPSK (0 << 6)
60#define STB0899_OFFST_BETA 0
61#define STB0899_WIDTH_BETA 6
62
63#define STB0899_EQON 0xf41e
64#define STB0899_LDT 0xf41f
65#define STB0899_LDT2 0xf420
66#define STB0899_EQUALREF 0xf425
67#define STB0899_TMGRAMP 0xf426
68#define STB0899_TMGTHD 0xf427
69#define STB0899_IDCCOMP 0xf428
70#define STB0899_QDCCOMP 0xf429
71#define STB0899_POWERI 0xf42a
72#define STB0899_POWERQ 0xf42b
73#define STB0899_RCOMP 0xf42c
74
75#define STB0899_AGCIQIN 0xf42e
76#define STB0899_AGCIQVALUE (0xff << 0)
77#define STB0899_OFFST_AGCIQVALUE 0
78#define STB0899_WIDTH_AGCIQVALUE 8
79
80#define STB0899_AGC2I1 0xf436
81#define STB0899_AGC2I2 0xf437
82
83#define STB0899_TLIR 0xf438
84#define STB0899_TLIR_TMG_LOCK_IND (0xff << 0)
85#define STB0899_OFFST_TLIR_TMG_LOCK_IND 0
86#define STB0899_WIDTH_TLIR_TMG_LOCK_IND 8
87
88#define STB0899_RTF 0xf439
89#define STB0899_RTF_TIMING_LOOP_FREQ (0xff << 0)
90#define STB0899_OFFST_RTF_TIMING_LOOP_FREQ 0
91#define STB0899_WIDTH_RTF_TIMING_LOOP_FREQ 8
92
93#define STB0899_DSTATUS 0xf43a
94#define STB0899_CARRIER_FOUND (0x01 << 7)
95#define STB0899_OFFST_CARRIER_FOUND 7
96#define STB0899_WIDTH_CARRIER_FOUND 1
97#define STB0899_TMG_LOCK (0x01 << 6)
98#define STB0899_OFFST_TMG_LOCK 6
99#define STB0899_WIDTH_TMG_LOCK 1
100#define STB0899_DEMOD_LOCK (0x01 << 5)
101#define STB0899_OFFST_DEMOD_LOCK 5
102#define STB0899_WIDTH_DEMOD_LOCK 1
103#define STB0899_TMG_AUTO (0x01 << 4)
104#define STB0899_OFFST_TMG_AUTO 4
105#define STB0899_WIDTH_TMG_AUTO 1
106#define STB0899_END_MAIN (0x01 << 3)
107#define STB0899_OFFST_END_MAIN 3
108#define STB0899_WIDTH_END_MAIN 1
109
110#define STB0899_LDI 0xf43b
111#define STB0899_OFFST_LDI 0
112#define STB0899_WIDTH_LDI 8
113
114#define STB0899_CFRM 0xf43e
115#define STB0899_OFFST_CFRM 0
116#define STB0899_WIDTH_CFRM 8
117
118#define STB0899_CFRL 0xf43f
119#define STB0899_OFFST_CFRL 0
120#define STB0899_WIDTH_CFRL 8
121
122#define STB0899_NIRM 0xf440
123#define STB0899_OFFST_NIRM 0
124#define STB0899_WIDTH_NIRM 8
125
126#define STB0899_NIRL 0xf441
127#define STB0899_OFFST_NIRL 0
128#define STB0899_WIDTH_NIRL 8
129
130#define STB0899_ISYMB 0xf444
131#define STB0899_QSYMB 0xf445
132
133#define STB0899_SFRH 0xf446
134#define STB0899_OFFST_SFRH 0
135#define STB0899_WIDTH_SFRH 8
136
137#define STB0899_SFRM 0xf447
138#define STB0899_OFFST_SFRM 0
139#define STB0899_WIDTH_SFRM 8
140
141#define STB0899_SFRL 0xf448
142#define STB0899_OFFST_SFRL 4
143#define STB0899_WIDTH_SFRL 4
144
145#define STB0899_SFRUPH 0xf44c
146#define STB0899_SFRUPM 0xf44d
147#define STB0899_SFRUPL 0xf44e
148
149#define STB0899_EQUAI1 0xf4e0
150#define STB0899_EQUAQ1 0xf4e1
151#define STB0899_EQUAI2 0xf4e2
152#define STB0899_EQUAQ2 0xf4e3
153#define STB0899_EQUAI3 0xf4e4
154#define STB0899_EQUAQ3 0xf4e5
155#define STB0899_EQUAI4 0xf4e6
156#define STB0899_EQUAQ4 0xf4e7
157#define STB0899_EQUAI5 0xf4e8
158#define STB0899_EQUAQ5 0xf4e9
159
160#define STB0899_DSTATUS2 0xf50c
161#define STB0899_DS2_TMG_AUTOSRCH (0x01 << 7)
162#define STB8999_OFFST_DS2_TMG_AUTOSRCH 7
163#define STB0899_WIDTH_DS2_TMG_AUTOSRCH 1
164#define STB0899_DS2_END_MAINLOOP (0x01 << 6)
165#define STB0899_OFFST_DS2_END_MAINLOOP 6
166#define STB0899_WIDTH_DS2_END_MAINLOOP 1
167#define STB0899_DS2_CFSYNC (0x01 << 5)
168#define STB0899_OFFST_DS2_CFSYNC 5
169#define STB0899_WIDTH_DS2_CFSYNC 1
170#define STB0899_DS2_TMGLOCK (0x01 << 4)
171#define STB0899_OFFST_DS2_TMGLOCK 4
172#define STB0899_WIDTH_DS2_TMGLOCK 1
173#define STB0899_DS2_DEMODWAIT (0x01 << 3)
174#define STB0899_OFFST_DS2_DEMODWAIT 3
175#define STB0899_WIDTH_DS2_DEMODWAIT 1
176#define STB0899_DS2_FECON (0x01 << 1)
177#define STB0899_OFFST_DS2_FECON 1
178#define STB0899_WIDTH_DS2_FECON 1
179
180/* S1 FEC */
181#define STB0899_VSTATUS 0xf50d
182#define STB0899_VSTATUS_VITERBI_ON (0x01 << 7)
183#define STB0899_OFFST_VSTATUS_VITERBI_ON 7
184#define STB0899_WIDTH_VSTATUS_VITERBI_ON 1
185#define STB0899_VSTATUS_END_LOOPVIT (0x01 << 6)
186#define STB0899_OFFST_VSTATUS_END_LOOPVIT 6
187#define STB0899_WIDTH_VSTATUS_END_LOOPVIT 1
188#define STB0899_VSTATUS_PRFVIT (0x01 << 4)
189#define STB0899_OFFST_VSTATUS_PRFVIT 4
190#define STB0899_WIDTH_VSTATUS_PRFVIT 1
191#define STB0899_VSTATUS_LOCKEDVIT (0x01 << 3)
192#define STB0899_OFFST_VSTATUS_LOCKEDVIT 3
193#define STB0899_WIDTH_VSTATUS_LOCKEDVIT 1
194
195#define STB0899_VERROR 0xf50f
196
197#define STB0899_IQSWAP 0xf523
198#define STB0899_SYM (0x01 << 3)
199#define STB0899_OFFST_SYM 3
200#define STB0899_WIDTH_SYM 1
201
202#define STB0899_FECAUTO1 0xf530
203#define STB0899_DSSSRCH (0x01 << 3)
204#define STB0899_OFFST_DSSSRCH 3
205#define STB0899_WIDTH_DSSSRCH 1
206#define STB0899_SYMSRCH (0x01 << 2)
207#define STB0899_OFFST_SYMSRCH 2
208#define STB0899_WIDTH_SYMSRCH 1
209#define STB0899_QPSKSRCH (0x01 << 1)
210#define STB0899_OFFST_QPSKSRCH 1
211#define STB0899_WIDTH_QPSKSRCH 1
212#define STB0899_BPSKSRCH (0x01 << 0)
213#define STB0899_OFFST_BPSKSRCH 0
214#define STB0899_WIDTH_BPSKSRCH 1
215
216#define STB0899_FECM 0xf533
217#define STB0899_FECM_NOT_DVB (0x01 << 7)
218#define STB0899_OFFST_FECM_NOT_DVB 7
219#define STB0899_WIDTH_FECM_NOT_DVB 1
220#define STB0899_FECM_RSVD1 (0x07 << 4)
221#define STB0899_OFFST_FECM_RSVD1 4
222#define STB0899_WIDTH_FECM_RSVD1 3
223#define STB0899_FECM_VITERBI_ON (0x01 << 3)
224#define STB0899_OFFST_FECM_VITERBI_ON 3
225#define STB0899_WIDTH_FECM_VITERBI_ON 1
226#define STB0899_FECM_RSVD0 (0x01 << 2)
227#define STB0899_OFFST_FECM_RSVD0 2
228#define STB0899_WIDTH_FECM_RSVD0 1
229#define STB0899_FECM_SYNCDIS (0x01 << 1)
230#define STB0899_OFFST_FECM_SYNCDIS 1
231#define STB0899_WIDTH_FECM_SYNCDIS 1
232#define STB0899_FECM_SYMI (0x01 << 0)
233#define STB0899_OFFST_FECM_SYMI 1
234#define STB0899_WIDTH_FECM_SYMI 1
235
236#define STB0899_VTH12 0xf534
237#define STB0899_VTH23 0xf535
238#define STB0899_VTH34 0xf536
239#define STB0899_VTH56 0xf537
240#define STB0899_VTH67 0xf538
241#define STB0899_VTH78 0xf539
242
243#define STB0899_PRVIT 0xf53c
244#define STB0899_PR_7_8 (0x01 << 5)
245#define STB0899_OFFST_PR_7_8 5
246#define STB0899_WIDTH_PR_7_8 1
247#define STB0899_PR_6_7 (0x01 << 4)
248#define STB0899_OFFST_PR_6_7 4
249#define STB0899_WIDTH_PR_6_7 1
250#define STB0899_PR_5_6 (0x01 << 3)
251#define STB0899_OFFST_PR_5_6 3
252#define STB0899_WIDTH_PR_5_6 1
253#define STB0899_PR_3_4 (0x01 << 2)
254#define STB0899_OFFST_PR_3_4 2
255#define STB0899_WIDTH_PR_3_4 1
256#define STB0899_PR_2_3 (0x01 << 1)
257#define STB0899_OFFST_PR_2_3 1
258#define STB0899_WIDTH_PR_2_3 1
259#define STB0899_PR_1_2 (0x01 << 0)
260#define STB0899_OFFST_PR_1_2 0
261#define STB0899_WIDTH_PR_1_2 1
262
263#define STB0899_VITSYNC 0xf53d
264#define STB0899_AM (0x01 << 7)
265#define STB0899_OFFST_AM 7
266#define STB0899_WIDTH_AM 1
267#define STB0899_FREEZE (0x01 << 6)
268#define STB0899_OFFST_FREEZE 6
269#define STB0899_WIDTH_FREEZE 1
270#define STB0899_SN_65536 (0x03 << 4)
271#define STB0899_OFFST_SN_65536 4
272#define STB0899_WIDTH_SN_65536 2
273#define STB0899_SN_16384 (0x01 << 5)
274#define STB0899_OFFST_SN_16384 5
275#define STB0899_WIDTH_SN_16384 1
276#define STB0899_SN_4096 (0x01 << 4)
277#define STB0899_OFFST_SN_4096 4
278#define STB0899_WIDTH_SN_4096 1
279#define STB0899_SN_1024 (0x00 << 4)
280#define STB0899_OFFST_SN_1024 4
281#define STB0899_WIDTH_SN_1024 0
282#define STB0899_TO_128 (0x03 << 2)
283#define STB0899_OFFST_TO_128 2
284#define STB0899_WIDTH_TO_128 2
285#define STB0899_TO_64 (0x01 << 3)
286#define STB0899_OFFST_TO_64 3
287#define STB0899_WIDTH_TO_64 1
288#define STB0899_TO_32 (0x01 << 2)
289#define STB0899_OFFST_TO_32 2
290#define STB0899_WIDTH_TO_32 1
291#define STB0899_TO_16 (0x00 << 2)
292#define STB0899_OFFST_TO_16 2
293#define STB0899_WIDTH_TO_16 0
294#define STB0899_HYST_128 (0x03 << 1)
295#define STB0899_OFFST_HYST_128 1
296#define STB0899_WIDTH_HYST_128 2
297#define STB0899_HYST_64 (0x01 << 1)
298#define STB0899_OFFST_HYST_64 1
299#define STB0899_WIDTH_HYST_64 1
300#define STB0899_HYST_32 (0x01 << 0)
301#define STB0899_OFFST_HYST_32 0
302#define STB0899_WIDTH_HYST_32 1
303#define STB0899_HYST_16 (0x00 << 0)
304#define STB0899_OFFST_HYST_16 0
305#define STB0899_WIDTH_HYST_16 0
306
307#define STB0899_RSULC 0xf548
308#define STB0899_ULDIL_ON (0x01 << 7)
309#define STB0899_OFFST_ULDIL_ON 7
310#define STB0899_WIDTH_ULDIL_ON 1
311#define STB0899_ULAUTO_ON (0x01 << 6)
312#define STB0899_OFFST_ULAUTO_ON 6
313#define STB0899_WIDTH_ULAUTO_ON 1
314#define STB0899_ULRS_ON (0x01 << 5)
315#define STB0899_OFFST_ULRS_ON 5
316#define STB0899_WIDTH_ULRS_ON 1
317#define STB0899_ULDESCRAM_ON (0x01 << 4)
318#define STB0899_OFFST_ULDESCRAM_ON 4
319#define STB0899_WIDTH_ULDESCRAM_ON 1
320#define STB0899_UL_DISABLE (0x01 << 2)
321#define STB0899_OFFST_UL_DISABLE 2
322#define STB0899_WIDTH_UL_DISABLE 1
323#define STB0899_NOFTHRESHOLD (0x01 << 0)
324#define STB0899_OFFST_NOFTHRESHOLD 0
325#define STB0899_WIDTH_NOFTHRESHOLD 1
326
327#define STB0899_RSLLC 0xf54a
328#define STB0899_DEMAPVIT 0xf583
329#define STB0899_DEMAPVIT_RSVD (0x01 << 7)
330#define STB0899_OFFST_DEMAPVIT_RSVD 7
331#define STB0899_WIDTH_DEMAPVIT_RSVD 1
332#define STB0899_DEMAPVIT_KDIVIDER (0x7f << 0)
333#define STB0899_OFFST_DEMAPVIT_KDIVIDER 0
334#define STB0899_WIDTH_DEMAPVIT_KDIVIDER 7
335
336#define STB0899_PLPARM 0xf58c
337#define STB0899_VITMAPPING (0x07 << 5)
338#define STB0899_OFFST_VITMAPPING 5
339#define STB0899_WIDTH_VITMAPPING 3
340#define STB0899_VITMAPPING_BPSK (0x01 << 5)
341#define STB0899_OFFST_VITMAPPING_BPSK 5
342#define STB0899_WIDTH_VITMAPPING_BPSK 1
343#define STB0899_VITMAPPING_QPSK (0x00 << 5)
344#define STB0899_OFFST_VITMAPPING_QPSK 5
345#define STB0899_WIDTH_VITMAPPING_QPSK 0
346#define STB0899_VITCURPUN (0x1f << 0)
347#define STB0899_OFFST_VITCURPUN 0
348#define STB0899_WIDTH_VITCURPUN 5
349#define STB0899_VITCURPUN_1_2 (0x0d << 0)
350#define STB0899_VITCURPUN_2_3 (0x12 << 0)
351#define STB0899_VITCURPUN_3_4 (0x15 << 0)
352#define STB0899_VITCURPUN_5_6 (0x18 << 0)
353#define STB0899_VITCURPUN_6_7 (0x19 << 0)
354#define STB0899_VITCURPUN_7_8 (0x1a << 0)
355
356/* S2 DEMOD */
357#define STB0899_OFF0_DMD_STATUS 0xf300
358#define STB0899_BASE_DMD_STATUS 0x00000000
359#define STB0899_IF_AGC_LOCK (0x01 << 0)
360#define STB0899_OFFST_IF_AGC_LOCK 0
361#define STB0899_WIDTH_IF_AGC_LOCK 1
362
363#define STB0899_OFF0_CRL_FREQ 0xf304
364#define STB0899_BASE_CRL_FREQ 0x00000000
365#define STB0899_CARR_FREQ (0x1fffffff << 0)
366#define STB0899_OFFST_CARR_FREQ 0
367#define STB0899_WIDTH_CARR_FREQ 30
368
369#define STB0899_OFF0_BTR_FREQ 0xf308
370#define STB0899_BASE_BTR_FREQ 0x00000000
371#define STB0899_BTR_FREQ (0xfffffff << 0)
372#define STB0899_OFFST_BTR_FREQ 0
373#define STB0899_WIDTH_BTR_FREQ 28
374
375#define STB0899_OFF0_IF_AGC_GAIN 0xf30c
376#define STB0899_BASE_IF_AGC_GAIN 0x00000000
377#define STB0899_IF_AGC_GAIN (0x3fff < 0)
378#define STB0899_OFFST_IF_AGC_GAIN 0
379#define STB0899_WIDTH_IF_AGC_GAIN 14
380
381#define STB0899_OFF0_BB_AGC_GAIN 0xf310
382#define STB0899_BASE_BB_AGC_GAIN 0x00000000
383#define STB0899_BB_AGC_GAIN (0x3fff < 0)
384#define STB0899_OFFST_BB_AGC_GAIN 0
385#define STB0899_WIDTH_BB_AGC_GAIN 14
386
387#define STB0899_OFF0_DC_OFFSET 0xf314
388#define STB0899_BASE_DC_OFFSET 0x00000000
389#define STB0899_I (0xff < 8)
390#define STB0899_OFFST_I 8
391#define STB0899_WIDTH_I 8
392#define STB0899_Q (0xff < 0)
393#define STB0899_OFFST_Q 8
394#define STB0899_WIDTH_Q 8
395
396#define STB0899_OFF0_DMD_CNTRL 0xf31c
397#define STB0899_BASE_DMD_CNTRL 0x00000000
398#define STB0899_ADC0_PINS1IN (0x01 << 6)
399#define STB0899_OFFST_ADC0_PINS1IN 6
400#define STB0899_WIDTH_ADC0_PINS1IN 1
401#define STB0899_IN2COMP1_OFFBIN0 (0x01 << 3)
402#define STB0899_OFFST_IN2COMP1_OFFBIN0 3
403#define STB0899_WIDTH_IN2COMP1_OFFBIN0 1
404#define STB0899_DC_COMP (0x01 << 2)
405#define STB0899_OFFST_DC_COMP 2
406#define STB0899_WIDTH_DC_COMP 1
407#define STB0899_MODMODE (0x03 << 0)
408#define STB0899_OFFST_MODMODE 0
409#define STB0899_WIDTH_MODMODE 2
410
411#define STB0899_OFF0_IF_AGC_CNTRL 0xf320
412#define STB0899_BASE_IF_AGC_CNTRL 0x00000000
413#define STB0899_IF_GAIN_INIT (0x3fff << 13)
414#define STB0899_OFFST_IF_GAIN_INIT 13
415#define STB0899_WIDTH_IF_GAIN_INIT 14
416#define STB0899_IF_GAIN_SENSE (0x01 << 12)
417#define STB0899_OFFST_IF_GAIN_SENSE 12
418#define STB0899_WIDTH_IF_GAIN_SENSE 1
419#define STB0899_IF_LOOP_GAIN (0x0f << 8)
420#define STB0899_OFFST_IF_LOOP_GAIN 8
421#define STB0899_WIDTH_IF_LOOP_GAIN 4
422#define STB0899_IF_LD_GAIN_INIT (0x01 << 7)
423#define STB0899_OFFST_IF_LD_GAIN_INIT 7
424#define STB0899_WIDTH_IF_LD_GAIN_INIT 1
425#define STB0899_IF_AGC_REF (0x7f << 0)
426#define STB0899_OFFST_IF_AGC_REF 0
427#define STB0899_WIDTH_IF_AGC_REF 7
428
429#define STB0899_OFF0_BB_AGC_CNTRL 0xf324
430#define STB0899_BASE_BB_AGC_CNTRL 0x00000000
431#define STB0899_BB_GAIN_INIT (0x3fff << 12)
432#define STB0899_OFFST_BB_GAIN_INIT 12
433#define STB0899_WIDTH_BB_GAIN_INIT 14
434#define STB0899_BB_LOOP_GAIN (0x0f << 8)
435#define STB0899_OFFST_BB_LOOP_GAIN 8
436#define STB0899_WIDTH_BB_LOOP_GAIN 4
437#define STB0899_BB_LD_GAIN_INIT (0x01 << 7)
438#define STB0899_OFFST_BB_LD_GAIN_INIT 7
439#define STB0899_WIDTH_BB_LD_GAIN_INIT 1
440#define STB0899_BB_AGC_REF (0x7f << 0)
441#define STB0899_OFFST_BB_AGC_REF 0
442#define STB0899_WIDTH_BB_AGC_REF 7
443
444#define STB0899_OFF0_CRL_CNTRL 0xf328
445#define STB0899_BASE_CRL_CNTRL 0x00000000
446#define STB0899_CRL_LOCK_CLEAR (0x01 << 5)
447#define STB0899_OFFST_CRL_LOCK_CLEAR 5
448#define STB0899_WIDTH_CRL_LOCK_CLEAR 1
449#define STB0899_CRL_SWPR_CLEAR (0x01 << 4)
450#define STB0899_OFFST_CRL_SWPR_CLEAR 4
451#define STB0899_WIDTH_CRL_SWPR_CLEAR 1
452#define STB0899_CRL_SWP_ENA (0x01 << 3)
453#define STB0899_OFFST_CRL_SWP_ENA 3
454#define STB0899_WIDTH_CRL_SWP_ENA 1
455#define STB0899_CRL_DET_SEL (0x01 << 2)
456#define STB0899_OFFST_CRL_DET_SEL 2
457#define STB0899_WIDTH_CRL_DET_SEL 1
458#define STB0899_CRL_SENSE (0x01 << 1)
459#define STB0899_OFFST_CRL_SENSE 1
460#define STB0899_WIDTH_CRL_SENSE 1
461#define STB0899_CRL_PHSERR_CLEAR (0x01 << 0)
462#define STB0899_OFFST_CRL_PHSERR_CLEAR 0
463#define STB0899_WIDTH_CRL_PHSERR_CLEAR 1
464
465#define STB0899_OFF0_CRL_PHS_INIT 0xf32c
466#define STB0899_BASE_CRL_PHS_INIT 0x00000000
467#define STB0899_CRL_PHS_INIT_31 (0x1 << 30)
468#define STB0899_OFFST_CRL_PHS_INIT_31 30
469#define STB0899_WIDTH_CRL_PHS_INIT_31 1
470#define STB0899_CRL_LD_INIT_PHASE (0x1 << 24)
471#define STB0899_OFFST_CRL_LD_INIT_PHASE 24
472#define STB0899_WIDTH_CRL_LD_INIT_PHASE 1
473#define STB0899_CRL_INIT_PHASE (0xffffff << 0)
474#define STB0899_OFFST_CRL_INIT_PHASE 0
475#define STB0899_WIDTH_CRL_INIT_PHASE 24
476
477#define STB0899_OFF0_CRL_FREQ_INIT 0xf330
478#define STB0899_BASE_CRL_FREQ_INIT 0x00000000
479#define STB0899_CRL_FREQ_INIT_31 (0x1 << 30)
480#define STB0899_OFFST_CRL_FREQ_INIT_31 30
481#define STB0899_WIDTH_CRL_FREQ_INIT_31 1
482#define STB0899_CRL_LD_FREQ_INIT (0x1 << 24)
483#define STB0899_OFFST_CRL_LD_FREQ_INIT 24
484#define STB0899_WIDTH_CRL_LD_FREQ_INIT 1
485#define STB0899_CRL_FREQ_INIT (0xffffff << 0)
486#define STB0899_OFFST_CRL_FREQ_INIT 0
487#define STB0899_WIDTH_CRL_FREQ_INIT 24
488
489#define STB0899_OFF0_CRL_LOOP_GAIN 0xf334
490#define STB0899_BASE_CRL_LOOP_GAIN 0x00000000
491#define STB0899_KCRL2_RSHFT (0xf << 16)
492#define STB0899_OFFST_KCRL2_RSHFT 16
493#define STB0899_WIDTH_KCRL2_RSHFT 4
494#define STB0899_KCRL1 (0xf << 12)
495#define STB0899_OFFST_KCRL1 12
496#define STB0899_WIDTH_KCRL1 4
497#define STB0899_KCRL1_RSHFT (0xf << 8)
498#define STB0899_OFFST_KCRL1_RSHFT 8
499#define STB0899_WIDTH_KCRL1_RSHFT 4
500#define STB0899_KCRL0 (0xf << 4)
501#define STB0899_OFFST_KCRL0 4
502#define STB0899_WIDTH_KCRL0 4
503#define STB0899_KCRL0_RSHFT (0xf << 0)
504#define STB0899_OFFST_KCRL0_RSHFT 0
505#define STB0899_WIDTH_KCRL0_RSHFT 4
506
507#define STB0899_OFF0_CRL_NOM_FREQ 0xf338
508#define STB0899_BASE_CRL_NOM_FREQ 0x00000000
509#define STB0899_CRL_NOM_FREQ (0x3fffffff << 0)
510#define STB0899_OFFST_CRL_NOM_FREQ 0
511#define STB0899_WIDTH_CRL_NOM_FREQ 30
512
513#define STB0899_OFF0_CRL_SWP_RATE 0xf33c
514#define STB0899_BASE_CRL_SWP_RATE 0x00000000
515#define STB0899_CRL_SWP_RATE (0x3fffffff << 0)
516#define STB0899_OFFST_CRL_SWP_RATE 0
517#define STB0899_WIDTH_CRL_SWP_RATE 30
518
519#define STB0899_OFF0_CRL_MAX_SWP 0xf340
520#define STB0899_BASE_CRL_MAX_SWP 0x00000000
521#define STB0899_CRL_MAX_SWP (0x3fffffff << 0)
522#define STB0899_OFFST_CRL_MAX_SWP 0
523#define STB0899_WIDTH_CRL_MAX_SWP 30
524
525#define STB0899_OFF0_CRL_LK_CNTRL 0xf344
526#define STB0899_BASE_CRL_LK_CNTRL 0x00000000
527
528#define STB0899_OFF0_DECIM_CNTRL 0xf348
529#define STB0899_BASE_DECIM_CNTRL 0x00000000
530#define STB0899_BAND_LIMIT_B (0x01 << 5)
531#define STB0899_OFFST_BAND_LIMIT_B 5
532#define STB0899_WIDTH_BAND_LIMIT_B 1
533#define STB0899_WIN_SEL (0x03 << 3)
534#define STB0899_OFFST_WIN_SEL 3
535#define STB0899_WIDTH_WIN_SEL 2
536#define STB0899_DECIM_RATE (0x07 << 0)
537#define STB0899_OFFST_DECIM_RATE 0
538#define STB0899_WIDTH_DECIM_RATE 3
539
540#define STB0899_OFF0_BTR_CNTRL 0xf34c
541#define STB0899_BASE_BTR_CNTRL 0x00000000
542#define STB0899_BTR_FREQ_CORR (0x7ff << 4)
543#define STB0899_OFFST_BTR_FREQ_CORR 4
544#define STB0899_WIDTH_BTR_FREQ_CORR 11
545#define STB0899_BTR_CLR_LOCK (0x01 << 3)
546#define STB0899_OFFST_BTR_CLR_LOCK 3
547#define STB0899_WIDTH_BTR_CLR_LOCK 1
548#define STB0899_BTR_SENSE (0x01 << 2)
549#define STB0899_OFFST_BTR_SENSE 2
550#define STB0899_WIDTH_BTR_SENSE 1
551#define STB0899_BTR_ERR_ENA (0x01 << 1)
552#define STB0899_OFFST_BTR_ERR_ENA 1
553#define STB0899_WIDTH_BTR_ERR_ENA 1
554#define STB0899_INTRP_PHS_SENSE (0x01 << 0)
555#define STB0899_OFFST_INTRP_PHS_SENSE 0
556#define STB0899_WIDTH_INTRP_PHS_SENSE 1
557
558#define STB0899_OFF0_BTR_LOOP_GAIN 0xf350
559#define STB0899_BASE_BTR_LOOP_GAIN 0x00000000
560#define STB0899_KBTR2_RSHFT (0x0f << 16)
561#define STB0899_OFFST_KBTR2_RSHFT 16
562#define STB0899_WIDTH_KBTR2_RSHFT 4
563#define STB0899_KBTR1 (0x0f << 12)
564#define STB0899_OFFST_KBTR1 12
565#define STB0899_WIDTH_KBTR1 4
566#define STB0899_KBTR1_RSHFT (0x0f << 8)
567#define STB0899_OFFST_KBTR1_RSHFT 8
568#define STB0899_WIDTH_KBTR1_RSHFT 4
569#define STB0899_KBTR0 (0x0f << 4)
570#define STB0899_OFFST_KBTR0 4
571#define STB0899_WIDTH_KBTR0 4
572#define STB0899_KBTR0_RSHFT (0x0f << 0)
573#define STB0899_OFFST_KBTR0_RSHFT 0
574#define STB0899_WIDTH_KBTR0_RSHFT 4
575
576#define STB0899_OFF0_BTR_PHS_INIT 0xf354
577#define STB0899_BASE_BTR_PHS_INIT 0x00000000
578#define STB0899_BTR_LD_PHASE_INIT (0x01 << 28)
579#define STB0899_OFFST_BTR_LD_PHASE_INIT 28
580#define STB0899_WIDTH_BTR_LD_PHASE_INIT 1
581#define STB0899_BTR_INIT_PHASE (0xfffffff << 0)
582#define STB0899_OFFST_BTR_INIT_PHASE 0
583#define STB0899_WIDTH_BTR_INIT_PHASE 28
584
585#define STB0899_OFF0_BTR_FREQ_INIT 0xf358
586#define STB0899_BASE_BTR_FREQ_INIT 0x00000000
587#define STB0899_BTR_LD_FREQ_INIT (1 << 28)
588#define STB0899_OFFST_BTR_LD_FREQ_INIT 28
589#define STB0899_WIDTH_BTR_LD_FREQ_INIT 1
590#define STB0899_BTR_FREQ_INIT (0xfffffff << 0)
591#define STB0899_OFFST_BTR_FREQ_INIT 0
592#define STB0899_WIDTH_BTR_FREQ_INIT 28
593
594#define STB0899_OFF0_BTR_NOM_FREQ 0xf35c
595#define STB0899_BASE_BTR_NOM_FREQ 0x00000000
596#define STB0899_BTR_NOM_FREQ (0xfffffff << 0)
597#define STB0899_OFFST_BTR_NOM_FREQ 0
598#define STB0899_WIDTH_BTR_NOM_FREQ 28
599
600#define STB0899_OFF0_BTR_LK_CNTRL 0xf360
601#define STB0899_BASE_BTR_LK_CNTRL 0x00000000
602#define STB0899_BTR_MIN_ENERGY (0x0f << 24)
603#define STB0899_OFFST_BTR_MIN_ENERGY 24
604#define STB0899_WIDTH_BTR_MIN_ENERGY 4
605#define STB0899_BTR_LOCK_TH_LO (0xff << 16)
606#define STB0899_OFFST_BTR_LOCK_TH_LO 16
607#define STB0899_WIDTH_BTR_LOCK_TH_LO 8
608#define STB0899_BTR_LOCK_TH_HI (0xff << 8)
609#define STB0899_OFFST_BTR_LOCK_TH_HI 8
610#define STB0899_WIDTH_BTR_LOCK_TH_HI 8
611#define STB0899_BTR_LOCK_GAIN (0x03 << 6)
612#define STB0899_OFFST_BTR_LOCK_GAIN 6
613#define STB0899_WIDTH_BTR_LOCK_GAIN 2
614#define STB0899_BTR_LOCK_LEAK (0x3f << 0)
615#define STB0899_OFFST_BTR_LOCK_LEAK 0
616#define STB0899_WIDTH_BTR_LOCK_LEAK 6
617
618#define STB0899_OFF0_DECN_CNTRL 0xf364
619#define STB0899_BASE_DECN_CNTRL 0x00000000
620
621#define STB0899_OFF0_TP_CNTRL 0xf368
622#define STB0899_BASE_TP_CNTRL 0x00000000
623
624#define STB0899_OFF0_TP_BUF_STATUS 0xf36c
625#define STB0899_BASE_TP_BUF_STATUS 0x00000000
626#define STB0899_TP_BUFFER_FULL (1 << 0)
627
628#define STB0899_OFF0_DC_ESTIM 0xf37c
629#define STB0899_BASE_DC_ESTIM 0x0000
630#define STB0899_I_DC_ESTIMATE (0xff << 8)
631#define STB0899_OFFST_I_DC_ESTIMATE 8
632#define STB0899_WIDTH_I_DC_ESTIMATE 8
633#define STB0899_Q_DC_ESTIMATE (0xff << 0)
634#define STB0899_OFFST_Q_DC_ESTIMATE 0
635#define STB0899_WIDTH_Q_DC_ESTIMATE 8
636
637#define STB0899_OFF0_FLL_CNTRL 0xf310
638#define STB0899_BASE_FLL_CNTRL 0x00000020
639#define STB0899_CRL_FLL_ACC (0x01 << 4)
640#define STB0899_OFFST_CRL_FLL_ACC 4
641#define STB0899_WIDTH_CRL_FLL_ACC 1
642#define STB0899_FLL_AVG_PERIOD (0x0f << 0)
643#define STB0899_OFFST_FLL_AVG_PERIOD 0
644#define STB0899_WIDTH_FLL_AVG_PERIOD 4
645
646#define STB0899_OFF0_FLL_FREQ_WD 0xf314
647#define STB0899_BASE_FLL_FREQ_WD 0x00000020
648#define STB0899_FLL_FREQ_WD (0xffffffff << 0)
649#define STB0899_OFFST_FLL_FREQ_WD 0
650#define STB0899_WIDTH_FLL_FREQ_WD 32
651
652#define STB0899_OFF0_ANTI_ALIAS_SEL 0xf358
653#define STB0899_BASE_ANTI_ALIAS_SEL 0x00000020
654#define STB0899_ANTI_ALIAS_SELB (0x03 << 0)
655#define STB0899_OFFST_ANTI_ALIAS_SELB 0
656#define STB0899_WIDTH_ANTI_ALIAS_SELB 2
657
658#define STB0899_OFF0_RRC_ALPHA 0xf35c
659#define STB0899_BASE_RRC_ALPHA 0x00000020
660#define STB0899_RRC_ALPHA (0x03 << 0)
661#define STB0899_OFFST_RRC_ALPHA 0
662#define STB0899_WIDTH_RRC_ALPHA 2
663
664#define STB0899_OFF0_DC_ADAPT_LSHFT 0xf360
665#define STB0899_BASE_DC_ADAPT_LSHFT 0x00000020
666#define STB0899_DC_ADAPT_LSHFT (0x077 << 0)
667#define STB0899_OFFST_DC_ADAPT_LSHFT 0
668#define STB0899_WIDTH_DC_ADAPT_LSHFT 3
669
670#define STB0899_OFF0_IMB_OFFSET 0xf364
671#define STB0899_BASE_IMB_OFFSET 0x00000020
672#define STB0899_PHS_IMB_COMP (0xff << 8)
673#define STB0899_OFFST_PHS_IMB_COMP 8
674#define STB0899_WIDTH_PHS_IMB_COMP 8
675#define STB0899_AMPL_IMB_COMP (0xff << 0)
676#define STB0899_OFFST_AMPL_IMB_COMP 0
677#define STB0899_WIDTH_AMPL_IMB_COMP 8
678
679#define STB0899_OFF0_IMB_ESTIMATE 0xf368
680#define STB0899_BASE_IMB_ESTIMATE 0x00000020
681#define STB0899_PHS_IMB_ESTIMATE (0xff << 8)
682#define STB0899_OFFST_PHS_IMB_ESTIMATE 8
683#define STB0899_WIDTH_PHS_IMB_ESTIMATE 8
684#define STB0899_AMPL_IMB_ESTIMATE (0xff << 0)
685#define STB0899_OFFST_AMPL_IMB_ESTIMATE 0
686#define STB0899_WIDTH_AMPL_IMB_ESTIMATE 8
687
688#define STB0899_OFF0_IMB_CNTRL 0xf36c
689#define STB0899_BASE_IMB_CNTRL 0x00000020
690#define STB0899_PHS_ADAPT_LSHFT (0x07 << 4)
691#define STB0899_OFFST_PHS_ADAPT_LSHFT 4
692#define STB0899_WIDTH_PHS_ADAPT_LSHFT 3
693#define STB0899_AMPL_ADAPT_LSHFT (0x07 << 1)
694#define STB0899_OFFST_AMPL_ADAPT_LSHFT 1
695#define STB0899_WIDTH_AMPL_ADAPT_LSHFT 3
696#define STB0899_IMB_COMP (0x01 << 0)
697#define STB0899_OFFST_IMB_COMP 0
698#define STB0899_WIDTH_IMB_COMP 1
699
700#define STB0899_OFF0_IF_AGC_CNTRL2 0xf374
701#define STB0899_BASE_IF_AGC_CNTRL2 0x00000020
702#define STB0899_IF_AGC_LOCK_TH (0xff << 11)
703#define STB0899_OFFST_IF_AGC_LOCK_TH 11
704#define STB0899_WIDTH_IF_AGC_LOCK_TH 8
705#define STB0899_IF_AGC_SD_DIV (0xff << 3)
706#define STB0899_OFFST_IF_AGC_SD_DIV 3
707#define STB0899_WIDTH_IF_AGC_SD_DIV 8
708#define STB0899_IF_AGC_DUMP_PER (0x07 << 0)
709#define STB0899_OFFST_IF_AGC_DUMP_PER 0
710#define STB0899_WIDTH_IF_AGC_DUMP_PER 3
711
712#define STB0899_OFF0_DMD_CNTRL2 0xf378
713#define STB0899_BASE_DMD_CNTRL2 0x00000020
714#define STB0899_SPECTRUM_INVERT (0x01 << 2)
715#define STB0899_OFFST_SPECTRUM_INVERT 2
716#define STB0899_WIDTH_SPECTRUM_INVERT 1
717#define STB0899_AGC_MODE (0x01 << 1)
718#define STB0899_OFFST_AGC_MODE 1
719#define STB0899_WIDTH_AGC_MODE 1
720#define STB0899_CRL_FREQ_ADJ (0x01 << 0)
721#define STB0899_OFFST_CRL_FREQ_ADJ 0
722#define STB0899_WIDTH_CRL_FREQ_ADJ 1
723
724#define STB0899_OFF0_TP_BUFFER 0xf300
725#define STB0899_BASE_TP_BUFFER 0x00000040
726#define STB0899_TP_BUFFER_IN (0xffff << 0)
727#define STB0899_OFFST_TP_BUFFER_IN 0
728#define STB0899_WIDTH_TP_BUFFER_IN 16
729
730#define STB0899_OFF0_TP_BUFFER1 0xf304
731#define STB0899_BASE_TP_BUFFER1 0x00000040
732#define STB0899_OFF0_TP_BUFFER2 0xf308
733#define STB0899_BASE_TP_BUFFER2 0x00000040
734#define STB0899_OFF0_TP_BUFFER3 0xf30c
735#define STB0899_BASE_TP_BUFFER3 0x00000040
736#define STB0899_OFF0_TP_BUFFER4 0xf310
737#define STB0899_BASE_TP_BUFFER4 0x00000040
738#define STB0899_OFF0_TP_BUFFER5 0xf314
739#define STB0899_BASE_TP_BUFFER5 0x00000040
740#define STB0899_OFF0_TP_BUFFER6 0xf318
741#define STB0899_BASE_TP_BUFFER6 0x00000040
742#define STB0899_OFF0_TP_BUFFER7 0xf31c
743#define STB0899_BASE_TP_BUFFER7 0x00000040
744#define STB0899_OFF0_TP_BUFFER8 0xf320
745#define STB0899_BASE_TP_BUFFER8 0x00000040
746#define STB0899_OFF0_TP_BUFFER9 0xf324
747#define STB0899_BASE_TP_BUFFER9 0x00000040
748#define STB0899_OFF0_TP_BUFFER10 0xf328
749#define STB0899_BASE_TP_BUFFER10 0x00000040
750#define STB0899_OFF0_TP_BUFFER11 0xf32c
751#define STB0899_BASE_TP_BUFFER11 0x00000040
752#define STB0899_OFF0_TP_BUFFER12 0xf330
753#define STB0899_BASE_TP_BUFFER12 0x00000040
754#define STB0899_OFF0_TP_BUFFER13 0xf334
755#define STB0899_BASE_TP_BUFFER13 0x00000040
756#define STB0899_OFF0_TP_BUFFER14 0xf338
757#define STB0899_BASE_TP_BUFFER14 0x00000040
758#define STB0899_OFF0_TP_BUFFER15 0xf33c
759#define STB0899_BASE_TP_BUFFER15 0x00000040
760#define STB0899_OFF0_TP_BUFFER16 0xf340
761#define STB0899_BASE_TP_BUFFER16 0x00000040
762#define STB0899_OFF0_TP_BUFFER17 0xf344
763#define STB0899_BASE_TP_BUFFER17 0x00000040
764#define STB0899_OFF0_TP_BUFFER18 0xf348
765#define STB0899_BASE_TP_BUFFER18 0x00000040
766#define STB0899_OFF0_TP_BUFFER19 0xf34c
767#define STB0899_BASE_TP_BUFFER19 0x00000040
768#define STB0899_OFF0_TP_BUFFER20 0xf350
769#define STB0899_BASE_TP_BUFFER20 0x00000040
770#define STB0899_OFF0_TP_BUFFER21 0xf354
771#define STB0899_BASE_TP_BUFFER21 0x00000040
772#define STB0899_OFF0_TP_BUFFER22 0xf358
773#define STB0899_BASE_TP_BUFFER22 0x00000040
774#define STB0899_OFF0_TP_BUFFER23 0xf35c
775#define STB0899_BASE_TP_BUFFER23 0x00000040
776#define STB0899_OFF0_TP_BUFFER24 0xf360
777#define STB0899_BASE_TP_BUFFER24 0x00000040
778#define STB0899_OFF0_TP_BUFFER25 0xf364
779#define STB0899_BASE_TP_BUFFER25 0x00000040
780#define STB0899_OFF0_TP_BUFFER26 0xf368
781#define STB0899_BASE_TP_BUFFER26 0x00000040
782#define STB0899_OFF0_TP_BUFFER27 0xf36c
783#define STB0899_BASE_TP_BUFFER27 0x00000040
784#define STB0899_OFF0_TP_BUFFER28 0xf370
785#define STB0899_BASE_TP_BUFFER28 0x00000040
786#define STB0899_OFF0_TP_BUFFER29 0xf374
787#define STB0899_BASE_TP_BUFFER29 0x00000040
788#define STB0899_OFF0_TP_BUFFER30 0xf378
789#define STB0899_BASE_TP_BUFFER30 0x00000040
790#define STB0899_OFF0_TP_BUFFER31 0xf37c
791#define STB0899_BASE_TP_BUFFER31 0x00000040
792#define STB0899_OFF0_TP_BUFFER32 0xf300
793#define STB0899_BASE_TP_BUFFER32 0x00000060
794#define STB0899_OFF0_TP_BUFFER33 0xf304
795#define STB0899_BASE_TP_BUFFER33 0x00000060
796#define STB0899_OFF0_TP_BUFFER34 0xf308
797#define STB0899_BASE_TP_BUFFER34 0x00000060
798#define STB0899_OFF0_TP_BUFFER35 0xf30c
799#define STB0899_BASE_TP_BUFFER35 0x00000060
800#define STB0899_OFF0_TP_BUFFER36 0xf310
801#define STB0899_BASE_TP_BUFFER36 0x00000060
802#define STB0899_OFF0_TP_BUFFER37 0xf314
803#define STB0899_BASE_TP_BUFFER37 0x00000060
804#define STB0899_OFF0_TP_BUFFER38 0xf318
805#define STB0899_BASE_TP_BUFFER38 0x00000060
806#define STB0899_OFF0_TP_BUFFER39 0xf31c
807#define STB0899_BASE_TP_BUFFER39 0x00000060
808#define STB0899_OFF0_TP_BUFFER40 0xf320
809#define STB0899_BASE_TP_BUFFER40 0x00000060
810#define STB0899_OFF0_TP_BUFFER41 0xf324
811#define STB0899_BASE_TP_BUFFER41 0x00000060
812#define STB0899_OFF0_TP_BUFFER42 0xf328
813#define STB0899_BASE_TP_BUFFER42 0x00000060
814#define STB0899_OFF0_TP_BUFFER43 0xf32c
815#define STB0899_BASE_TP_BUFFER43 0x00000060
816#define STB0899_OFF0_TP_BUFFER44 0xf330
817#define STB0899_BASE_TP_BUFFER44 0x00000060
818#define STB0899_OFF0_TP_BUFFER45 0xf334
819#define STB0899_BASE_TP_BUFFER45 0x00000060
820#define STB0899_OFF0_TP_BUFFER46 0xf338
821#define STB0899_BASE_TP_BUFFER46 0x00000060
822#define STB0899_OFF0_TP_BUFFER47 0xf33c
823#define STB0899_BASE_TP_BUFFER47 0x00000060
824#define STB0899_OFF0_TP_BUFFER48 0xf340
825#define STB0899_BASE_TP_BUFFER48 0x00000060
826#define STB0899_OFF0_TP_BUFFER49 0xf344
827#define STB0899_BASE_TP_BUFFER49 0x00000060
828#define STB0899_OFF0_TP_BUFFER50 0xf348
829#define STB0899_BASE_TP_BUFFER50 0x00000060
830#define STB0899_OFF0_TP_BUFFER51 0xf34c
831#define STB0899_BASE_TP_BUFFER51 0x00000060
832#define STB0899_OFF0_TP_BUFFER52 0xf350
833#define STB0899_BASE_TP_BUFFER52 0x00000060
834#define STB0899_OFF0_TP_BUFFER53 0xf354
835#define STB0899_BASE_TP_BUFFER53 0x00000060
836#define STB0899_OFF0_TP_BUFFER54 0xf358
837#define STB0899_BASE_TP_BUFFER54 0x00000060
838#define STB0899_OFF0_TP_BUFFER55 0xf35c
839#define STB0899_BASE_TP_BUFFER55 0x00000060
840#define STB0899_OFF0_TP_BUFFER56 0xf360
841#define STB0899_BASE_TP_BUFFER56 0x00000060
842#define STB0899_OFF0_TP_BUFFER57 0xf364
843#define STB0899_BASE_TP_BUFFER57 0x00000060
844#define STB0899_OFF0_TP_BUFFER58 0xf368
845#define STB0899_BASE_TP_BUFFER58 0x00000060
846#define STB0899_OFF0_TP_BUFFER59 0xf36c
847#define STB0899_BASE_TP_BUFFER59 0x00000060
848#define STB0899_OFF0_TP_BUFFER60 0xf370
849#define STB0899_BASE_TP_BUFFER60 0x00000060
850#define STB0899_OFF0_TP_BUFFER61 0xf374
851#define STB0899_BASE_TP_BUFFER61 0x00000060
852#define STB0899_OFF0_TP_BUFFER62 0xf378
853#define STB0899_BASE_TP_BUFFER62 0x00000060
854#define STB0899_OFF0_TP_BUFFER63 0xf37c
855#define STB0899_BASE_TP_BUFFER63 0x00000060
856
857#define STB0899_OFF0_RESET_CNTRL 0xf300
858#define STB0899_BASE_RESET_CNTRL 0x00000400
859#define STB0899_DVBS2_RESET (0x01 << 0)
860#define STB0899_OFFST_DVBS2_RESET 0
861#define STB0899_WIDTH_DVBS2_RESET 1
862
863#define STB0899_OFF0_ACM_ENABLE 0xf304
864#define STB0899_BASE_ACM_ENABLE 0x00000400
865#define STB0899_ACM_ENABLE 1
866
867#define STB0899_OFF0_DESCR_CNTRL 0xf30c
868#define STB0899_BASE_DESCR_CNTRL 0x00000400
869#define STB0899_OFFST_DESCR_CNTRL 0
870#define STB0899_WIDTH_DESCR_CNTRL 16
871
872#define STB0899_OFF0_UWP_CNTRL1 0xf320
873#define STB0899_BASE_UWP_CNTRL1 0x00000400
874#define STB0899_UWP_TH_SOF (0x7fff << 11)
875#define STB0899_OFFST_UWP_TH_SOF 11
876#define STB0899_WIDTH_UWP_TH_SOF 15
877#define STB0899_UWP_ESN0_QUANT (0xff << 3)
878#define STB0899_OFFST_UWP_ESN0_QUANT 3
879#define STB0899_WIDTH_UWP_ESN0_QUANT 8
880#define STB0899_UWP_ESN0_AVE (0x03 << 1)
881#define STB0899_OFFST_UWP_ESN0_AVE 1
882#define STB0899_WIDTH_UWP_ESN0_AVE 2
883#define STB0899_UWP_START (0x01 << 0)
884#define STB0899_OFFST_UWP_START 0
885#define STB0899_WIDTH_UWP_START 1
886
887#define STB0899_OFF0_UWP_CNTRL2 0xf324
888#define STB0899_BASE_UWP_CNTRL2 0x00000400
889#define STB0899_UWP_MISS_TH (0xff << 16)
890#define STB0899_OFFST_UWP_MISS_TH 16
891#define STB0899_WIDTH_UWP_MISS_TH 8
892#define STB0899_FE_FINE_TRK (0xff << 8)
893#define STB0899_OFFST_FE_FINE_TRK 8
894#define STB0899_WIDTH_FE_FINE_TRK 8
895#define STB0899_FE_COARSE_TRK (0xff << 0)
896#define STB0899_OFFST_FE_COARSE_TRK 0
897#define STB0899_WIDTH_FE_COARSE_TRK 8
898
899#define STB0899_OFF0_UWP_STAT1 0xf328
900#define STB0899_BASE_UWP_STAT1 0x00000400
901#define STB0899_UWP_STATE (0x03ff << 15)
902#define STB0899_OFFST_UWP_STATE 15
903#define STB0899_WIDTH_UWP_STATE 10
904#define STB0899_UW_MAX_PEAK (0x7fff << 0)
905#define STB0899_OFFST_UW_MAX_PEAK 0
906#define STB0899_WIDTH_UW_MAX_PEAK 15
907
908#define STB0899_OFF0_UWP_STAT2 0xf32c
909#define STB0899_BASE_UWP_STAT2 0x00000400
910#define STB0899_ESNO_EST (0x07ffff << 7)
911#define STB0899_OFFST_ESN0_EST 7
912#define STB0899_WIDTH_ESN0_EST 19
913#define STB0899_UWP_DECODE_MOD (0x7f << 0)
914#define STB0899_OFFST_UWP_DECODE_MOD 0
915#define STB0899_WIDTH_UWP_DECODE_MOD 7
916
917#define STB0899_OFF0_DMD_CORE_ID 0xf334
918#define STB0899_BASE_DMD_CORE_ID 0x00000400
919#define STB0899_CORE_ID (0xffffffff << 0)
920#define STB0899_OFFST_CORE_ID 0
921#define STB0899_WIDTH_CORE_ID 32
922
923#define STB0899_OFF0_DMD_VERSION_ID 0xf33c
924#define STB0899_BASE_DMD_VERSION_ID 0x00000400
925#define STB0899_VERSION_ID (0xff << 0)
926#define STB0899_OFFST_VERSION_ID 0
927#define STB0899_WIDTH_VERSION_ID 8
928
929#define STB0899_OFF0_DMD_STAT2 0xf340
930#define STB0899_BASE_DMD_STAT2 0x00000400
931#define STB0899_CSM_LOCK (0x01 << 1)
932#define STB0899_OFFST_CSM_LOCK 1
933#define STB0899_WIDTH_CSM_LOCK 1
934#define STB0899_UWP_LOCK (0x01 << 0)
935#define STB0899_OFFST_UWP_LOCK 0
936#define STB0899_WIDTH_UWP_LOCK 1
937
938#define STB0899_OFF0_FREQ_ADJ_SCALE 0xf344
939#define STB0899_BASE_FREQ_ADJ_SCALE 0x00000400
940#define STB0899_FREQ_ADJ_SCALE (0x0fff << 0)
941#define STB0899_OFFST_FREQ_ADJ_SCALE 0
942#define STB0899_WIDTH_FREQ_ADJ_SCALE 12
943
944#define STB0899_OFF0_UWP_CNTRL3 0xf34c
945#define STB0899_BASE_UWP_CNTRL3 0x00000400
946#define STB0899_UWP_TH_TRACK (0x7fff << 15)
947#define STB0899_OFFST_UWP_TH_TRACK 15
948#define STB0899_WIDTH_UWP_TH_TRACK 15
949#define STB0899_UWP_TH_ACQ (0x7fff << 0)
950#define STB0899_OFFST_UWP_TH_ACQ 0
951#define STB0899_WIDTH_UWP_TH_ACQ 15
952
953#define STB0899_OFF0_SYM_CLK_SEL 0xf350
954#define STB0899_BASE_SYM_CLK_SEL 0x00000400
955#define STB0899_SYM_CLK_SEL (0x03 << 0)
956#define STB0899_OFFST_SYM_CLK_SEL 0
957#define STB0899_WIDTH_SYM_CLK_SEL 2
958
959#define STB0899_OFF0_SOF_SRCH_TO 0xf354
960#define STB0899_BASE_SOF_SRCH_TO 0x00000400
961#define STB0899_SOF_SEARCH_TIMEOUT (0x3fffff << 0)
962#define STB0899_OFFST_SOF_SEARCH_TIMEOUT 0
963#define STB0899_WIDTH_SOF_SEARCH_TIMEOUT 22
964
965#define STB0899_OFF0_ACQ_CNTRL1 0xf358
966#define STB0899_BASE_ACQ_CNTRL1 0x00000400
967#define STB0899_FE_FINE_ACQ (0xff << 8)
968#define STB0899_OFFST_FE_FINE_ACQ 8
969#define STB0899_WIDTH_FE_FINE_ACQ 8
970#define STB0899_FE_COARSE_ACQ (0xff << 0)
971#define STB0899_OFFST_FE_COARSE_ACQ 0
972#define STB0899_WIDTH_FE_COARSE_ACQ 8
973
974#define STB0899_OFF0_ACQ_CNTRL2 0xf35c
975#define STB0899_BASE_ACQ_CNTRL2 0x00000400
976#define STB0899_ZIGZAG (0x01 << 25)
977#define STB0899_OFFST_ZIGZAG 25
978#define STB0899_WIDTH_ZIGZAG 1
979#define STB0899_NUM_STEPS (0xff << 17)
980#define STB0899_OFFST_NUM_STEPS 17
981#define STB0899_WIDTH_NUM_STEPS 8
982#define STB0899_FREQ_STEPSIZE (0x1ffff << 0)
983#define STB0899_OFFST_FREQ_STEPSIZE 0
984#define STB0899_WIDTH_FREQ_STEPSIZE 17
985
986#define STB0899_OFF0_ACQ_CNTRL3 0xf360
987#define STB0899_BASE_ACQ_CNTRL3 0x00000400
988#define STB0899_THRESHOLD_SCL (0x3f << 23)
989#define STB0899_OFFST_THRESHOLD_SCL 23
990#define STB0899_WIDTH_THRESHOLD_SCL 6
991#define STB0899_UWP_TH_SRCH (0x7fff << 8)
992#define STB0899_OFFST_UWP_TH_SRCH 8
993#define STB0899_WIDTH_UWP_TH_SRCH 15
994#define STB0899_AUTO_REACQUIRE (0x01 << 7)
995#define STB0899_OFFST_AUTO_REACQUIRE 7
996#define STB0899_WIDTH_AUTO_REACQUIRE 1
997#define STB0899_TRACK_LOCK_SEL (0x01 << 6)
998#define STB0899_OFFST_TRACK_LOCK_SEL 6
999#define STB0899_WIDTH_TRACK_LOCK_SEL 1
1000#define STB0899_ACQ_SEARCH_MODE (0x03 << 4)
1001#define STB0899_OFFST_ACQ_SEARCH_MODE 4
1002#define STB0899_WIDTH_ACQ_SEARCH_MODE 2
1003#define STB0899_CONFIRM_FRAMES (0x0f << 0)
1004#define STB0899_OFFST_CONFIRM_FRAMES 0
1005#define STB0899_WIDTH_CONFIRM_FRAMES 4
1006
1007#define STB0899_OFF0_FE_SETTLE 0xf364
1008#define STB0899_BASE_FE_SETTLE 0x00000400
1009#define STB0899_SETTLING_TIME (0x3fffff << 0)
1010#define STB0899_OFFST_SETTLING_TIME 0
1011#define STB0899_WIDTH_SETTLING_TIME 22
1012
1013#define STB0899_OFF0_AC_DWELL 0xf368
1014#define STB0899_BASE_AC_DWELL 0x00000400
1015#define STB0899_DWELL_TIME (0x3fffff << 0)
1016#define STB0899_OFFST_DWELL_TIME 0
1017#define STB0899_WIDTH_DWELL_TIME 22
1018
1019#define STB0899_OFF0_ACQUIRE_TRIG 0xf36c
1020#define STB0899_BASE_ACQUIRE_TRIG 0x00000400
1021#define STB0899_ACQUIRE (0x01 << 0)
1022#define STB0899_OFFST_ACQUIRE 0
1023#define STB0899_WIDTH_ACQUIRE 1
1024
1025#define STB0899_OFF0_LOCK_LOST 0xf370
1026#define STB0899_BASE_LOCK_LOST 0x00000400
1027#define STB0899_LOCK_LOST (0x01 << 0)
1028#define STB0899_OFFST_LOCK_LOST 0
1029#define STB0899_WIDTH_LOCK_LOST 1
1030
1031#define STB0899_OFF0_ACQ_STAT1 0xf374
1032#define STB0899_BASE_ACQ_STAT1 0x00000400
1033#define STB0899_STEP_FREQ (0x1fffff << 11)
1034#define STB0899_OFFST_STEP_FREQ 11
1035#define STB0899_WIDTH_STEP_FREQ 21
1036#define STB0899_ACQ_STATE (0x07 << 8)
1037#define STB0899_OFFST_ACQ_STATE 8
1038#define STB0899_WIDTH_ACQ_STATE 3
1039#define STB0899_UW_DETECT_COUNT (0xff << 0)
1040#define STB0899_OFFST_UW_DETECT_COUNT 0
1041#define STB0899_WIDTH_UW_DETECT_COUNT 8
1042
1043#define STB0899_OFF0_ACQ_TIMEOUT 0xf378
1044#define STB0899_BASE_ACQ_TIMEOUT 0x00000400
1045#define STB0899_ACQ_TIMEOUT (0x3fffff << 0)
1046#define STB0899_OFFST_ACQ_TIMEOUT 0
1047#define STB0899_WIDTH_ACQ_TIMEOUT 22
1048
1049#define STB0899_OFF0_ACQ_TIME 0xf37c
1050#define STB0899_BASE_ACQ_TIME 0x00000400
1051#define STB0899_ACQ_TIME_SYM (0xffffff << 0)
1052#define STB0899_OFFST_ACQ_TIME_SYM 0
1053#define STB0899_WIDTH_ACQ_TIME_SYM 24
1054
1055#define STB0899_OFF0_FINAL_AGC_CNTRL 0xf308
1056#define STB0899_BASE_FINAL_AGC_CNTRL 0x00000440
1057#define STB0899_FINAL_GAIN_INIT (0x3fff << 12)
1058#define STB0899_OFFST_FINAL_GAIN_INIT 12
1059#define STB0899_WIDTH_FINAL_GAIN_INIT 14
1060#define STB0899_FINAL_LOOP_GAIN (0x0f << 8)
1061#define STB0899_OFFST_FINAL_LOOP_GAIN 8
1062#define STB0899_WIDTH_FINAL_LOOP_GAIN 4
1063#define STB0899_FINAL_LD_GAIN_INIT (0x01 << 7)
1064#define STB0899_OFFST_FINAL_LD_GAIN_INIT 7
1065#define STB0899_WIDTH_FINAL_LD_GAIN_INIT 1
1066#define STB0899_FINAL_AGC_REF (0x7f << 0)
1067#define STB0899_OFFST_FINAL_AGC_REF 0
1068#define STB0899_WIDTH_FINAL_AGC_REF 7
1069
1070#define STB0899_OFF0_FINAL_AGC_GAIN 0xf30c
1071#define STB0899_BASE_FINAL_AGC_GAIN 0x00000440
1072#define STB0899_FINAL_AGC_GAIN (0x3fff << 0)
1073#define STB0899_OFFST_FINAL_AGC_GAIN 0
1074#define STB0899_WIDTH_FINAL_AGC_GAIN 14
1075
1076#define STB0899_OFF0_EQUALIZER_INIT 0xf310
1077#define STB0899_BASE_EQUALIZER_INIT 0x00000440
1078#define STB0899_EQ_SRST (0x01 << 1)
1079#define STB0899_OFFST_EQ_SRST 1
1080#define STB0899_WIDTH_EQ_SRST 1
1081#define STB0899_EQ_INIT (0x01 << 0)
1082#define STB0899_OFFST_EQ_INIT 0
1083#define STB0899_WIDTH_EQ_INIT 1
1084
1085#define STB0899_OFF0_EQ_CNTRL 0xf314
1086#define STB0899_BASE_EQ_CNTRL 0x00000440
1087#define STB0899_EQ_ADAPT_MODE (0x01 << 18)
1088#define STB0899_OFFST_EQ_ADAPT_MODE 18
1089#define STB0899_WIDTH_EQ_ADAPT_MODE 1
1090#define STB0899_EQ_DELAY (0x0f << 14)
1091#define STB0899_OFFST_EQ_DELAY 14
1092#define STB0899_WIDTH_EQ_DELAY 4
1093#define STB0899_EQ_QUANT_LEVEL (0xff << 6)
1094#define STB0899_OFFST_EQ_QUANT_LEVEL 6
1095#define STB0899_WIDTH_EQ_QUANT_LEVEL 8
1096#define STB0899_EQ_DISABLE_UPDATE (0x01 << 5)
1097#define STB0899_OFFST_EQ_DISABLE_UPDATE 5
1098#define STB0899_WIDTH_EQ_DISABLE_UPDATE 1
1099#define STB0899_EQ_BYPASS (0x01 << 4)
1100#define STB0899_OFFST_EQ_BYPASS 4
1101#define STB0899_WIDTH_EQ_BYPASS 1
1102#define STB0899_EQ_SHIFT (0x0f << 0)
1103#define STB0899_OFFST_EQ_SHIFT 0
1104#define STB0899_WIDTH_EQ_SHIFT 4
1105
1106#define STB0899_OFF0_EQ_I_INIT_COEFF_0 0xf320
1107#define STB0899_OFF1_EQ_I_INIT_COEFF_1 0xf324
1108#define STB0899_OFF2_EQ_I_INIT_COEFF_2 0xf328
1109#define STB0899_OFF3_EQ_I_INIT_COEFF_3 0xf32c
1110#define STB0899_OFF4_EQ_I_INIT_COEFF_4 0xf330
1111#define STB0899_OFF5_EQ_I_INIT_COEFF_5 0xf334
1112#define STB0899_OFF6_EQ_I_INIT_COEFF_6 0xf338
1113#define STB0899_OFF7_EQ_I_INIT_COEFF_7 0xf33c
1114#define STB0899_OFF8_EQ_I_INIT_COEFF_8 0xf340
1115#define STB0899_OFF9_EQ_I_INIT_COEFF_9 0xf344
1116#define STB0899_OFFa_EQ_I_INIT_COEFF_10 0xf348
1117#define STB0899_BASE_EQ_I_INIT_COEFF_N 0x00000440
1118#define STB0899_EQ_I_INIT_COEFF_N (0x0fff << 0)
1119#define STB0899_OFFST_EQ_I_INIT_COEFF_N 0
1120#define STB0899_WIDTH_EQ_I_INIT_COEFF_N 12
1121
1122#define STB0899_OFF0_EQ_Q_INIT_COEFF_0 0xf350
1123#define STB0899_OFF1_EQ_Q_INIT_COEFF_1 0xf354
1124#define STB0899_OFF2_EQ_Q_INIT_COEFF_2 0xf358
1125#define STB0899_OFF3_EQ_Q_INIT_COEFF_3 0xf35c
1126#define STB0899_OFF4_EQ_Q_INIT_COEFF_4 0xf360
1127#define STB0899_OFF5_EQ_Q_INIT_COEFF_5 0xf364
1128#define STB0899_OFF6_EQ_Q_INIT_COEFF_6 0xf368
1129#define STB0899_OFF7_EQ_Q_INIT_COEFF_7 0xf36c
1130#define STB0899_OFF8_EQ_Q_INIT_COEFF_8 0xf370
1131#define STB0899_OFF9_EQ_Q_INIT_COEFF_9 0xf374
1132#define STB0899_OFFa_EQ_Q_INIT_COEFF_10 0xf378
1133#define STB0899_BASE_EQ_Q_INIT_COEFF_N 0x00000440
1134#define STB0899_EQ_Q_INIT_COEFF_N (0x0fff << 0)
1135#define STB0899_OFFST_EQ_Q_INIT_COEFF_N 0
1136#define STB0899_WIDTH_EQ_Q_INIT_COEFF_N 12
1137
1138#define STB0899_OFF0_EQ_I_OUT_COEFF_0 0xf300
1139#define STB0899_OFF1_EQ_I_OUT_COEFF_1 0xf304
1140#define STB0899_OFF2_EQ_I_OUT_COEFF_2 0xf308
1141#define STB0899_OFF3_EQ_I_OUT_COEFF_3 0xf30c
1142#define STB0899_OFF4_EQ_I_OUT_COEFF_4 0xf310
1143#define STB0899_OFF5_EQ_I_OUT_COEFF_5 0xf314
1144#define STB0899_OFF6_EQ_I_OUT_COEFF_6 0xf318
1145#define STB0899_OFF7_EQ_I_OUT_COEFF_7 0xf31c
1146#define STB0899_OFF8_EQ_I_OUT_COEFF_8 0xf320
1147#define STB0899_OFF9_EQ_I_OUT_COEFF_9 0xf324
1148#define STB0899_OFFa_EQ_I_OUT_COEFF_10 0xf328
1149#define STB0899_BASE_EQ_I_OUT_COEFF_N 0x00000460
1150#define STB0899_EQ_I_OUT_COEFF_N (0x0fff << 0)
1151#define STB0899_OFFST_EQ_I_OUT_COEFF_N 0
1152#define STB0899_WIDTH_EQ_I_OUT_COEFF_N 12
1153
1154#define STB0899_OFF0_EQ_Q_OUT_COEFF_0 0xf330
1155#define STB0899_OFF1_EQ_Q_OUT_COEFF_1 0xf334
1156#define STB0899_OFF2_EQ_Q_OUT_COEFF_2 0xf338
1157#define STB0899_OFF3_EQ_Q_OUT_COEFF_3 0xf33c
1158#define STB0899_OFF4_EQ_Q_OUT_COEFF_4 0xf340
1159#define STB0899_OFF5_EQ_Q_OUT_COEFF_5 0xf344
1160#define STB0899_OFF6_EQ_Q_OUT_COEFF_6 0xf348
1161#define STB0899_OFF7_EQ_Q_OUT_COEFF_7 0xf34c
1162#define STB0899_OFF8_EQ_Q_OUT_COEFF_8 0xf350
1163#define STB0899_OFF9_EQ_Q_OUT_COEFF_9 0xf354
1164#define STB0899_OFFa_EQ_Q_OUT_COEFF_10 0xf358
1165#define STB0899_BASE_EQ_Q_OUT_COEFF_N 0x00000460
1166#define STB0899_EQ_Q_OUT_COEFF_N (0x0fff << 0)
1167#define STB0899_OFFST_EQ_Q_OUT_COEFF_N 0
1168#define STB0899_WIDTH_EQ_Q_OUT_COEFF_N 12
1169
1170/* S2 FEC */
1171#define STB0899_OFF0_BLOCK_LNGTH 0xfa04
1172#define STB0899_BASE_BLOCK_LNGTH 0x00000000
1173#define STB0899_BLOCK_LENGTH (0xff << 0)
1174#define STB0899_OFFST_BLOCK_LENGTH 0
1175#define STB0899_WIDTH_BLOCK_LENGTH 8
1176
1177#define STB0899_OFF0_ROW_STR 0xfa08
1178#define STB0899_BASE_ROW_STR 0x00000000
1179#define STB0899_ROW_STRIDE (0xff << 0)
1180#define STB0899_OFFST_ROW_STRIDE 0
1181#define STB0899_WIDTH_ROW_STRIDE 8
1182
1183#define STB0899_OFF0_MAX_ITER 0xfa0c
1184#define STB0899_BASE_MAX_ITER 0x00000000
1185#define STB0899_MAX_ITERATIONS (0xff << 0)
1186#define STB0899_OFFST_MAX_ITERATIONS 0
1187#define STB0899_WIDTH_MAX_ITERATIONS 8
1188
1189#define STB0899_OFF0_BN_END_ADDR 0xfa10
1190#define STB0899_BASE_BN_END_ADDR 0x00000000
1191#define STB0899_BN_END_ADDR (0x0fff << 0)
1192#define STB0899_OFFST_BN_END_ADDR 0
1193#define STB0899_WIDTH_BN_END_ADDR 12
1194
1195#define STB0899_OFF0_CN_END_ADDR 0xfa14
1196#define STB0899_BASE_CN_END_ADDR 0x00000000
1197#define STB0899_CN_END_ADDR (0x0fff << 0)
1198#define STB0899_OFFST_CN_END_ADDR 0
1199#define STB0899_WIDTH_CN_END_ADDR 12
1200
1201#define STB0899_OFF0_INFO_LENGTH 0xfa1c
1202#define STB0899_BASE_INFO_LENGTH 0x00000000
1203#define STB0899_INFO_LENGTH (0xff << 0)
1204#define STB0899_OFFST_INFO_LENGTH 0
1205#define STB0899_WIDTH_INFO_LENGTH 8
1206
1207#define STB0899_OFF0_BOT_ADDR 0xfa20
1208#define STB0899_BASE_BOT_ADDR 0x00000000
1209#define STB0899_BOTTOM_BASE_ADDR (0x03ff << 0)
1210#define STB0899_OFFST_BOTTOM_BASE_ADDR 0
1211#define STB0899_WIDTH_BOTTOM_BASE_ADDR 10
1212
1213#define STB0899_OFF0_BCH_BLK_LN 0xfa24
1214#define STB0899_BASE_BCH_BLK_LN 0x00000000
1215#define STB0899_BCH_BLOCK_LENGTH (0xffff << 0)
1216#define STB0899_OFFST_BCH_BLOCK_LENGTH 0
1217#define STB0899_WIDTH_BCH_BLOCK_LENGTH 16
1218
1219#define STB0899_OFF0_BCH_T 0xfa28
1220#define STB0899_BASE_BCH_T 0x00000000
1221#define STB0899_BCH_T (0x0f << 0)
1222#define STB0899_OFFST_BCH_T 0
1223#define STB0899_WIDTH_BCH_T 4
1224
1225#define STB0899_OFF0_CNFG_MODE 0xfa00
1226#define STB0899_BASE_CNFG_MODE 0x00000800
1227#define STB0899_MODCOD (0x1f << 2)
1228#define STB0899_OFFST_MODCOD 2
1229#define STB0899_WIDTH_MODCOD 5
1230#define STB0899_MODCOD_SEL (0x01 << 1)
1231#define STB0899_OFFST_MODCOD_SEL 1
1232#define STB0899_WIDTH_MODCOD_SEL 1
1233#define STB0899_CONFIG_MODE (0x01 << 0)
1234#define STB0899_OFFST_CONFIG_MODE 0
1235#define STB0899_WIDTH_CONFIG_MODE 1
1236
1237#define STB0899_OFF0_LDPC_STAT 0xfa04
1238#define STB0899_BASE_LDPC_STAT 0x00000800
1239#define STB0899_ITERATION (0xff << 3)
1240#define STB0899_OFFST_ITERATION 3
1241#define STB0899_WIDTH_ITERATION 8
1242#define STB0899_LDPC_DEC_STATE (0x07 << 0)
1243#define STB0899_OFFST_LDPC_DEC_STATE 0
1244#define STB0899_WIDTH_LDPC_DEC_STATE 3
1245
1246#define STB0899_OFF0_ITER_SCALE 0xfa08
1247#define STB0899_BASE_ITER_SCALE 0x00000800
1248#define STB0899_ITERATION_SCALE (0xff << 0)
1249#define STB0899_OFFST_ITERATION_SCALE 0
1250#define STB0899_WIDTH_ITERATION_SCALE 8
1251
1252#define STB0899_OFF0_INPUT_MODE 0xfa0c
1253#define STB0899_BASE_INPUT_MODE 0x00000800
1254#define STB0899_SD_BLOCK1_STREAM0 (0x01 << 0)
1255#define STB0899_OFFST_SD_BLOCK1_STREAM0 0
1256#define STB0899_WIDTH_SD_BLOCK1_STREAM0 1
1257
1258#define STB0899_OFF0_LDPCDECRST 0xfa10
1259#define STB0899_BASE_LDPCDECRST 0x00000800
1260#define STB0899_LDPC_DEC_RST (0x01 << 0)
1261#define STB0899_OFFST_LDPC_DEC_RST 0
1262#define STB0899_WIDTH_LDPC_DEC_RST 1
1263
1264#define STB0899_OFF0_CLK_PER_BYTE_RW 0xfa14
1265#define STB0899_BASE_CLK_PER_BYTE_RW 0x00000800
1266#define STB0899_CLKS_PER_BYTE (0x0f << 0)
1267#define STB0899_OFFST_CLKS_PER_BYTE 0
1268#define STB0899_WIDTH_CLKS_PER_BYTE 5
1269
1270#define STB0899_OFF0_BCH_ERRORS 0xfa18
1271#define STB0899_BASE_BCH_ERRORS 0x00000800
1272#define STB0899_BCH_ERRORS (0x0f << 0)
1273#define STB0899_OFFST_BCH_ERRORS 0
1274#define STB0899_WIDTH_BCH_ERRORS 4
1275
1276#define STB0899_OFF0_LDPC_ERRORS 0xfa1c
1277#define STB0899_BASE_LDPC_ERRORS 0x00000800
1278#define STB0899_LDPC_ERRORS (0xffff << 0)
1279#define STB0899_OFFST_LDPC_ERRORS 0
1280#define STB0899_WIDTH_LDPC_ERRORS 16
1281
1282#define STB0899_OFF0_BCH_MODE 0xfa20
1283#define STB0899_BASE_BCH_MODE 0x00000800
1284#define STB0899_BCH_CORRECT_N (0x01 << 1)
1285#define STB0899_OFFST_BCH_CORRECT_N 1
1286#define STB0899_WIDTH_BCH_CORRECT_N 1
1287#define STB0899_FULL_BYPASS (0x01 << 0)
1288#define STB0899_OFFST_FULL_BYPASS 0
1289#define STB0899_WIDTH_FULL_BYPASS 1
1290
1291#define STB0899_OFF0_ERR_ACC_PER 0xfa24
1292#define STB0899_BASE_ERR_ACC_PER 0x00000800
1293#define STB0899_BCH_ERR_ACC_PERIOD (0x0f << 0)
1294#define STB0899_OFFST_BCH_ERR_ACC_PERIOD 0
1295#define STB0899_WIDTH_BCH_ERR_ACC_PERIOD 4
1296
1297#define STB0899_OFF0_BCH_ERR_ACC 0xfa28
1298#define STB0899_BASE_BCH_ERR_ACC 0x00000800
1299#define STB0899_BCH_ERR_ACCUM (0xff << 0)
1300#define STB0899_OFFST_BCH_ERR_ACCUM 0
1301#define STB0899_WIDTH_BCH_ERR_ACCUM 8
1302
1303#define STB0899_OFF0_FEC_CORE_ID_REG 0xfa2c
1304#define STB0899_BASE_FEC_CORE_ID_REG 0x00000800
1305#define STB0899_FEC_CORE_ID (0xffffffff << 0)
1306#define STB0899_OFFST_FEC_CORE_ID 0
1307#define STB0899_WIDTH_FEC_CORE_ID 32
1308
1309#define STB0899_OFF0_FEC_VER_ID_REG 0xfa34
1310#define STB0899_BASE_FEC_VER_ID_REG 0x00000800
1311#define STB0899_FEC_VER_ID (0xff << 0)
1312#define STB0899_OFFST_FEC_VER_ID 0
1313#define STB0899_WIDTH_FEC_VER_ID 8
1314
1315#define STB0899_OFF0_FEC_TP_SEL 0xfa38
1316#define STB0899_BASE_FEC_TP_SEL 0x00000800
1317
1318#define STB0899_OFF0_CSM_CNTRL1 0xf310
1319#define STB0899_BASE_CSM_CNTRL1 0x00000400
1320#define STB0899_CSM_FORCE_FREQLOCK (0x01 << 19)
1321#define STB0899_OFFST_CSM_FORCE_FREQLOCK 19
1322#define STB0899_WIDTH_CSM_FORCE_FREQLOCK 1
1323#define STB0899_CSM_FREQ_LOCKSTATE (0x01 << 18)
1324#define STB0899_OFFST_CSM_FREQ_LOCKSTATE 18
1325#define STB0899_WIDTH_CSM_FREQ_LOCKSTATE 1
1326#define STB0899_CSM_AUTO_PARAM (0x01 << 17)
1327#define STB0899_OFFST_CSM_AUTO_PARAM 17
1328#define STB0899_WIDTH_CSM_AUTO_PARAM 1
1329#define STB0899_FE_LOOP_SHIFT (0x07 << 14)
1330#define STB0899_OFFST_FE_LOOP_SHIFT 14
1331#define STB0899_WIDTH_FE_LOOP_SHIFT 3
1332#define STB0899_CSM_AGC_SHIFT (0x07 << 11)
1333#define STB0899_OFFST_CSM_AGC_SHIFT 11
1334#define STB0899_WIDTH_CSM_AGC_SHIFT 3
1335#define STB0899_CSM_AGC_GAIN (0x09 << 2)
1336#define STB0899_OFFST_CSM_AGC_GAIN 2
1337#define STB0899_WIDTH_CSM_AGC_GAIN 9
1338#define STB0899_CSM_TWO_PASS (0x01 << 1)
1339#define STB0899_OFFST_CSM_TWO_PASS 1
1340#define STB0899_WIDTH_CSM_TWO_PASS 1
1341#define STB0899_CSM_DVT_TABLE (0x01 << 0)
1342#define STB0899_OFFST_CSM_DVT_TABLE 0
1343#define STB0899_WIDTH_CSM_DVT_TABLE 1
1344
1345#define STB0899_OFF0_CSM_CNTRL2 0xf314
1346#define STB0899_BASE_CSM_CNTRL2 0x00000400
1347#define STB0899_CSM_GAMMA_RHO_ACQ (0x09 << 9)
1348#define STB0899_OFFST_CSM_GAMMA_RHOACQ 9
1349#define STB0899_WIDTH_CSM_GAMMA_RHOACQ 9
1350#define STB0899_CSM_GAMMA_ACQ (0x09 << 0)
1351#define STB0899_OFFST_CSM_GAMMA_ACQ 0
1352#define STB0899_WIDTH_CSM_GAMMA_ACQ 9
1353
1354#define STB0899_OFF0_CSM_CNTRL3 0xf320
1355#define STB0899_BASE_CSM_CNTRL3 0x00000400
1356#define STB0899_CSM_GAMMA_RHO_TRACK (0x09 << 9)
1357#define STB0899_OFFST_CSM_GAMMA_RHOTRACK 9
1358#define STB0899_WIDTH_CSM_GAMMA_RHOTRACK 9
1359#define STB0899_CSM_GAMMA_TRACK (0x09 << 0)
1360#define STB0899_OFFST_CSM_GAMMA_TRACK 0
1361#define STB0899_WIDTH_CSM_GAMMA_TRACK 9
1362
1363#define STB0899_OFF0_CSM_CNTRL4 0xf324
1364#define STB0899_BASE_CSM_CNTRL4 0x00000400
1365#define STB0899_CSM_PHASEDIFF_THRESH (0x0f << 8)
1366#define STB0899_OFFST_CSM_PHASEDIFF_THRESH 8
1367#define STB0899_WIDTH_CSM_PHASEDIFF_THRESH 4
1368#define STB0899_CSM_LOCKCOUNT_THRESH (0xff << 0)
1369#define STB0899_OFFST_CSM_LOCKCOUNT_THRESH 0
1370#define STB0899_WIDTH_CSM_LOCKCOUNT_THRESH 8
1371
1372/* Check on chapter 8 page 42 */
1373#define STB0899_ERRCTRL1 0xf574
1374#define STB0899_ERRCTRL2 0xf575
1375#define STB0899_ERRCTRL3 0xf576
1376#define STB0899_ERR_SRC_S1 (0x1f << 3)
1377#define STB0899_OFFST_ERR_SRC_S1 3
1378#define STB0899_WIDTH_ERR_SRC_S1 5
1379#define STB0899_ERR_SRC_S2 (0x0f << 0)
1380#define STB0899_OFFST_ERR_SRC_S2 0
1381#define STB0899_WIDTH_ERR_SRC_S2 4
1382#define STB0899_NOE (0x07 << 0)
1383#define STB0899_OFFST_NOE 0
1384#define STB0899_WIDTH_NOE 3
1385
1386#define STB0899_ECNT1M 0xf524
1387#define STB0899_ECNT1L 0xf525
1388#define STB0899_ECNT2M 0xf526
1389#define STB0899_ECNT2L 0xf527
1390#define STB0899_ECNT3M 0xf528
1391#define STB0899_ECNT3L 0xf529
1392
1393#define STB0899_DMONMSK1 0xf57b
1394#define STB0899_DMONMSK1_WAIT_1STEP (1 << 7)
1395#define STB0899_DMONMSK1_FREE_14 (1 << 6)
1396#define STB0899_DMONMSK1_AVRGVIT_CALC (1 << 5)
1397#define STB0899_DMONMSK1_FREE_12 (1 << 4)
1398#define STB0899_DMONMSK1_FREE_11 (1 << 3)
1399#define STB0899_DMONMSK1_B0DIV_CALC (1 << 2)
1400#define STB0899_DMONMSK1_KDIVB1_CALC (1 << 1)
1401#define STB0899_DMONMSK1_KDIVB2_CALC (1 << 0)
1402
1403#define STB0899_DMONMSK0 0xf57c
1404#define STB0899_DMONMSK0_SMOTTH_CALC (1 << 7)
1405#define STB0899_DMONMSK0_FREE_6 (1 << 6)
1406#define STB0899_DMONMSK0_SIGPOWER_CALC (1 << 5)
1407#define STB0899_DMONMSK0_QSEUIL_CALC (1 << 4)
1408#define STB0899_DMONMSK0_FREE_3 (1 << 3)
1409#define STB0899_DMONMSK0_FREE_2 (1 << 2)
1410#define STB0899_DMONMSK0_KVDIVB1_CALC (1 << 1)
1411#define STB0899_DMONMSK0_KVDIVB2_CALC (1 << 0)
1412
1413#define STB0899_TSULC 0xf549
1414#define STB0899_ULNOSYNCBYTES (0x01 << 7)
1415#define STB0899_OFFST_ULNOSYNCBYTES 7
1416#define STB0899_WIDTH_ULNOSYNCBYTES 1
1417#define STB0899_ULPARITY_ON (0x01 << 6)
1418#define STB0899_OFFST_ULPARITY_ON 6
1419#define STB0899_WIDTH_ULPARITY_ON 1
1420#define STB0899_ULSYNCOUTRS (0x01 << 5)
1421#define STB0899_OFFST_ULSYNCOUTRS 5
1422#define STB0899_WIDTH_ULSYNCOUTRS 1
1423#define STB0899_ULDSS_PACKETS (0x01 << 0)
1424#define STB0899_OFFST_ULDSS_PACKETS 0
1425#define STB0899_WIDTH_ULDSS_PACKETS 1
1426
1427#define STB0899_TSLPL 0xf54b
1428#define STB0899_LLDVBS2_MODE (0x01 << 4)
1429#define STB0899_OFFST_LLDVBS2_MODE 4
1430#define STB0899_WIDTH_LLDVBS2_MODE 1
1431#define STB0899_LLISSYI_ON (0x01 << 3)
1432#define STB0899_OFFST_LLISSYI_ON 3
1433#define STB0899_WIDTH_LLISSYI_ON 1
1434#define STB0899_LLNPD_ON (0x01 << 2)
1435#define STB0899_OFFST_LLNPD_ON 2
1436#define STB0899_WIDTH_LLNPD_ON 1
1437#define STB0899_LLCRC8_ON (0x01 << 1)
1438#define STB0899_OFFST_LLCRC8_ON 1
1439#define STB0899_WIDTH_LLCRC8_ON 1
1440
1441#define STB0899_TSCFGH 0xf54c
1442#define STB0899_OUTRS_PS (0x01 << 6)
1443#define STB0899_OFFST_OUTRS_PS 6
1444#define STB0899_WIDTH_OUTRS_PS 1
1445#define STB0899_SYNCBYTE (0x01 << 5)
1446#define STB0899_OFFST_SYNCBYTE 5
1447#define STB0899_WIDTH_SYNCBYTE 1
1448#define STB0899_PFBIT (0x01 << 4)
1449#define STB0899_OFFST_PFBIT 4
1450#define STB0899_WIDTH_PFBIT 1
1451#define STB0899_ERR_BIT (0x01 << 3)
1452#define STB0899_OFFST_ERR_BIT 3
1453#define STB0899_WIDTH_ERR_BIT 1
1454#define STB0899_MPEG (0x01 << 2)
1455#define STB0899_OFFST_MPEG 2
1456#define STB0899_WIDTH_MPEG 1
1457#define STB0899_CLK_POL (0x01 << 1)
1458#define STB0899_OFFST_CLK_POL 1
1459#define STB0899_WIDTH_CLK_POL 1
1460#define STB0899_FORCE0 (0x01 << 0)
1461#define STB0899_OFFST_FORCE0 0
1462#define STB0899_WIDTH_FORCE0 1
1463
1464#define STB0899_TSCFGM 0xf54d
1465#define STB0899_LLPRIORITY (0x01 << 3)
1466#define STB0899_OFFST_LLPRIORIY 3
1467#define STB0899_WIDTH_LLPRIORITY 1
1468#define STB0899_EN188 (0x01 << 2)
1469#define STB0899_OFFST_EN188 2
1470#define STB0899_WIDTH_EN188 1
1471
1472#define STB0899_TSCFGL 0xf54e
1473#define STB0899_DEL_ERRPCK (0x01 << 7)
1474#define STB0899_OFFST_DEL_ERRPCK 7
1475#define STB0899_WIDTH_DEL_ERRPCK 1
1476#define STB0899_ERRFLAGSTD (0x01 << 5)
1477#define STB0899_OFFST_ERRFLAGSTD 5
1478#define STB0899_WIDTH_ERRFLAGSTD 1
1479#define STB0899_MPEGERR (0x01 << 4)
1480#define STB0899_OFFST_MPEGERR 4
1481#define STB0899_WIDTH_MPEGERR 1
1482#define STB0899_BCH_CHK (0x01 << 3)
1483#define STB0899_OFFST_BCH_CHK 5
1484#define STB0899_WIDTH_BCH_CHK 1
1485#define STB0899_CRC8CHK (0x01 << 2)
1486#define STB0899_OFFST_CRC8CHK 2
1487#define STB0899_WIDTH_CRC8CHK 1
1488#define STB0899_SPEC_INFO (0x01 << 1)
1489#define STB0899_OFFST_SPEC_INFO 1
1490#define STB0899_WIDTH_SPEC_INFO 1
1491#define STB0899_LOW_PRIO_CLK (0x01 << 0)
1492#define STB0899_OFFST_LOW_PRIO_CLK 0
1493#define STB0899_WIDTH_LOW_PRIO_CLK 1
1494#define STB0899_ERROR_NORM (0x00 << 0)
1495#define STB0899_OFFST_ERROR_NORM 0
1496#define STB0899_WIDTH_ERROR_NORM 0
1497
1498#define STB0899_TSOUT 0xf54f
1499#define STB0899_RSSYNCDEL 0xf550
1500#define STB0899_TSINHDELH 0xf551
1501#define STB0899_TSINHDELM 0xf552
1502#define STB0899_TSINHDELL 0xf553
1503#define STB0899_TSLLSTKM 0xf55a
1504#define STB0899_TSLLSTKL 0xf55b
1505#define STB0899_TSULSTKM 0xf55c
1506#define STB0899_TSULSTKL 0xf55d
1507#define STB0899_TSSTATUS 0xf561
1508
1509#define STB0899_PDELCTRL 0xf600
1510#define STB0899_INVERT_RES (0x01 << 7)
1511#define STB0899_OFFST_INVERT_RES 7
1512#define STB0899_WIDTH_INVERT_RES 1
1513#define STB0899_FORCE_ACCEPTED (0x01 << 6)
1514#define STB0899_OFFST_FORCE_ACCEPTED 6
1515#define STB0899_WIDTH_FORCE_ACCEPTED 1
1516#define STB0899_FILTER_EN (0x01 << 5)
1517#define STB0899_OFFST_FILTER_EN 5
1518#define STB0899_WIDTH_FILTER_EN 1
1519#define STB0899_LOCKFALL_THRESH (0x01 << 4)
1520#define STB0899_OFFST_LOCKFALL_THRESH 4
1521#define STB0899_WIDTH_LOCKFALL_THRESH 1
1522#define STB0899_HYST_EN (0x01 << 3)
1523#define STB0899_OFFST_HYST_EN 3
1524#define STB0899_WIDTH_HYST_EN 1
1525#define STB0899_HYST_SWRST (0x01 << 2)
1526#define STB0899_OFFST_HYST_SWRST 2
1527#define STB0899_WIDTH_HYST_SWRST 1
1528#define STB0899_ALGO_EN (0x01 << 1)
1529#define STB0899_OFFST_ALGO_EN 1
1530#define STB0899_WIDTH_ALGO_EN 1
1531#define STB0899_ALGO_SWRST (0x01 << 0)
1532#define STB0899_OFFST_ALGO_SWRST 0
1533#define STB0899_WIDTH_ALGO_SWRST 1
1534
1535#define STB0899_PDELCTRL2 0xf601
1536#define STB0899_BBHCTRL1 0xf602
1537#define STB0899_BBHCTRL2 0xf603
1538#define STB0899_HYSTTHRESH 0xf604
1539
1540#define STB0899_MATCSTM 0xf605
1541#define STB0899_MATCSTL 0xf606
1542#define STB0899_UPLCSTM 0xf607
1543#define STB0899_UPLCSTL 0xf608
1544#define STB0899_DFLCSTM 0xf609
1545#define STB0899_DFLCSTL 0xf60a
1546#define STB0899_SYNCCST 0xf60b
1547#define STB0899_SYNCDCSTM 0xf60c
1548#define STB0899_SYNCDCSTL 0xf60d
1549#define STB0899_ISI_ENTRY 0xf60e
1550#define STB0899_ISI_BIT_EN 0xf60f
1551#define STB0899_MATSTRM 0xf610
1552#define STB0899_MATSTRL 0xf611
1553#define STB0899_UPLSTRM 0xf612
1554#define STB0899_UPLSTRL 0xf613
1555#define STB0899_DFLSTRM 0xf614
1556#define STB0899_DFLSTRL 0xf615
1557#define STB0899_SYNCSTR 0xf616
1558#define STB0899_SYNCDSTRM 0xf617
1559#define STB0899_SYNCDSTRL 0xf618
1560
1561#define STB0899_CFGPDELSTATUS1 0xf619
1562#define STB0899_BADDFL (0x01 << 6)
1563#define STB0899_OFFST_BADDFL 6
1564#define STB0899_WIDTH_BADDFL 1
1565#define STB0899_CONTINUOUS_STREAM (0x01 << 5)
1566#define STB0899_OFFST_CONTINUOUS_STREAM 5
1567#define STB0899_WIDTH_CONTINUOUS_STREAM 1
1568#define STB0899_ACCEPTED_STREAM (0x01 << 4)
1569#define STB0899_OFFST_ACCEPTED_STREAM 4
1570#define STB0899_WIDTH_ACCEPTED_STREAM 1
1571#define STB0899_BCH_ERRFLAG (0x01 << 3)
1572#define STB0899_OFFST_BCH_ERRFLAG 3
1573#define STB0899_WIDTH_BCH_ERRFLAG 1
1574#define STB0899_CRCRES (0x01 << 2)
1575#define STB0899_OFFST_CRCRES 2
1576#define STB0899_WIDTH_CRCRES 1
1577#define STB0899_CFGPDELSTATUS_LOCK (0x01 << 1)
1578#define STB0899_OFFST_CFGPDELSTATUS_LOCK 1
1579#define STB0899_WIDTH_CFGPDELSTATUS_LOCK 1
1580#define STB0899_1STLOCK (0x01 << 0)
1581#define STB0899_OFFST_1STLOCK 0
1582#define STB0899_WIDTH_1STLOCK 1
1583
1584#define STB0899_CFGPDELSTATUS2 0xf61a
1585#define STB0899_BBFERRORM 0xf61b
1586#define STB0899_BBFERRORL 0xf61c
1587#define STB0899_UPKTERRORM 0xf61d
1588#define STB0899_UPKTERRORL 0xf61e
1589
1590#define STB0899_TSTCK 0xff10
1591
1592#define STB0899_TSTRES 0xff11
1593#define STB0899_FRESLDPC (0x01 << 7)
1594#define STB0899_OFFST_FRESLDPC 7
1595#define STB0899_WIDTH_FRESLDPC 1
1596#define STB0899_FRESRS (0x01 << 6)
1597#define STB0899_OFFST_FRESRS 6
1598#define STB0899_WIDTH_FRESRS 1
1599#define STB0899_FRESVIT (0x01 << 5)
1600#define STB0899_OFFST_FRESVIT 5
1601#define STB0899_WIDTH_FRESVIT 1
1602#define STB0899_FRESMAS1_2 (0x01 << 4)
1603#define STB0899_OFFST_FRESMAS1_2 4
1604#define STB0899_WIDTH_FRESMAS1_2 1
1605#define STB0899_FRESACS (0x01 << 3)
1606#define STB0899_OFFST_FRESACS 3
1607#define STB0899_WIDTH_FRESACS 1
1608#define STB0899_FRESSYM (0x01 << 2)
1609#define STB0899_OFFST_FRESSYM 2
1610#define STB0899_WIDTH_FRESSYM 1
1611#define STB0899_FRESMAS (0x01 << 1)
1612#define STB0899_OFFST_FRESMAS 1
1613#define STB0899_WIDTH_FRESMAS 1
1614#define STB0899_FRESINT (0x01 << 0)
1615#define STB0899_OFFST_FRESINIT 0
1616#define STB0899_WIDTH_FRESINIT 1
1617
1618#define STB0899_TSTOUT 0xff12
1619#define STB0899_EN_SIGNATURE (0x01 << 7)
1620#define STB0899_OFFST_EN_SIGNATURE 7
1621#define STB0899_WIDTH_EN_SIGNATURE 1
1622#define STB0899_BCLK_CLK (0x01 << 6)
1623#define STB0899_OFFST_BCLK_CLK 6
1624#define STB0899_WIDTH_BCLK_CLK 1
1625#define STB0899_SGNL_OUT (0x01 << 5)
1626#define STB0899_OFFST_SGNL_OUT 5
1627#define STB0899_WIDTH_SGNL_OUT 1
1628#define STB0899_TS (0x01 << 4)
1629#define STB0899_OFFST_TS 4
1630#define STB0899_WIDTH_TS 1
1631#define STB0899_CTEST (0x01 << 0)
1632#define STB0899_OFFST_CTEST 0
1633#define STB0899_WIDTH_CTEST 1
1634
1635#define STB0899_TSTIN 0xff13
1636#define STB0899_TEST_IN (0x01 << 7)
1637#define STB0899_OFFST_TEST_IN 7
1638#define STB0899_WIDTH_TEST_IN 1
1639#define STB0899_EN_ADC (0x01 << 6)
1640#define STB0899_OFFST_EN_ADC 6
1641#define STB0899_WIDTH_ENADC 1
1642#define STB0899_SGN_ADC (0x01 << 5)
1643#define STB0899_OFFST_SGN_ADC 5
1644#define STB0899_WIDTH_SGN_ADC 1
1645#define STB0899_BCLK_IN (0x01 << 4)
1646#define STB0899_OFFST_BCLK_IN 4
1647#define STB0899_WIDTH_BCLK_IN 1
1648#define STB0899_JETONIN_MODE (0x01 << 3)
1649#define STB0899_OFFST_JETONIN_MODE 3
1650#define STB0899_WIDTH_JETONIN_MODE 1
1651#define STB0899_BCLK_VALUE (0x01 << 2)
1652#define STB0899_OFFST_BCLK_VALUE 2
1653#define STB0899_WIDTH_BCLK_VALUE 1
1654#define STB0899_SGNRST_T12 (0x01 << 1)
1655#define STB0899_OFFST_SGNRST_T12 1
1656#define STB0899_WIDTH_SGNRST_T12 1
1657#define STB0899_LOWSP_ENAX (0x01 << 0)
1658#define STB0899_OFFST_LOWSP_ENAX 0
1659#define STB0899_WIDTH_LOWSP_ENAX 1
1660
1661#define STB0899_TSTSYS 0xff14
1662#define STB0899_TSTCHIP 0xff15
1663#define STB0899_TSTFREE 0xff16
1664#define STB0899_TSTI2C 0xff17
1665#define STB0899_BITSPEEDM 0xff1c
1666#define STB0899_BITSPEEDL 0xff1d
1667#define STB0899_TBUSBIT 0xff1e
1668#define STB0899_TSTDIS 0xff24
1669#define STB0899_TSTDISRX 0xff25
1670#define STB0899_TSTJETON 0xff28
1671#define STB0899_TSTDCADJ 0xff40
1672#define STB0899_TSTAGC1 0xff41
1673#define STB0899_TSTAGC1N 0xff42
1674#define STB0899_TSTPOLYPH 0xff48
1675#define STB0899_TSTR 0xff49
1676#define STB0899_TSTAGC2 0xff4a
1677#define STB0899_TSTCTL1 0xff4b
1678#define STB0899_TSTCTL2 0xff4c
1679#define STB0899_TSTCTL3 0xff4d
1680#define STB0899_TSTDEMAP 0xff50
1681#define STB0899_TSTDEMAP2 0xff51
1682#define STB0899_TSTDEMMON 0xff52
1683#define STB0899_TSTRATE 0xff53
1684#define STB0899_TSTSELOUT 0xff54
1685#define STB0899_TSYNC 0xff55
1686#define STB0899_TSTERR 0xff56
1687#define STB0899_TSTRAM1 0xff58
1688#define STB0899_TSTVSELOUT 0xff59
1689#define STB0899_TSTFORCEIN 0xff5a
1690#define STB0899_TSTRS1 0xff5c
1691#define STB0899_TSTRS2 0xff5d
1692#define STB0899_TSTRS3 0xff53
1693
1694#define STB0899_INTBUFSTATUS 0xf200
1695#define STB0899_INTBUFCTRL 0xf201
1696#define STB0899_PCKLENUL 0xf55e
1697#define STB0899_PCKLENLL 0xf55f
1698#define STB0899_RSPCKLEN 0xf560
1699
1700/* 2 registers */
1701#define STB0899_SYNCDCST 0xf60c
1702
1703/* DiSEqC */
1704#define STB0899_DISCNTRL1 0xf0a0
1705#define STB0899_TIMOFF (0x01 << 7)
1706#define STB0899_OFFST_TIMOFF 7
1707#define STB0899_WIDTH_TIMOFF 1
1708#define STB0899_DISEQCRESET (0x01 << 6)
1709#define STB0899_OFFST_DISEQCRESET 6
1710#define STB0899_WIDTH_DISEQCRESET 1
1711#define STB0899_TIMCMD (0x03 << 4)
1712#define STB0899_OFFST_TIMCMD 4
1713#define STB0899_WIDTH_TIMCMD 2
1714#define STB0899_DISPRECHARGE (0x01 << 2)
1715#define STB0899_OFFST_DISPRECHARGE 2
1716#define STB0899_WIDTH_DISPRECHARGE 1
1717#define STB0899_DISEQCMODE (0x01 << 0)
1718#define STB0899_OFFST_DISEQCMODE 0
1719#define STB0899_WIDTH_DISEQCMODE 2
1720
1721#define STB0899_DISCNTRL2 0xf0a1
1722#define STB0899_RECEIVER_ON (0x01 << 7)
1723#define STB0899_OFFST_RECEIVER_ON 7
1724#define STB0899_WIDTH_RECEIVER_ON 1
1725#define STB0899_IGNO_SHORT_22K (0x01 << 6)
1726#define STB0899_OFFST_IGNO_SHORT_22K 6
1727#define STB0899_WIDTH_IGNO_SHORT_22K 1
1728#define STB0899_ONECHIP_TRX (0x01 << 5)
1729#define STB0899_OFFST_ONECHIP_TRX 5
1730#define STB0899_WIDTH_ONECHIP_TRX 1
1731#define STB0899_EXT_ENVELOP (0x01 << 4)
1732#define STB0899_OFFST_EXT_ENVELOP 4
1733#define STB0899_WIDTH_EXT_ENVELOP 1
1734#define STB0899_PIN_SELECT (0x03 << 2)
1735#define STB0899_OFFST_PIN_SELCT 2
1736#define STB0899_WIDTH_PIN_SELCT 2
1737#define STB0899_IRQ_RXEND (0x01 << 1)
1738#define STB0899_OFFST_IRQ_RXEND 1
1739#define STB0899_WIDTH_IRQ_RXEND 1
1740#define STB0899_IRQ_4NBYTES (0x01 << 0)
1741#define STB0899_OFFST_IRQ_4NBYTES 0
1742#define STB0899_WIDTH_IRQ_4NBYTES 1
1743
1744#define STB0899_DISRX_ST0 0xf0a4
1745#define STB0899_RXEND (0x01 << 7)
1746#define STB0899_OFFST_RXEND 7
1747#define STB0899_WIDTH_RXEND 1
1748#define STB0899_RXACTIVE (0x01 << 6)
1749#define STB0899_OFFST_RXACTIVE 6
1750#define STB0899_WIDTH_RXACTIVE 1
1751#define STB0899_SHORT22K (0x01 << 5)
1752#define STB0899_OFFST_SHORT22K 5
1753#define STB0899_WIDTH_SHORT22K 1
1754#define STB0899_CONTTONE (0x01 << 4)
1755#define STB0899_OFFST_CONTTONE 4
1756#define STB0899_WIDTH_CONTONE 1
1757#define STB0899_4BFIFOREDY (0x01 << 3)
1758#define STB0899_OFFST_4BFIFOREDY 3
1759#define STB0899_WIDTH_4BFIFOREDY 1
1760#define STB0899_FIFOEMPTY (0x01 << 2)
1761#define STB0899_OFFST_FIFOEMPTY 2
1762#define STB0899_WIDTH_FIFOEMPTY 1
1763#define STB0899_ABORTTRX (0x01 << 0)
1764#define STB0899_OFFST_ABORTTRX 0
1765#define STB0899_WIDTH_ABORTTRX 1
1766
1767#define STB0899_DISRX_ST1 0xf0a5
1768#define STB0899_RXFAIL (0x01 << 7)
1769#define STB0899_OFFST_RXFAIL 7
1770#define STB0899_WIDTH_RXFAIL 1
1771#define STB0899_FIFOPFAIL (0x01 << 6)
1772#define STB0899_OFFST_FIFOPFAIL 6
1773#define STB0899_WIDTH_FIFOPFAIL 1
1774#define STB0899_RXNONBYTES (0x01 << 5)
1775#define STB0899_OFFST_RXNONBYTES 5
1776#define STB0899_WIDTH_RXNONBYTES 1
1777#define STB0899_FIFOOVF (0x01 << 4)
1778#define STB0899_OFFST_FIFOOVF 4
1779#define STB0899_WIDTH_FIFOOVF 1
1780#define STB0899_FIFOBYTENBR (0x0f << 0)
1781#define STB0899_OFFST_FIFOBYTENBR 0
1782#define STB0899_WIDTH_FIFOBYTENBR 4
1783
1784#define STB0899_DISPARITY 0xf0a6
1785
1786#define STB0899_DISFIFO 0xf0a7
1787
1788#define STB0899_DISSTATUS 0xf0a8
1789#define STB0899_FIFOFULL (0x01 << 6)
1790#define STB0899_OFFST_FIFOFULL 6
1791#define STB0899_WIDTH_FIFOFULL 1
1792#define STB0899_TXIDLE (0x01 << 5)
1793#define STB0899_OFFST_TXIDLE 5
1794#define STB0899_WIDTH_TXIDLE 1
1795#define STB0899_GAPBURST (0x01 << 4)
1796#define STB0899_OFFST_GAPBURST 4
1797#define STB0899_WIDTH_GAPBURST 1
1798#define STB0899_TXFIFOBYTES (0x0f << 0)
1799#define STB0899_OFFST_TXFIFOBYTES 0
1800#define STB0899_WIDTH_TXFIFOBYTES 4
1801#define STB0899_DISF22 0xf0a9
1802
1803#define STB0899_DISF22RX 0xf0aa
1804
1805/* General Purpose */
1806#define STB0899_SYSREG 0xf101
1807#define STB0899_ACRPRESC 0xf110
1808#define STB0899_ACRDIV1 0xf111
1809#define STB0899_ACRDIV2 0xf112
1810#define STB0899_DACR1 0xf113
1811#define STB0899_DACR2 0xf114
1812#define STB0899_OUTCFG 0xf11c
1813#define STB0899_MODECFG 0xf11d
1814#define STB0899_NCOARSE 0xf1b3
1815
1816#define STB0899_SYNTCTRL 0xf1b6
1817#define STB0899_STANDBY (0x01 << 7)
1818#define STB0899_OFFST_STANDBY 7
1819#define STB0899_WIDTH_STANDBY 1
1820#define STB0899_BYPASSPLL (0x01 << 6)
1821#define STB0899_OFFST_BYPASSPLL 6
1822#define STB0899_WIDTH_BYPASSPLL 1
1823#define STB0899_SEL1XRATIO (0x01 << 5)
1824#define STB0899_OFFST_SEL1XRATIO 5
1825#define STB0899_WIDTH_SEL1XRATIO 1
1826#define STB0899_SELOSCI (0x01 << 1)
1827#define STB0899_OFFST_SELOSCI 1
1828#define STB0899_WIDTH_SELOSCI 1
1829
1830#define STB0899_FILTCTRL 0xf1b7
1831#define STB0899_SYSCTRL 0xf1b8
1832
1833#define STB0899_STOPCLK1 0xf1c2
1834#define STB0899_STOP_CKINTBUF108 (0x01 << 7)
1835#define STB0899_OFFST_STOP_CKINTBUF108 7
1836#define STB0899_WIDTH_STOP_CKINTBUF108 1
1837#define STB0899_STOP_CKINTBUF216 (0x01 << 6)
1838#define STB0899_OFFST_STOP_CKINTBUF216 6
1839#define STB0899_WIDTH_STOP_CKINTBUF216 1
1840#define STB0899_STOP_CHK8PSK (0x01 << 5)
1841#define STB0899_OFFST_STOP_CHK8PSK 5
1842#define STB0899_WIDTH_STOP_CHK8PSK 1
1843#define STB0899_STOP_CKFEC108 (0x01 << 4)
1844#define STB0899_OFFST_STOP_CKFEC108 4
1845#define STB0899_WIDTH_STOP_CKFEC108 1
1846#define STB0899_STOP_CKFEC216 (0x01 << 3)
1847#define STB0899_OFFST_STOP_CKFEC216 3
1848#define STB0899_WIDTH_STOP_CKFEC216 1
1849#define STB0899_STOP_CKCORE216 (0x01 << 2)
1850#define STB0899_OFFST_STOP_CKCORE216 2
1851#define STB0899_WIDTH_STOP_CKCORE216 1
1852#define STB0899_STOP_CKADCI108 (0x01 << 1)
1853#define STB0899_OFFST_STOP_CKADCI108 1
1854#define STB0899_WIDTH_STOP_CKADCI108 1
1855#define STB0899_STOP_INVCKADCI108 (0x01 << 0)
1856#define STB0899_OFFST_STOP_INVCKADCI108 0
1857#define STB0899_WIDTH_STOP_INVCKADCI108 1
1858
1859#define STB0899_STOPCLK2 0xf1c3
1860#define STB0899_STOP_CKS2DMD108 (0x01 << 2)
1861#define STB0899_OFFST_STOP_CKS2DMD108 2
1862#define STB0899_WIDTH_STOP_CKS2DMD108 1
1863#define STB0899_STOP_CKPKDLIN108 (0x01 << 1)
1864#define STB0899_OFFST_STOP_CKPKDLIN108 1
1865#define STB0899_WIDTH_STOP_CKPKDLIN108 1
1866#define STB0899_STOP_CKPKDLIN216 (0x01 << 0)
1867#define STB0899_OFFST_STOP_CKPKDLIN216 0
1868#define STB0899_WIDTH_STOP_CKPKDLIN216 1
1869
1870#define STB0899_TSTTNR1 0xf1e0
1871#define STB0899_BYPASS_ADC (0x01 << 7)
1872#define STB0899_OFFST_BYPASS_ADC 7
1873#define STB0899_WIDTH_BYPASS_ADC 1
1874#define STB0899_INVADCICKOUT (0x01 << 6)
1875#define STB0899_OFFST_INVADCICKOUT 6
1876#define STB0899_WIDTH_INVADCICKOUT 1
1877#define STB0899_ADCTEST_VOLTAGE (0x03 << 4)
1878#define STB0899_OFFST_ADCTEST_VOLTAGE 4
1879#define STB0899_WIDTH_ADCTEST_VOLTAGE 1
1880#define STB0899_ADC_RESET (0x01 << 3)
1881#define STB0899_OFFST_ADC_RESET 3
1882#define STB0899_WIDTH_ADC_RESET 1
1883#define STB0899_TSTTNR1_2 (0x01 << 2)
1884#define STB0899_OFFST_TSTTNR1_2 2
1885#define STB0899_WIDTH_TSTTNR1_2 1
1886#define STB0899_ADCPON (0x01 << 1)
1887#define STB0899_OFFST_ADCPON 1
1888#define STB0899_WIDTH_ADCPON 1
1889#define STB0899_ADCIN_MODE (0x01 << 0)
1890#define STB0899_OFFST_ADCIN_MODE 0
1891#define STB0899_WIDTH_ADCIN_MODE 1
1892
1893#define STB0899_TSTTNR2 0xf1e1
1894#define STB0899_TSTTNR2_7 (0x01 << 7)
1895#define STB0899_OFFST_TSTTNR2_7 7
1896#define STB0899_WIDTH_TSTTNR2_7 1
1897#define STB0899_NOT_DISRX_WIRED (0x01 << 6)
1898#define STB0899_OFFST_NOT_DISRX_WIRED 6
1899#define STB0899_WIDTH_NOT_DISRX_WIRED 1
1900#define STB0899_DISEQC_DCURRENT (0x01 << 5)
1901#define STB0899_OFFST_DISEQC_DCURRENT 5
1902#define STB0899_WIDTH_DISEQC_DCURRENT 1
1903#define STB0899_DISEQC_ZCURRENT (0x01 << 4)
1904#define STB0899_OFFST_DISEQC_ZCURRENT 4
1905#define STB0899_WIDTH_DISEQC_ZCURRENT 1
1906#define STB0899_DISEQC_SINC_SOURCE (0x03 << 2)
1907#define STB0899_OFFST_DISEQC_SINC_SOURCE 2
1908#define STB0899_WIDTH_DISEQC_SINC_SOURCE 2
1909#define STB0899_SELIQSRC (0x03 << 0)
1910#define STB0899_OFFST_SELIQSRC 0
1911#define STB0899_WIDTH_SELIQSRC 2
1912
1913#define STB0899_TSTTNR3 0xf1e2
1914
1915#define STB0899_I2CCFG 0xf129
1916#define STB0899_I2CCFGRSVD (0x0f << 4)
1917#define STB0899_OFFST_I2CCFGRSVD 4
1918#define STB0899_WIDTH_I2CCFGRSVD 4
1919#define STB0899_I2CFASTMODE (0x01 << 3)
1920#define STB0899_OFFST_I2CFASTMODE 3
1921#define STB0899_WIDTH_I2CFASTMODE 1
1922#define STB0899_STATUSWR (0x01 << 2)
1923#define STB0899_OFFST_STATUSWR 2
1924#define STB0899_WIDTH_STATUSWR 1
1925#define STB0899_I2CADDRINC (0x03 << 0)
1926#define STB0899_OFFST_I2CADDRINC 0
1927#define STB0899_WIDTH_I2CADDRINC 2
1928
1929#define STB0899_I2CRPT 0xf12a
1930#define STB0899_I2CTON (0x01 << 7)
1931#define STB0899_OFFST_I2CTON 7
1932#define STB0899_WIDTH_I2CTON 1
1933#define STB0899_ENARPTLEVEL (0x01 << 6)
1934#define STB0899_OFFST_ENARPTLEVEL 6
1935#define STB0899_WIDTH_ENARPTLEVEL 2
1936#define STB0899_SCLTDELAY (0x01 << 3)
1937#define STB0899_OFFST_SCLTDELAY 3
1938#define STB0899_WIDTH_SCLTDELAY 1
1939#define STB0899_STOPENA (0x01 << 2)
1940#define STB0899_OFFST_STOPENA 2
1941#define STB0899_WIDTH_STOPENA 1
1942#define STB0899_STOPSDAT2SDA (0x01 << 1)
1943#define STB0899_OFFST_STOPSDAT2SDA 1
1944#define STB0899_WIDTH_STOPSDAT2SDA 1
1945
1946#define STB0899_IOPVALUE8 0xf136
1947#define STB0899_IOPVALUE7 0xf137
1948#define STB0899_IOPVALUE6 0xf138
1949#define STB0899_IOPVALUE5 0xf139
1950#define STB0899_IOPVALUE4 0xf13a
1951#define STB0899_IOPVALUE3 0xf13b
1952#define STB0899_IOPVALUE2 0xf13c
1953#define STB0899_IOPVALUE1 0xf13d
1954#define STB0899_IOPVALUE0 0xf13e
1955
1956#define STB0899_GPIO00CFG 0xf140
1957
1958#define STB0899_GPIO01CFG 0xf141
1959#define STB0899_GPIO02CFG 0xf142
1960#define STB0899_GPIO03CFG 0xf143
1961#define STB0899_GPIO04CFG 0xf144
1962#define STB0899_GPIO05CFG 0xf145
1963#define STB0899_GPIO06CFG 0xf146
1964#define STB0899_GPIO07CFG 0xf147
1965#define STB0899_GPIO08CFG 0xf148
1966#define STB0899_GPIO09CFG 0xf149
1967#define STB0899_GPIO10CFG 0xf14a
1968#define STB0899_GPIO11CFG 0xf14b
1969#define STB0899_GPIO12CFG 0xf14c
1970#define STB0899_GPIO13CFG 0xf14d
1971#define STB0899_GPIO14CFG 0xf14e
1972#define STB0899_GPIO15CFG 0xf14f
1973#define STB0899_GPIO16CFG 0xf150
1974#define STB0899_GPIO17CFG 0xf151
1975#define STB0899_GPIO18CFG 0xf152
1976#define STB0899_GPIO19CFG 0xf153
1977#define STB0899_GPIO20CFG 0xf154
1978
1979#define STB0899_SDATCFG 0xf155
1980#define STB0899_SCLTCFG 0xf156
1981#define STB0899_AGCRFCFG 0xf157
1982#define STB0899_GPIO22 0xf158 /* AGCBB2CFG */
1983#define STB0899_GPIO21 0xf159 /* AGCBB1CFG */
1984#define STB0899_DIRCLKCFG 0xf15a
1985#define STB0899_CLKOUT27CFG 0xf15b
1986#define STB0899_STDBYCFG 0xf15c
1987#define STB0899_CS0CFG 0xf15d
1988#define STB0899_CS1CFG 0xf15e
1989#define STB0899_DISEQCOCFG 0xf15f
1990
1991#define STB0899_GPIO32CFG 0xf160
1992#define STB0899_GPIO33CFG 0xf161
1993#define STB0899_GPIO34CFG 0xf162
1994#define STB0899_GPIO35CFG 0xf163
1995#define STB0899_GPIO36CFG 0xf164
1996#define STB0899_GPIO37CFG 0xf165
1997#define STB0899_GPIO38CFG 0xf166
1998#define STB0899_GPIO39CFG 0xf167
1999
2000#define STB0899_IRQSTATUS_3 0xf120
2001#define STB0899_IRQSTATUS_2 0xf121
2002#define STB0899_IRQSTATUS_1 0xf122
2003#define STB0899_IRQSTATUS_0 0xf123
2004
2005#define STB0899_IRQMSK_3 0xf124
2006#define STB0899_IRQMSK_2 0xf125
2007#define STB0899_IRQMSK_1 0xf126
2008#define STB0899_IRQMSK_0 0xf127
2009
2010#define STB0899_IRQCFG 0xf128
2011
2012#define STB0899_GHOSTREG 0xf000
2013
2014#define STB0899_S2DEMOD 0xf3fc
2015#define STB0899_S2FEC 0xfafc
2016
2017
2018#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 20:23:37 -0500