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authorDave Olson <dave.olson@qlogic.com>2008-01-09 02:16:17 -0500
committerRoland Dreier <rolandd@cisco.com>2008-01-25 17:15:44 -0500
commit7387273307139ebf8d7f7fb3bb79d1ca48bd71d6 (patch)
tree9d65581f68a0dd14589053aaafffa155193e5bf1 /drivers/infiniband/hw/ipath/ipath_registers.h
parent2ec8e662416cc9a171cdfe3d75e1ff00ba757859 (diff)
IB/ipath: Remove unused MDIO interface code
This code has been unused for some time, but still had leftovers from when it was used. Signed-off-by: Dave Olson <dave.olson@qlogic.com Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/ipath/ipath_registers.h')
-rw-r--r--drivers/infiniband/hw/ipath/ipath_registers.h16
1 files changed, 0 insertions, 16 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_registers.h b/drivers/infiniband/hw/ipath/ipath_registers.h
index 156ef147346..6d2a17f9c1d 100644
--- a/drivers/infiniband/hw/ipath/ipath_registers.h
+++ b/drivers/infiniband/hw/ipath/ipath_registers.h
@@ -271,20 +271,6 @@
271#define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL 271#define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL
272#define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL 272#define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL
273 273
274/* kr_mdio bits */
275#define INFINIPATH_MDIO_CLKDIV_MASK 0x7FULL
276#define INFINIPATH_MDIO_CLKDIV_SHIFT 32
277#define INFINIPATH_MDIO_COMMAND_MASK 0x7ULL
278#define INFINIPATH_MDIO_COMMAND_SHIFT 26
279#define INFINIPATH_MDIO_DEVADDR_MASK 0x1FULL
280#define INFINIPATH_MDIO_DEVADDR_SHIFT 21
281#define INFINIPATH_MDIO_REGADDR_MASK 0x1FULL
282#define INFINIPATH_MDIO_REGADDR_SHIFT 16
283#define INFINIPATH_MDIO_DATA_MASK 0xFFFFULL
284#define INFINIPATH_MDIO_DATA_SHIFT 0
285#define INFINIPATH_MDIO_CMDVALID 0x0000000040000000ULL
286#define INFINIPATH_MDIO_RDDATAVALID 0x0000000080000000ULL
287
288/* kr_partitionkey bits */ 274/* kr_partitionkey bits */
289#define INFINIPATH_PKEY_SIZE 16 275#define INFINIPATH_PKEY_SIZE 16
290#define INFINIPATH_PKEY_MASK 0xFFFF 276#define INFINIPATH_PKEY_MASK 0xFFFF
@@ -302,8 +288,6 @@
302 288
303/* kr_xgxsconfig bits */ 289/* kr_xgxsconfig bits */
304#define INFINIPATH_XGXS_RESET 0x7ULL 290#define INFINIPATH_XGXS_RESET 0x7ULL
305#define INFINIPATH_XGXS_MDIOADDR_MASK 0xfULL
306#define INFINIPATH_XGXS_MDIOADDR_SHIFT 4
307#define INFINIPATH_XGXS_RX_POL_SHIFT 19 291#define INFINIPATH_XGXS_RX_POL_SHIFT 19
308#define INFINIPATH_XGXS_RX_POL_MASK 0xfULL 292#define INFINIPATH_XGXS_RX_POL_MASK 0xfULL
309 293