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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-02-16 20:40:25 -0500
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-02-16 20:40:25 -0500
commit0ecdca26e556eae9668ce6de9554757dddb942ef (patch)
tree21d62c01d0c0d5aeea2524252ed8dec6ca20b6d4 /drivers/ide/pci/tc86c001.c
parent7569e8dc2213ecc47024ea5edbadc8736487d926 (diff)
ide: use PIO/MMIO operations directly where possible (v2)
This results in smaller/faster/simpler code and allows future optimizations. Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}. v2: * updated for scc_pata Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pci/tc86c001.c')
-rw-r--r--drivers/ide/pci/tc86c001.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/ide/pci/tc86c001.c b/drivers/ide/pci/tc86c001.c
index 4e893808f06..b408508a96e 100644
--- a/drivers/ide/pci/tc86c001.c
+++ b/drivers/ide/pci/tc86c001.c
@@ -45,7 +45,7 @@ static int tc86c001_tune_chipset(ide_drive_t *drive, u8 speed)
45 45
46 scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f; 46 scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
47 scr |= mode; 47 scr |= mode;
48 hwif->OUTW(scr, scr_port); 48 outw(scr, scr_port);
49 49
50 return ide_config_drive_speed(drive, speed); 50 return ide_config_drive_speed(drive, speed);
51} 51}
@@ -89,15 +89,15 @@ static int tc86c001_timer_expiry(ide_drive_t *drive)
89 "attempting recovery...\n", drive->name); 89 "attempting recovery...\n", drive->name);
90 90
91 /* Stop DMA */ 91 /* Stop DMA */
92 hwif->OUTB(dma_cmd & ~0x01, hwif->dma_command); 92 outb(dma_cmd & ~0x01, hwif->dma_command);
93 93
94 /* Setup the dummy DMA transfer */ 94 /* Setup the dummy DMA transfer */
95 hwif->OUTW(0, sc_base + 0x0a); /* Sector Count */ 95 outw(0, sc_base + 0x0a); /* Sector Count */
96 hwif->OUTW(0, twcr_port); /* Transfer Word Count 1 or 2 */ 96 outw(0, twcr_port); /* Transfer Word Count 1 or 2 */
97 97
98 /* Start the dummy DMA transfer */ 98 /* Start the dummy DMA transfer */
99 hwif->OUTB(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */ 99 outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
100 hwif->OUTB(0x01, hwif->dma_command); /* set START_STOPBM */ 100 outb(0x01, hwif->dma_command); /* set START_STOPBM */
101 101
102 /* 102 /*
103 * If an interrupt was pending, it should come thru shortly. 103 * If an interrupt was pending, it should come thru shortly.
@@ -128,8 +128,8 @@ static void tc86c001_dma_start(ide_drive_t *drive)
128 * the appropriate system control registers for DMA to work 128 * the appropriate system control registers for DMA to work
129 * with LBA48 and ATAPI devices... 129 * with LBA48 and ATAPI devices...
130 */ 130 */
131 hwif->OUTW(nsectors, sc_base + 0x0a); /* Sector Count */ 131 outw(nsectors, sc_base + 0x0a); /* Sector Count */
132 hwif->OUTW(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */ 132 outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
133 133
134 /* Install our timeout expiry hook, saving the current handler... */ 134 /* Install our timeout expiry hook, saving the current handler... */
135 ide_set_hwifdata(hwif, hwgroup->expiry); 135 ide_set_hwifdata(hwif, hwgroup->expiry);
@@ -168,7 +168,7 @@ static int tc86c001_busproc(ide_drive_t *drive, int state)
168 } 168 }
169 169
170 /* System Control 1 Register bit 11 (ATA Hard Reset) write */ 170 /* System Control 1 Register bit 11 (ATA Hard Reset) write */
171 hwif->OUTW(scr1, sc_base + 0x00); 171 outw(scr1, sc_base + 0x00);
172 return 0; 172 return 0;
173} 173}
174 174
@@ -204,13 +204,13 @@ static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
204 u16 scr1 = hwif->INW(sc_base + 0x00);; 204 u16 scr1 = hwif->INW(sc_base + 0x00);;
205 205
206 /* System Control 1 Register bit 15 (Soft Reset) set */ 206 /* System Control 1 Register bit 15 (Soft Reset) set */
207 hwif->OUTW(scr1 | 0x8000, sc_base + 0x00); 207 outw(scr1 | 0x8000, sc_base + 0x00);
208 208
209 /* System Control 1 Register bit 14 (FIFO Reset) set */ 209 /* System Control 1 Register bit 14 (FIFO Reset) set */
210 hwif->OUTW(scr1 | 0x4000, sc_base + 0x00); 210 outw(scr1 | 0x4000, sc_base + 0x00);
211 211
212 /* System Control 1 Register: reset clear */ 212 /* System Control 1 Register: reset clear */
213 hwif->OUTW(scr1 & ~0xc000, sc_base + 0x00); 213 outw(scr1 & ~0xc000, sc_base + 0x00);
214 214
215 /* Store the system control register base for convenience... */ 215 /* Store the system control register base for convenience... */
216 hwif->config_data = sc_base; 216 hwif->config_data = sc_base;
@@ -228,7 +228,7 @@ static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
228 * Sector Count Control Register bits 0 and 1 set: 228 * Sector Count Control Register bits 0 and 1 set:
229 * software sets Sector Count Register for master and slave device 229 * software sets Sector Count Register for master and slave device
230 */ 230 */
231 hwif->OUTW(0x0003, sc_base + 0x0c); 231 outw(0x0003, sc_base + 0x0c);
232 232
233 /* Sector Count Register limit */ 233 /* Sector Count Register limit */
234 hwif->rqsize = 0xffff; 234 hwif->rqsize = 0xffff;