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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-05-13 16:29:25 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-06-01 03:12:59 -0400
commit808cf72ca9988a146dff8a8f658dcbad3cd31d5d (patch)
treef1271ac5edf241cddfc83e7f268e86c80e9c4097 /drivers/gpu
parentaa8878bc13c76b9d8b52e55210e2c940987a5fb8 (diff)
drm/i915: don't clobber the pipe param in sanitize_modesetting
commit a9dcf84b14ef4e9a609910367576995e6f32f3dc upstream. ... we need it later on in the function to clean up pipe <-> plane associations. This regression has been introduced in commit f47166d2b0001fcb752b40c5a2d4db986dfbea68 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Mar 22 15:00:50 2012 +0000 drm/i915: Sanitize BIOS debugging bits from PIPECONF Spotted by staring at debug output of an (as it turns out) totally unrelated bug. v2: I've totally failed to do the s/pipe/i/ correctly, spotted by Chris Wilson. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a040ca0ae20..4b8e2355517 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6579,10 +6579,11 @@ static void intel_sanitize_modesetting(struct drm_device *dev,
6579{ 6579{
6580 struct drm_i915_private *dev_priv = dev->dev_private; 6580 struct drm_i915_private *dev_priv = dev->dev_private;
6581 u32 reg, val; 6581 u32 reg, val;
6582 int i;
6582 6583
6583 /* Clear any frame start delays used for debugging left by the BIOS */ 6584 /* Clear any frame start delays used for debugging left by the BIOS */
6584 for_each_pipe(pipe) { 6585 for_each_pipe(i) {
6585 reg = PIPECONF(pipe); 6586 reg = PIPECONF(i);
6586 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 6587 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6587 } 6588 }
6588 6589