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authorMichel Dänzer <daenzer@vmware.com>2009-08-13 05:10:51 -0400
committerDave Airlie <airlied@redhat.com>2009-08-15 18:36:19 -0400
commit7ed220d738cf16adff6bc3b31ad25b8848a2fa9c (patch)
treea751003e7cf1dc63ea478181dffef936f04cc24e /drivers/gpu/drm/radeon
parent3f8befec95d5c1bbc6e247e1a5dafa82519530f9 (diff)
drm/radeon/kms: Fix up vertical blank interrupt support.
Fixes 3D apps timing out in the WAIT_VBLANK ioctl. AVIVO bits compile-tested only. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/r100.c66
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h16
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h23
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c54
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c33
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h11
-rw-r--r--drivers/gpu/drm/radeon/rs600.c82
9 files changed, 217 insertions, 77 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index f1ba8ff4113..e1a6e82b996 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -254,6 +254,72 @@ void r100_mc_fini(struct radeon_device *rdev)
254 254
255 255
256/* 256/*
257 * Interrupts
258 */
259int r100_irq_set(struct radeon_device *rdev)
260{
261 uint32_t tmp = 0;
262
263 if (rdev->irq.sw_int) {
264 tmp |= RADEON_SW_INT_ENABLE;
265 }
266 if (rdev->irq.crtc_vblank_int[0]) {
267 tmp |= RADEON_CRTC_VBLANK_MASK;
268 }
269 if (rdev->irq.crtc_vblank_int[1]) {
270 tmp |= RADEON_CRTC2_VBLANK_MASK;
271 }
272 WREG32(RADEON_GEN_INT_CNTL, tmp);
273 return 0;
274}
275
276static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
277{
278 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
279 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
280 RADEON_CRTC2_VBLANK_STAT;
281
282 if (irqs) {
283 WREG32(RADEON_GEN_INT_STATUS, irqs);
284 }
285 return irqs & irq_mask;
286}
287
288int r100_irq_process(struct radeon_device *rdev)
289{
290 uint32_t status;
291
292 status = r100_irq_ack(rdev);
293 if (!status) {
294 return IRQ_NONE;
295 }
296 while (status) {
297 /* SW interrupt */
298 if (status & RADEON_SW_INT_TEST) {
299 radeon_fence_process(rdev);
300 }
301 /* Vertical blank interrupts */
302 if (status & RADEON_CRTC_VBLANK_STAT) {
303 drm_handle_vblank(rdev->ddev, 0);
304 }
305 if (status & RADEON_CRTC2_VBLANK_STAT) {
306 drm_handle_vblank(rdev->ddev, 1);
307 }
308 status = r100_irq_ack(rdev);
309 }
310 return IRQ_HANDLED;
311}
312
313u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
314{
315 if (crtc == 0)
316 return RREG32(RADEON_CRTC_CRNT_FRAME);
317 else
318 return RREG32(RADEON_CRTC2_CRNT_FRAME);
319}
320
321
322/*
257 * Fence emission 323 * Fence emission
258 */ 324 */
259void r100_fence_ring_emit(struct radeon_device *rdev, 325void r100_fence_ring_emit(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 036691b38cb..e1d5e0331e1 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -350,6 +350,7 @@
350#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 350#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
351#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 351#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
352#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c 352#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
353#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
353#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 354#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
354 355
355/* master controls */ 356/* master controls */
@@ -438,14 +439,15 @@
438# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 439# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
439# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff 440# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
440 441
441#define R500_DxMODE_INT_MASK 0x6540
442#define R500_D1MODE_INT_MASK (1<<0)
443#define R500_D2MODE_INT_MASK (1<<8)
444
445#define AVIVO_D1MODE_DATA_FORMAT 0x6528 442#define AVIVO_D1MODE_DATA_FORMAT 0x6528
446# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) 443# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
447#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C 444#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
445#define AVIVO_D1MODE_VBLANK_STATUS 0x6534
446# define AVIVO_VBLANK_ACK (1 << 4)
448#define AVIVO_D1MODE_VLINE_START_END 0x6538 447#define AVIVO_D1MODE_VLINE_START_END 0x6538
448#define AVIVO_DxMODE_INT_MASK 0x6540
449# define AVIVO_D1MODE_INT_MASK (1 << 0)
450# define AVIVO_D2MODE_INT_MASK (1 << 8)
449#define AVIVO_D1MODE_VIEWPORT_START 0x6580 451#define AVIVO_D1MODE_VIEWPORT_START 0x6580
450#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 452#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
451#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 453#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
@@ -475,6 +477,7 @@
475#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 477#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
476#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 478#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
477#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c 479#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
480#define AVIVO_D2CRTC_FRAME_COUNT 0x68a4
478#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 481#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
479 482
480#define AVIVO_D2GRPH_ENABLE 0x6900 483#define AVIVO_D2GRPH_ENABLE 0x6900
@@ -497,6 +500,7 @@
497#define AVIVO_D2CUR_SIZE 0x6c10 500#define AVIVO_D2CUR_SIZE 0x6c10
498#define AVIVO_D2CUR_POSITION 0x6c14 501#define AVIVO_D2CUR_POSITION 0x6c14
499 502
503#define AVIVO_D2MODE_VBLANK_STATUS 0x6d34
500#define AVIVO_D2MODE_VLINE_START_END 0x6d38 504#define AVIVO_D2MODE_VLINE_START_END 0x6d38
501#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 505#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
502#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 506#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
@@ -748,4 +752,8 @@
748# define AVIVO_I2C_EN (1 << 0) 752# define AVIVO_I2C_EN (1 << 0)
749# define AVIVO_I2C_RESET (1 << 8) 753# define AVIVO_I2C_RESET (1 << 8)
750 754
755#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc
756# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4)
757# define AVIVO_D2_VBLANK_INTERRUPT (1 << 5)
758
751#endif 759#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b1d945b8ed6..34611274084 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -574,6 +574,7 @@ struct radeon_asic {
574 void (*ring_start)(struct radeon_device *rdev); 574 void (*ring_start)(struct radeon_device *rdev);
575 int (*irq_set)(struct radeon_device *rdev); 575 int (*irq_set)(struct radeon_device *rdev);
576 int (*irq_process)(struct radeon_device *rdev); 576 int (*irq_process)(struct radeon_device *rdev);
577 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
577 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 578 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
578 int (*cs_parse)(struct radeon_cs_parser *p); 579 int (*cs_parse)(struct radeon_cs_parser *p);
579 int (*copy_blit)(struct radeon_device *rdev, 580 int (*copy_blit)(struct radeon_device *rdev,
@@ -862,6 +863,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
862#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 863#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
863#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 864#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
864#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 865#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
866#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
865#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 867#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
866#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 868#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
867#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 869#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c0ae2d92325..7ca6c13569b 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -49,6 +49,7 @@ void r100_vram_info(struct radeon_device *rdev);
49int r100_gpu_reset(struct radeon_device *rdev); 49int r100_gpu_reset(struct radeon_device *rdev);
50int r100_mc_init(struct radeon_device *rdev); 50int r100_mc_init(struct radeon_device *rdev);
51void r100_mc_fini(struct radeon_device *rdev); 51void r100_mc_fini(struct radeon_device *rdev);
52u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
52int r100_wb_init(struct radeon_device *rdev); 53int r100_wb_init(struct radeon_device *rdev);
53void r100_wb_fini(struct radeon_device *rdev); 54void r100_wb_fini(struct radeon_device *rdev);
54int r100_gart_enable(struct radeon_device *rdev); 55int r100_gart_enable(struct radeon_device *rdev);
@@ -96,6 +97,7 @@ static struct radeon_asic r100_asic = {
96 .ring_start = &r100_ring_start, 97 .ring_start = &r100_ring_start,
97 .irq_set = &r100_irq_set, 98 .irq_set = &r100_irq_set,
98 .irq_process = &r100_irq_process, 99 .irq_process = &r100_irq_process,
100 .get_vblank_counter = &r100_get_vblank_counter,
99 .fence_ring_emit = &r100_fence_ring_emit, 101 .fence_ring_emit = &r100_fence_ring_emit,
100 .cs_parse = &r100_cs_parse, 102 .cs_parse = &r100_cs_parse,
101 .copy_blit = &r100_copy_blit, 103 .copy_blit = &r100_copy_blit,
@@ -156,6 +158,7 @@ static struct radeon_asic r300_asic = {
156 .ring_start = &r300_ring_start, 158 .ring_start = &r300_ring_start,
157 .irq_set = &r100_irq_set, 159 .irq_set = &r100_irq_set,
158 .irq_process = &r100_irq_process, 160 .irq_process = &r100_irq_process,
161 .get_vblank_counter = &r100_get_vblank_counter,
159 .fence_ring_emit = &r300_fence_ring_emit, 162 .fence_ring_emit = &r300_fence_ring_emit,
160 .cs_parse = &r300_cs_parse, 163 .cs_parse = &r300_cs_parse,
161 .copy_blit = &r100_copy_blit, 164 .copy_blit = &r100_copy_blit,
@@ -196,6 +199,7 @@ static struct radeon_asic r420_asic = {
196 .ring_start = &r300_ring_start, 199 .ring_start = &r300_ring_start,
197 .irq_set = &r100_irq_set, 200 .irq_set = &r100_irq_set,
198 .irq_process = &r100_irq_process, 201 .irq_process = &r100_irq_process,
202 .get_vblank_counter = &r100_get_vblank_counter,
199 .fence_ring_emit = &r300_fence_ring_emit, 203 .fence_ring_emit = &r300_fence_ring_emit,
200 .cs_parse = &r300_cs_parse, 204 .cs_parse = &r300_cs_parse,
201 .copy_blit = &r100_copy_blit, 205 .copy_blit = &r100_copy_blit,
@@ -243,6 +247,7 @@ static struct radeon_asic rs400_asic = {
243 .ring_start = &r300_ring_start, 247 .ring_start = &r300_ring_start,
244 .irq_set = &r100_irq_set, 248 .irq_set = &r100_irq_set,
245 .irq_process = &r100_irq_process, 249 .irq_process = &r100_irq_process,
250 .get_vblank_counter = &r100_get_vblank_counter,
246 .fence_ring_emit = &r300_fence_ring_emit, 251 .fence_ring_emit = &r300_fence_ring_emit,
247 .cs_parse = &r300_cs_parse, 252 .cs_parse = &r300_cs_parse,
248 .copy_blit = &r100_copy_blit, 253 .copy_blit = &r100_copy_blit,
@@ -266,6 +271,8 @@ void rs600_vram_info(struct radeon_device *rdev);
266int rs600_mc_init(struct radeon_device *rdev); 271int rs600_mc_init(struct radeon_device *rdev);
267void rs600_mc_fini(struct radeon_device *rdev); 272void rs600_mc_fini(struct radeon_device *rdev);
268int rs600_irq_set(struct radeon_device *rdev); 273int rs600_irq_set(struct radeon_device *rdev);
274int rs600_irq_process(struct radeon_device *rdev);
275u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
269int rs600_gart_enable(struct radeon_device *rdev); 276int rs600_gart_enable(struct radeon_device *rdev);
270void rs600_gart_disable(struct radeon_device *rdev); 277void rs600_gart_disable(struct radeon_device *rdev);
271void rs600_gart_tlb_flush(struct radeon_device *rdev); 278void rs600_gart_tlb_flush(struct radeon_device *rdev);
@@ -291,7 +298,8 @@ static struct radeon_asic rs600_asic = {
291 .cp_disable = &r100_cp_disable, 298 .cp_disable = &r100_cp_disable,
292 .ring_start = &r300_ring_start, 299 .ring_start = &r300_ring_start,
293 .irq_set = &rs600_irq_set, 300 .irq_set = &rs600_irq_set,
294 .irq_process = &r100_irq_process, 301 .irq_process = &rs600_irq_process,
302 .get_vblank_counter = &rs600_get_vblank_counter,
295 .fence_ring_emit = &r300_fence_ring_emit, 303 .fence_ring_emit = &r300_fence_ring_emit,
296 .cs_parse = &r300_cs_parse, 304 .cs_parse = &r300_cs_parse,
297 .copy_blit = &r100_copy_blit, 305 .copy_blit = &r100_copy_blit,
@@ -334,7 +342,8 @@ static struct radeon_asic rs690_asic = {
334 .cp_disable = &r100_cp_disable, 342 .cp_disable = &r100_cp_disable,
335 .ring_start = &r300_ring_start, 343 .ring_start = &r300_ring_start,
336 .irq_set = &rs600_irq_set, 344 .irq_set = &rs600_irq_set,
337 .irq_process = &r100_irq_process, 345 .irq_process = &rs600_irq_process,
346 .get_vblank_counter = &rs600_get_vblank_counter,
338 .fence_ring_emit = &r300_fence_ring_emit, 347 .fence_ring_emit = &r300_fence_ring_emit,
339 .cs_parse = &r300_cs_parse, 348 .cs_parse = &r300_cs_parse,
340 .copy_blit = &r100_copy_blit, 349 .copy_blit = &r100_copy_blit,
@@ -382,8 +391,9 @@ static struct radeon_asic rv515_asic = {
382 .cp_fini = &r100_cp_fini, 391 .cp_fini = &r100_cp_fini,
383 .cp_disable = &r100_cp_disable, 392 .cp_disable = &r100_cp_disable,
384 .ring_start = &rv515_ring_start, 393 .ring_start = &rv515_ring_start,
385 .irq_set = &r100_irq_set, 394 .irq_set = &rs600_irq_set,
386 .irq_process = &r100_irq_process, 395 .irq_process = &rs600_irq_process,
396 .get_vblank_counter = &rs600_get_vblank_counter,
387 .fence_ring_emit = &r300_fence_ring_emit, 397 .fence_ring_emit = &r300_fence_ring_emit,
388 .cs_parse = &r300_cs_parse, 398 .cs_parse = &r300_cs_parse,
389 .copy_blit = &r100_copy_blit, 399 .copy_blit = &r100_copy_blit,
@@ -424,8 +434,9 @@ static struct radeon_asic r520_asic = {
424 .cp_fini = &r100_cp_fini, 434 .cp_fini = &r100_cp_fini,
425 .cp_disable = &r100_cp_disable, 435 .cp_disable = &r100_cp_disable,
426 .ring_start = &rv515_ring_start, 436 .ring_start = &rv515_ring_start,
427 .irq_set = &r100_irq_set, 437 .irq_set = &rs600_irq_set,
428 .irq_process = &r100_irq_process, 438 .irq_process = &rs600_irq_process,
439 .get_vblank_counter = &rs600_get_vblank_counter,
429 .fence_ring_emit = &r300_fence_ring_emit, 440 .fence_ring_emit = &r300_fence_ring_emit,
430 .cs_parse = &r300_cs_parse, 441 .cs_parse = &r300_cs_parse,
431 .copy_blit = &r100_copy_blit, 442 .copy_blit = &r100_copy_blit,
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 491d569deb0..9805e4b6ca1 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -32,60 +32,6 @@
32#include "radeon.h" 32#include "radeon.h"
33#include "atom.h" 33#include "atom.h"
34 34
35static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
36{
37 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
38 uint32_t irq_mask = RADEON_SW_INT_TEST;
39
40 if (irqs) {
41 WREG32(RADEON_GEN_INT_STATUS, irqs);
42 }
43 return irqs & irq_mask;
44}
45
46int r100_irq_set(struct radeon_device *rdev)
47{
48 uint32_t tmp = 0;
49
50 if (rdev->irq.sw_int) {
51 tmp |= RADEON_SW_INT_ENABLE;
52 }
53 /* Todo go through CRTC and enable vblank int or not */
54 WREG32(RADEON_GEN_INT_CNTL, tmp);
55 return 0;
56}
57
58int r100_irq_process(struct radeon_device *rdev)
59{
60 uint32_t status;
61
62 status = r100_irq_ack(rdev);
63 if (!status) {
64 return IRQ_NONE;
65 }
66 while (status) {
67 /* SW interrupt */
68 if (status & RADEON_SW_INT_TEST) {
69 radeon_fence_process(rdev);
70 }
71 status = r100_irq_ack(rdev);
72 }
73 return IRQ_HANDLED;
74}
75
76int rs600_irq_set(struct radeon_device *rdev)
77{
78 uint32_t tmp = 0;
79
80 if (rdev->irq.sw_int) {
81 tmp |= RADEON_SW_INT_ENABLE;
82 }
83 WREG32(RADEON_GEN_INT_CNTL, tmp);
84 /* Todo go through CRTC and enable vblank int or not */
85 WREG32(R500_DxMODE_INT_MASK, 0);
86 return 0;
87}
88
89irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS) 35irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
90{ 36{
91 struct drm_device *dev = (struct drm_device *) arg; 37 struct drm_device *dev = (struct drm_device *) arg;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 3357110e30c..d2764bf6b2a 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -141,19 +141,42 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
141 */ 141 */
142u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 142u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
143{ 143{
144 /* FIXME: implement */ 144 struct radeon_device *rdev = dev->dev_private;
145 return 0; 145
146 if (crtc < 0 || crtc > 1) {
147 DRM_ERROR("Invalid crtc %d\n", crtc);
148 return -EINVAL;
149 }
150
151 return radeon_get_vblank_counter(rdev, crtc);
146} 152}
147 153
148int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 154int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
149{ 155{
150 /* FIXME: implement */ 156 struct radeon_device *rdev = dev->dev_private;
151 return 0; 157
158 if (crtc < 0 || crtc > 1) {
159 DRM_ERROR("Invalid crtc %d\n", crtc);
160 return -EINVAL;
161 }
162
163 rdev->irq.crtc_vblank_int[crtc] = true;
164
165 return radeon_irq_set(rdev);
152} 166}
153 167
154void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 168void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
155{ 169{
156 /* FIXME: implement */ 170 struct radeon_device *rdev = dev->dev_private;
171
172 if (crtc < 0 || crtc > 1) {
173 DRM_ERROR("Invalid crtc %d\n", crtc);
174 return;
175 }
176
177 rdev->irq.crtc_vblank_int[crtc] = false;
178
179 radeon_irq_set(rdev);
157} 180}
158 181
159 182
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 7d06dc98a42..0da72f18fd3 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -310,10 +310,13 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
310 RADEON_CRTC_DISP_REQ_EN_B)); 310 RADEON_CRTC_DISP_REQ_EN_B));
311 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); 311 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
312 } 312 }
313 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
314 radeon_crtc_load_lut(crtc);
313 break; 315 break;
314 case DRM_MODE_DPMS_STANDBY: 316 case DRM_MODE_DPMS_STANDBY:
315 case DRM_MODE_DPMS_SUSPEND: 317 case DRM_MODE_DPMS_SUSPEND:
316 case DRM_MODE_DPMS_OFF: 318 case DRM_MODE_DPMS_OFF:
319 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
317 if (radeon_crtc->crtc_id) 320 if (radeon_crtc->crtc_id)
318 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask); 321 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
319 else { 322 else {
@@ -323,10 +326,6 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
323 } 326 }
324 break; 327 break;
325 } 328 }
326
327 if (mode != DRM_MODE_DPMS_OFF) {
328 radeon_crtc_load_lut(crtc);
329 }
330} 329}
331 330
332/* properly set crtc bpp when using atombios */ 331/* properly set crtc bpp when using atombios */
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index e1b61857446..5a098f304ed 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -982,12 +982,15 @@
982# define RS400_TMDS2_PLLRST (1 << 1) 982# define RS400_TMDS2_PLLRST (1 << 1)
983 983
984#define RADEON_GEN_INT_CNTL 0x0040 984#define RADEON_GEN_INT_CNTL 0x0040
985# define RADEON_CRTC_VBLANK_MASK (1 << 0)
986# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
985# define RADEON_SW_INT_ENABLE (1 << 25) 987# define RADEON_SW_INT_ENABLE (1 << 25)
986#define RADEON_GEN_INT_STATUS 0x0044 988#define RADEON_GEN_INT_STATUS 0x0044
987# define RADEON_VSYNC_INT_AK (1 << 2) 989# define AVIVO_DISPLAY_INT_STATUS (1 << 0)
988# define RADEON_VSYNC_INT (1 << 2) 990# define RADEON_CRTC_VBLANK_STAT (1 << 0)
989# define RADEON_VSYNC2_INT_AK (1 << 6) 991# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
990# define RADEON_VSYNC2_INT (1 << 6) 992# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
993# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
991# define RADEON_SW_INT_FIRE (1 << 26) 994# define RADEON_SW_INT_FIRE (1 << 26)
992# define RADEON_SW_INT_TEST (1 << 25) 995# define RADEON_SW_INT_TEST (1 << 25)
993# define RADEON_SW_INT_TEST_ACK (1 << 25) 996# define RADEON_SW_INT_TEST_ACK (1 << 25)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index bbea6dee4a9..7e8ce983a90 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -240,6 +240,88 @@ void rs600_mc_fini(struct radeon_device *rdev)
240 240
241 241
242/* 242/*
243 * Interrupts
244 */
245int rs600_irq_set(struct radeon_device *rdev)
246{
247 uint32_t tmp = 0;
248 uint32_t mode_int = 0;
249
250 if (rdev->irq.sw_int) {
251 tmp |= RADEON_SW_INT_ENABLE;
252 }
253 if (rdev->irq.crtc_vblank_int[0]) {
254 tmp |= AVIVO_DISPLAY_INT_STATUS;
255 mode_int |= AVIVO_D1MODE_INT_MASK;
256 }
257 if (rdev->irq.crtc_vblank_int[1]) {
258 tmp |= AVIVO_DISPLAY_INT_STATUS;
259 mode_int |= AVIVO_D2MODE_INT_MASK;
260 }
261 WREG32(RADEON_GEN_INT_CNTL, tmp);
262 WREG32(AVIVO_DxMODE_INT_MASK, mode_int);
263 return 0;
264}
265
266static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
267{
268 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
269 uint32_t irq_mask = RADEON_SW_INT_TEST;
270
271 if (irqs & AVIVO_DISPLAY_INT_STATUS) {
272 *r500_disp_int = RREG32(AVIVO_DISP_INTERRUPT_STATUS);
273 if (*r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
274 WREG32(AVIVO_D1MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
275 }
276 if (*r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
277 WREG32(AVIVO_D2MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
278 }
279 } else {
280 *r500_disp_int = 0;
281 }
282
283 if (irqs) {
284 WREG32(RADEON_GEN_INT_STATUS, irqs);
285 }
286 return irqs & irq_mask;
287}
288
289int rs600_irq_process(struct radeon_device *rdev)
290{
291 uint32_t status;
292 uint32_t r500_disp_int;
293
294 status = rs600_irq_ack(rdev, &r500_disp_int);
295 if (!status && !r500_disp_int) {
296 return IRQ_NONE;
297 }
298 while (status || r500_disp_int) {
299 /* SW interrupt */
300 if (status & RADEON_SW_INT_TEST) {
301 radeon_fence_process(rdev);
302 }
303 /* Vertical blank interrupts */
304 if (r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
305 drm_handle_vblank(rdev->ddev, 0);
306 }
307 if (r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
308 drm_handle_vblank(rdev->ddev, 1);
309 }
310 status = rs600_irq_ack(rdev, &r500_disp_int);
311 }
312 return IRQ_HANDLED;
313}
314
315u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
316{
317 if (crtc == 0)
318 return RREG32(AVIVO_D1CRTC_FRAME_COUNT);
319 else
320 return RREG32(AVIVO_D2CRTC_FRAME_COUNT);
321}
322
323
324/*
243 * Global GPU functions 325 * Global GPU functions
244 */ 326 */
245void rs600_disable_vga(struct radeon_device *rdev) 327void rs600_disable_vga(struct radeon_device *rdev)