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authorAlex Deucher <alexdeucher@gmail.com>2009-10-09 15:14:30 -0400
committerDave Airlie <airlied@redhat.com>2009-10-11 23:42:48 -0400
commitde2103e452ec7f2db5db7c44279735688608381d (patch)
tree10ccecbf806c916a774a486eb83c1b01520c607c /drivers/gpu/drm/radeon/radeon_mode.h
parent5a9bcacc0a56f0d9577494e834519480018a6cc3 (diff)
drm/radeon/kms: use drm_mode directly for panel modes
This reduces the number of mode format conversions needed and makes native panel mode support cleaner. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h19
1 files changed, 4 insertions, 15 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index e61226817cc..3d2631be073 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -186,17 +186,6 @@ struct radeon_mode_info {
186 186
187}; 187};
188 188
189struct radeon_native_mode {
190 /* preferred mode */
191 uint32_t panel_xres, panel_yres;
192 uint32_t hoverplus, hsync_width;
193 uint32_t hblank;
194 uint32_t voverplus, vsync_width;
195 uint32_t vblank;
196 uint32_t dotclock;
197 uint32_t flags;
198};
199
200#define MAX_H_CODE_TIMING_LEN 32 189#define MAX_H_CODE_TIMING_LEN 32
201#define MAX_V_CODE_TIMING_LEN 32 190#define MAX_V_CODE_TIMING_LEN 32
202 191
@@ -228,7 +217,7 @@ struct radeon_crtc {
228 enum radeon_rmx_type rmx_type; 217 enum radeon_rmx_type rmx_type;
229 fixed20_12 vsc; 218 fixed20_12 vsc;
230 fixed20_12 hsc; 219 fixed20_12 hsc;
231 struct radeon_native_mode native_mode; 220 struct drm_display_mode native_mode;
232}; 221};
233 222
234struct radeon_encoder_primary_dac { 223struct radeon_encoder_primary_dac {
@@ -248,7 +237,7 @@ struct radeon_encoder_lvds {
248 bool use_bios_dividers; 237 bool use_bios_dividers;
249 uint32_t lvds_gen_cntl; 238 uint32_t lvds_gen_cntl;
250 /* panel mode */ 239 /* panel mode */
251 struct radeon_native_mode native_mode; 240 struct drm_display_mode native_mode;
252}; 241};
253 242
254struct radeon_encoder_tv_dac { 243struct radeon_encoder_tv_dac {
@@ -279,7 +268,7 @@ struct radeon_encoder_atom_dig {
279 uint32_t lvds_misc; 268 uint32_t lvds_misc;
280 uint16_t panel_pwr_delay; 269 uint16_t panel_pwr_delay;
281 /* panel mode */ 270 /* panel mode */
282 struct radeon_native_mode native_mode; 271 struct drm_display_mode native_mode;
283}; 272};
284 273
285struct radeon_encoder_atom_dac { 274struct radeon_encoder_atom_dac {
@@ -294,7 +283,7 @@ struct radeon_encoder {
294 uint32_t flags; 283 uint32_t flags;
295 uint32_t pixel_clock; 284 uint32_t pixel_clock;
296 enum radeon_rmx_type rmx_type; 285 enum radeon_rmx_type rmx_type;
297 struct radeon_native_mode native_mode; 286 struct drm_display_mode native_mode;
298 void *enc_priv; 287 void *enc_priv;
299}; 288};
300 289