diff options
author | Dave Airlie <airlied@redhat.com> | 2011-03-15 21:34:41 -0400 |
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committer | Dave Airlie <airlied@redhat.com> | 2011-03-15 21:34:41 -0400 |
commit | 38f1cff0863809587b5fd10ecd0c24c8b543a48c (patch) | |
tree | 7cf6eb88cdc938c3683209d38311e711a1119400 /drivers/gpu/drm/radeon/radeon_legacy_crtc.c | |
parent | 4819d2e4310796c4e9eef674499af9b9caf36b5a (diff) | |
parent | 5359533801e3dd3abca5b7d3d985b0b33fd9fe8b (diff) |
Merge commit '5359533801e3dd3abca5b7d3d985b0b33fd9fe8b' into drm-core-next
This commit changed an internal radeon structure, that meant a new driver
in -next had to be fixed up, merge in the commit and fix up the driver.
Also fixes a trivial nouveau merge.
Conflicts:
drivers/gpu/drm/nouveau/nouveau_mem.c
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_legacy_crtc.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 9ae599eb2e6..66c9af1b3d9 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c | |||
@@ -443,7 +443,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, | |||
443 | (target_fb->bits_per_pixel * 8)); | 443 | (target_fb->bits_per_pixel * 8)); |
444 | crtc_pitch |= crtc_pitch << 16; | 444 | crtc_pitch |= crtc_pitch << 16; |
445 | 445 | ||
446 | 446 | crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; | |
447 | if (tiling_flags & RADEON_TILING_MACRO) { | 447 | if (tiling_flags & RADEON_TILING_MACRO) { |
448 | if (ASIC_IS_R300(rdev)) | 448 | if (ASIC_IS_R300(rdev)) |
449 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | | 449 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
@@ -502,6 +502,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, | |||
502 | gen_cntl_val = RREG32(gen_cntl_reg); | 502 | gen_cntl_val = RREG32(gen_cntl_reg); |
503 | gen_cntl_val &= ~(0xf << 8); | 503 | gen_cntl_val &= ~(0xf << 8); |
504 | gen_cntl_val |= (format << 8); | 504 | gen_cntl_val |= (format << 8); |
505 | gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; | ||
505 | WREG32(gen_cntl_reg, gen_cntl_val); | 506 | WREG32(gen_cntl_reg, gen_cntl_val); |
506 | 507 | ||
507 | crtc_offset = (u32)base; | 508 | crtc_offset = (u32)base; |