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authorAlex Deucher <alexdeucher@gmail.com>2010-11-22 17:56:23 -0500
committerDave Airlie <airlied@redhat.com>2010-11-22 18:23:20 -0500
commit4e8c65a1f9ee1a976d95c1d5d2027761aba2f1c3 (patch)
treeda1ea241cc8d5a37e4368b508ad06b97e56e1a65 /drivers/gpu/drm/radeon/radeon_encoders.c
parent2f062fda4f83932b87b3b6c903eeade43422245a (diff)
drm/radeon/kms: atom changes for DCE4.1 devices
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_encoders.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c25
1 files changed, 21 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 041943df966..806d552299b 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -713,7 +713,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
714 * 714 *
715 * DCE 4.0 715 * DCE 4.0
716 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). 716 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
717 * Supports up to 6 digital outputs 717 * Supports up to 6 digital outputs
718 * - 6 DIG encoder blocks. 718 * - 6 DIG encoder blocks.
719 * - DIG to PHY mapping is hardcoded 719 * - DIG to PHY mapping is hardcoded
@@ -724,6 +724,12 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
724 * DIG5 drives UNIPHY2 link A, A+B 724 * DIG5 drives UNIPHY2 link A, A+B
725 * DIG6 drives UNIPHY2 link B 725 * DIG6 drives UNIPHY2 link B
726 * 726 *
727 * DCE 4.1
728 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
729 * Supports up to 6 digital outputs
730 * - 2 DIG encoder blocks.
731 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
732 *
727 * Routing 733 * Routing
728 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 734 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
729 * Examples: 735 * Examples:
@@ -904,9 +910,15 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
904 else 910 else
905 args.v3.ucLaneNum = 4; 911 args.v3.ucLaneNum = 4;
906 912
907 if (dig->linkb) { 913 if (ASIC_IS_DCE41(rdev)) {
908 args.v3.acConfig.ucLinkSel = 1; 914 args.v3.acConfig.ucEncoderSel = dig->dig_encoder;
909 args.v3.acConfig.ucEncoderSel = 1; 915 if (dig->linkb)
916 args.v3.acConfig.ucLinkSel = 1;
917 } else {
918 if (dig->linkb) {
919 args.v3.acConfig.ucLinkSel = 1;
920 args.v3.acConfig.ucEncoderSel = 1;
921 }
910 } 922 }
911 923
912 /* Select the PLL for the PHY 924 /* Select the PLL for the PHY
@@ -1483,6 +1495,11 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1483 struct radeon_encoder_atom_dig *dig; 1495 struct radeon_encoder_atom_dig *dig;
1484 uint32_t dig_enc_in_use = 0; 1496 uint32_t dig_enc_in_use = 0;
1485 1497
1498 /* on DCE41 and encoder can driver any phy so just crtc id */
1499 if (ASIC_IS_DCE41(rdev)) {
1500 return radeon_crtc->crtc_id;
1501 }
1502
1486 if (ASIC_IS_DCE4(rdev)) { 1503 if (ASIC_IS_DCE4(rdev)) {
1487 dig = radeon_encoder->enc_priv; 1504 dig = radeon_encoder->enc_priv;
1488 switch (radeon_encoder->encoder_id) { 1505 switch (radeon_encoder->encoder_id) {