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authorAlex Deucher <alexdeucher@gmail.com>2010-04-22 12:52:11 -0400
committerDave Airlie <airlied@redhat.com>2010-05-18 04:20:49 -0400
commit2031f77ca9c17133869b265210418959a909d259 (patch)
tree21fc2aedea8f3c80c4de1d7b1168479bc7a1ce98 /drivers/gpu/drm/radeon/r600.c
parentdef9ba9cf6a8266ee1ffd72556db002c3a2663db (diff)
drm/radeon/kms: add support for gui idle interrupts (v4)
Useful for certain power management operations. You need to wait for the GUI engine (2D, 3D, CP, etc.) to be idle before changing clocks or adjusting engine parameters. (v2) Fix gui idle enable on pre-r6xx asics (v3) The gui idle interrrupt status bit is permanently asserted on pre-r6xx chips, but the interrrupt is still generated. workaround it in the driver. (v4) Add support for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1c85dcb168a..094c29dd96e 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2535,6 +2535,7 @@ int r600_irq_set(struct radeon_device *rdev)
2535 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 2535 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2536 u32 mode_int = 0; 2536 u32 mode_int = 0;
2537 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 2537 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2538 u32 grbm_int_cntl = 0;
2538 u32 hdmi1, hdmi2; 2539 u32 hdmi1, hdmi2;
2539 2540
2540 if (!rdev->irq.installed) { 2541 if (!rdev->irq.installed) {
@@ -2611,9 +2612,14 @@ int r600_irq_set(struct radeon_device *rdev)
2611 DRM_DEBUG("r600_irq_set: hdmi 2\n"); 2612 DRM_DEBUG("r600_irq_set: hdmi 2\n");
2612 hdmi2 |= R600_HDMI_INT_EN; 2613 hdmi2 |= R600_HDMI_INT_EN;
2613 } 2614 }
2615 if (rdev->irq.gui_idle) {
2616 DRM_DEBUG("gui idle\n");
2617 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2618 }
2614 2619
2615 WREG32(CP_INT_CNTL, cp_int_cntl); 2620 WREG32(CP_INT_CNTL, cp_int_cntl);
2616 WREG32(DxMODE_INT_MASK, mode_int); 2621 WREG32(DxMODE_INT_MASK, mode_int);
2622 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2617 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1); 2623 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
2618 if (ASIC_IS_DCE3(rdev)) { 2624 if (ASIC_IS_DCE3(rdev)) {
2619 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2); 2625 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
@@ -2929,6 +2935,11 @@ restart_ih:
2929 case 181: /* CP EOP event */ 2935 case 181: /* CP EOP event */
2930 DRM_DEBUG("IH: CP EOP\n"); 2936 DRM_DEBUG("IH: CP EOP\n");
2931 break; 2937 break;
2938 case 233: /* GUI IDLE */
2939 DRM_DEBUG("IH: CP EOP\n");
2940 rdev->pm.gui_idle = true;
2941 wake_up(&rdev->irq.idle_queue);
2942 break;
2932 default: 2943 default:
2933 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2944 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2934 break; 2945 break;