aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/r300.c
diff options
context:
space:
mode:
authorDave Airlie <airlied@redhat.com>2009-08-12 04:43:14 -0400
committerDave Airlie <airlied@redhat.com>2009-08-15 18:36:34 -0400
commitde1b28989edff519d0548ebaa3f94fd3d1524cf2 (patch)
treeea8bed0a409ced13c31ff68c62cf89e2b4cfd8b8 /drivers/gpu/drm/radeon/r300.c
parent7ed220d738cf16adff6bc3b31ad25b8848a2fa9c (diff)
drm/radeon/kms: cut down indirects in register accesses.
We really don't want to be doing all these indirects, updating the GPU gart table is something we do often so the less overhead the better. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r300.c')
-rw-r--r--drivers/gpu/drm/radeon/r300.c23
1 files changed, 1 insertions, 22 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 8594486e162..c47579dcafa 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -83,8 +83,8 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
83 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 83 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
84 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 84 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
85 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 85 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
86 mb();
87 } 86 }
87 mb();
88} 88}
89 89
90int rv370_pcie_gart_enable(struct radeon_device *rdev) 90int rv370_pcie_gart_enable(struct radeon_device *rdev)
@@ -593,27 +593,6 @@ void r300_vram_info(struct radeon_device *rdev)
593 593
594 594
595/* 595/*
596 * Indirect registers accessor
597 */
598uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
599{
600 uint32_t r;
601
602 WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff));
603 (void)RREG32(RADEON_PCIE_INDEX);
604 r = RREG32(RADEON_PCIE_DATA);
605 return r;
606}
607
608void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
609{
610 WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff));
611 (void)RREG32(RADEON_PCIE_INDEX);
612 WREG32(RADEON_PCIE_DATA, (v));
613 (void)RREG32(RADEON_PCIE_DATA);
614}
615
616/*
617 * PCIE Lanes 596 * PCIE Lanes
618 */ 597 */
619 598