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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-16 13:30:17 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-16 13:30:17 -0500
commitc5113e3d66d7c7140fe854c7638a27eb3a23fd7d (patch)
tree9247edfcfa87132e15a277d6f2359b303c24da29 /drivers/gpu/drm/radeon/r100_track.h
parent9b2831704e9250269032e3b8c2ffdfca09fd2851 (diff)
parentd785d78bbdb53580b12c40e820af5a3281ce2fc8 (diff)
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon/kms: fix r100->r500 CS checker for compressed textures. (v2) drm/radeon/kms: allow for texture tiling drm/radeon/kms: init pm on all chipsets drm/radeon/kms: HDMI support for R600 KMS drm/radeon/kms: make sure mc is initialized before mapping blit bo drm/radeon/kms: Return to userspace on ERESTARTSYS drm/radeon/gem: don't leak a gem object if reserve fails on get tiling (v2) drm/radeon/kms: don't report allocate failure on ERESTARTSYS drm/radeon/kms: Check if bo we got from ttm are radeon object or not drm/radeon/kms: If no placement is supplied fallback to system drm/ttm: Fix memory type manager debug information printing drm/ttm: Fix printk format & compute bo->mem.size at bo initialization drm/ttm: Fix potential ttm_mem_evict_first races. drm/ttm: Delayed delete fixes. drm/ttm: fix two bugs in new placement routines. drm/ttm: fix incorrect logic in ttm_bo_io path drm/nouveau: remove use of -ERESTART nouveau: Fix endianness with new context program loader drm/nouveau: fix build with CONFIG_AGP=n drm/nouveau: fix ch7006 build
Diffstat (limited to 'drivers/gpu/drm/radeon/r100_track.h')
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index ca50903dd2b..7188c3778ee 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -28,6 +28,10 @@ struct r100_cs_cube_info {
28 unsigned height; 28 unsigned height;
29}; 29};
30 30
31#define R100_TRACK_COMP_NONE 0
32#define R100_TRACK_COMP_DXT1 1
33#define R100_TRACK_COMP_DXT35 2
34
31struct r100_cs_track_texture { 35struct r100_cs_track_texture {
32 struct radeon_bo *robj; 36 struct radeon_bo *robj;
33 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 37 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
@@ -44,6 +48,7 @@ struct r100_cs_track_texture {
44 bool enabled; 48 bool enabled;
45 bool roundup_w; 49 bool roundup_w;
46 bool roundup_h; 50 bool roundup_h;
51 unsigned compress_format;
47}; 52};
48 53
49struct r100_cs_track_limits { 54struct r100_cs_track_limits {