diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-09-01 01:24:28 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-09-24 02:19:55 -0400 |
commit | 479dcaea09bf17e8de7005015345e4266723666d (patch) | |
tree | 46b30ebfb01f25687cf3ab63cfcde7352c122318 /drivers/gpu/drm/nouveau/nouveau_object.c | |
parent | 2a7fdb2bc15b3bfc824eb969b3dc7efa3fb52463 (diff) |
drm/nouveau: move ramht code out of nouveau_object.c, nothing to see here
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_object.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_object.c | 132 |
1 files changed, 1 insertions, 131 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c index b6bcb254f4a..e658aa2dbe6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_object.c +++ b/drivers/gpu/drm/nouveau/nouveau_object.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include "drm.h" | 34 | #include "drm.h" |
35 | #include "nouveau_drv.h" | 35 | #include "nouveau_drv.h" |
36 | #include "nouveau_drm.h" | 36 | #include "nouveau_drm.h" |
37 | #include "nouveau_ramht.h" | ||
37 | 38 | ||
38 | /* NVidia uses context objects to drive drawing operations. | 39 | /* NVidia uses context objects to drive drawing operations. |
39 | 40 | ||
@@ -65,137 +66,6 @@ | |||
65 | The key into the hash table depends on the object handle and channel id and | 66 | The key into the hash table depends on the object handle and channel id and |
66 | is given as: | 67 | is given as: |
67 | */ | 68 | */ |
68 | static uint32_t | ||
69 | nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) | ||
70 | { | ||
71 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
72 | uint32_t hash = 0; | ||
73 | int i; | ||
74 | |||
75 | NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle); | ||
76 | |||
77 | for (i = 32; i > 0; i -= dev_priv->ramht_bits) { | ||
78 | hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1)); | ||
79 | handle >>= dev_priv->ramht_bits; | ||
80 | } | ||
81 | |||
82 | if (dev_priv->card_type < NV_50) | ||
83 | hash ^= channel << (dev_priv->ramht_bits - 4); | ||
84 | hash <<= 3; | ||
85 | |||
86 | NV_DEBUG(dev, "hash=0x%08x\n", hash); | ||
87 | return hash; | ||
88 | } | ||
89 | |||
90 | static int | ||
91 | nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht, | ||
92 | uint32_t offset) | ||
93 | { | ||
94 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
95 | uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4); | ||
96 | |||
97 | if (dev_priv->card_type < NV_40) | ||
98 | return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0); | ||
99 | return (ctx != 0); | ||
100 | } | ||
101 | |||
102 | static int | ||
103 | nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) | ||
104 | { | ||
105 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
106 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; | ||
107 | struct nouveau_channel *chan = ref->channel; | ||
108 | struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; | ||
109 | uint32_t ctx, co, ho; | ||
110 | |||
111 | if (!ramht) { | ||
112 | NV_ERROR(dev, "No hash table!\n"); | ||
113 | return -EINVAL; | ||
114 | } | ||
115 | |||
116 | if (dev_priv->card_type < NV_40) { | ||
117 | ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) | | ||
118 | (chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) | | ||
119 | (ref->gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT); | ||
120 | } else | ||
121 | if (dev_priv->card_type < NV_50) { | ||
122 | ctx = (ref->instance >> 4) | | ||
123 | (chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) | | ||
124 | (ref->gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); | ||
125 | } else { | ||
126 | if (ref->gpuobj->engine == NVOBJ_ENGINE_DISPLAY) { | ||
127 | ctx = (ref->instance << 10) | 2; | ||
128 | } else { | ||
129 | ctx = (ref->instance >> 4) | | ||
130 | ((ref->gpuobj->engine << | ||
131 | NV40_RAMHT_CONTEXT_ENGINE_SHIFT)); | ||
132 | } | ||
133 | } | ||
134 | |||
135 | co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle); | ||
136 | do { | ||
137 | if (!nouveau_ramht_entry_valid(dev, ramht, co)) { | ||
138 | NV_DEBUG(dev, | ||
139 | "insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n", | ||
140 | chan->id, co, ref->handle, ctx); | ||
141 | nv_wo32(dev, ramht, (co + 0)/4, ref->handle); | ||
142 | nv_wo32(dev, ramht, (co + 4)/4, ctx); | ||
143 | |||
144 | list_add_tail(&ref->list, &chan->ramht_refs); | ||
145 | instmem->flush(dev); | ||
146 | return 0; | ||
147 | } | ||
148 | NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n", | ||
149 | chan->id, co, nv_ro32(dev, ramht, co/4)); | ||
150 | |||
151 | co += 8; | ||
152 | if (co >= dev_priv->ramht_size) | ||
153 | co = 0; | ||
154 | } while (co != ho); | ||
155 | |||
156 | NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id); | ||
157 | return -ENOMEM; | ||
158 | } | ||
159 | |||
160 | static void | ||
161 | nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) | ||
162 | { | ||
163 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
164 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; | ||
165 | struct nouveau_channel *chan = ref->channel; | ||
166 | struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; | ||
167 | uint32_t co, ho; | ||
168 | |||
169 | if (!ramht) { | ||
170 | NV_ERROR(dev, "No hash table!\n"); | ||
171 | return; | ||
172 | } | ||
173 | |||
174 | co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle); | ||
175 | do { | ||
176 | if (nouveau_ramht_entry_valid(dev, ramht, co) && | ||
177 | (ref->handle == nv_ro32(dev, ramht, (co/4)))) { | ||
178 | NV_DEBUG(dev, | ||
179 | "remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n", | ||
180 | chan->id, co, ref->handle, | ||
181 | nv_ro32(dev, ramht, (co + 4))); | ||
182 | nv_wo32(dev, ramht, (co + 0)/4, 0x00000000); | ||
183 | nv_wo32(dev, ramht, (co + 4)/4, 0x00000000); | ||
184 | |||
185 | list_del(&ref->list); | ||
186 | instmem->flush(dev); | ||
187 | return; | ||
188 | } | ||
189 | |||
190 | co += 8; | ||
191 | if (co >= dev_priv->ramht_size) | ||
192 | co = 0; | ||
193 | } while (co != ho); | ||
194 | list_del(&ref->list); | ||
195 | |||
196 | NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n", | ||
197 | chan->id, ref->handle); | ||
198 | } | ||
199 | 69 | ||
200 | int | 70 | int |
201 | nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, | 71 | nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, |