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authorFrancisco Jerez <currojerez@riseup.net>2010-08-26 17:07:02 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-09-24 02:17:59 -0400
commit4295f188e8297660b498e021caee430a40558d8b (patch)
tree9cec49772202a50ed168c0215a48f6b22f79fc16 /drivers/gpu/drm/nouveau/nouveau_calc.c
parent316f60a120a8f1dacb574f705d5faf7eac3e6e2a (diff)
drm/nv20: Use the nv30 CRTC bandwidth calculation code.
nv2x CRTC FIFOs are as large as in nv3x (4kB it seems), and the FIFO control registers have the same layout: we can make them share the same implementation. Previously we were using the nv1x code, but the calculated FIFO watermarks are usually too low for nv2x and they cause horrible scanout artifacts. They've gone unnoticed until now because we've been leaving one of the bandwidth regs uninitialized (CRE 47, which contains the most significant bits of FFLWM), so everything seemed to work fine except in some cases after a cold boot, depending on the memory bandwidth and pixel clocks used. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_calc.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_calc.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_calc.c b/drivers/gpu/drm/nouveau/nouveau_calc.c
index ca85da78484..23d9896962f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_calc.c
+++ b/drivers/gpu/drm/nouveau/nouveau_calc.c
@@ -234,7 +234,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
234} 234}
235 235
236static void 236static void
237nv30_update_arb(int *burst, int *lwm) 237nv20_update_arb(int *burst, int *lwm)
238{ 238{
239 unsigned int fifo_size, burst_size, graphics_lwm; 239 unsigned int fifo_size, burst_size, graphics_lwm;
240 240
@@ -251,14 +251,14 @@ nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm
251{ 251{
252 struct drm_nouveau_private *dev_priv = dev->dev_private; 252 struct drm_nouveau_private *dev_priv = dev->dev_private;
253 253
254 if (dev_priv->card_type < NV_30) 254 if (dev_priv->card_type < NV_20)
255 nv04_update_arb(dev, vclk, bpp, burst, lwm); 255 nv04_update_arb(dev, vclk, bpp, burst, lwm);
256 else if ((dev->pci_device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ || 256 else if ((dev->pci_device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
257 (dev->pci_device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) { 257 (dev->pci_device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
258 *burst = 128; 258 *burst = 128;
259 *lwm = 0x0480; 259 *lwm = 0x0480;
260 } else 260 } else
261 nv30_update_arb(burst, lwm); 261 nv20_update_arb(burst, lwm);
262} 262}
263 263
264static int 264static int