drm/i915: add FIFO watermark support

This patch from jbarnes and myself adds FIFO watermark control to the
driver.  This is needed for both power saving features on new platforms
with the so-called "big FIFO" and for controlling FIFO allocation
between pipes in multi-head configurations.

It's also necessary infrastructure to support things like framebuffer
compression and configuration supportability checks (i.e. checking a
configuration against available bandwidth).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 40 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f83364974a8..6096600aff6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1082,6 +1082,44 @@ void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
         master->driver_priv = NULL;
 }
 
+static void i915_get_mem_freq(struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        u32 tmp;
+
+        if (!IS_IGD(dev))
+                return;
+
+        tmp = I915_READ(CLKCFG);
+
+        switch (tmp & CLKCFG_FSB_MASK) {
+        case CLKCFG_FSB_533:
+                dev_priv->fsb_freq = 533; /* 133*4 */
+                break;
+        case CLKCFG_FSB_800:
+                dev_priv->fsb_freq = 800; /* 200*4 */
+                break;
+        case CLKCFG_FSB_667:
+                dev_priv->fsb_freq =  667; /* 167*4 */
+                break;
+        case CLKCFG_FSB_400:
+                dev_priv->fsb_freq = 400; /* 100*4 */
+                break;
+        }
+
+        switch (tmp & CLKCFG_MEM_MASK) {
+        case CLKCFG_MEM_533:
+                dev_priv->mem_freq = 533;
+                break;
+        case CLKCFG_MEM_667:
+                dev_priv->mem_freq = 667;
+                break;
+        case CLKCFG_MEM_800:
+                dev_priv->mem_freq = 800;
+                break;
+        }
+}
+
 /**
  * i915_driver_load - setup chip and create an initial config
  * @dev: DRM device
@@ -1165,6 +1203,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                         goto out_iomapfree;
         }
 
+        i915_get_mem_freq(dev);
+
         /* On the 945G/GM, the chipset reports the MSI capability on the
          * integrated graphics even though the support isn't actually there
          * according to the published specs.  It doesn't appear to function