diff options
author | Chris Leech <christopher.leech@intel.com> | 2007-03-08 12:57:35 -0500 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2007-07-11 18:39:04 -0400 |
commit | e38288117c50fe22ed1693c2d8397245bb7e1a53 (patch) | |
tree | a3189299b0056bb109fb7d306d5d0574c621a0a0 /drivers/dma/ioatdma.c | |
parent | ff487fb773749124550a5ad2b7fbfe0376af6f0d (diff) |
ioatdma: Remove the wrappers around read(bwl)/write(bwl) in ioatdma
Signed-off-by: Chris Leech <christopher.leech@intel.com>
Diffstat (limited to 'drivers/dma/ioatdma.c')
-rw-r--r-- | drivers/dma/ioatdma.c | 60 |
1 files changed, 28 insertions, 32 deletions
diff --git a/drivers/dma/ioatdma.c b/drivers/dma/ioatdma.c index 4e6afd75203..275707097bf 100644 --- a/drivers/dma/ioatdma.c +++ b/drivers/dma/ioatdma.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include <linux/delay.h> | 32 | #include <linux/delay.h> |
33 | #include <linux/dma-mapping.h> | 33 | #include <linux/dma-mapping.h> |
34 | #include "ioatdma.h" | 34 | #include "ioatdma.h" |
35 | #include "ioatdma_io.h" | ||
36 | #include "ioatdma_registers.h" | 35 | #include "ioatdma_registers.h" |
37 | #include "ioatdma_hw.h" | 36 | #include "ioatdma_hw.h" |
38 | 37 | ||
@@ -51,8 +50,8 @@ static int enumerate_dma_channels(struct ioat_device *device) | |||
51 | int i; | 50 | int i; |
52 | struct ioat_dma_chan *ioat_chan; | 51 | struct ioat_dma_chan *ioat_chan; |
53 | 52 | ||
54 | device->common.chancnt = ioatdma_read8(device, IOAT_CHANCNT_OFFSET); | 53 | device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); |
55 | xfercap_scale = ioatdma_read8(device, IOAT_XFERCAP_OFFSET); | 54 | xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); |
56 | xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); | 55 | xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); |
57 | 56 | ||
58 | for (i = 0; i < device->common.chancnt; i++) { | 57 | for (i = 0; i < device->common.chancnt; i++) { |
@@ -123,7 +122,7 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) | |||
123 | * In-use bit automatically set by reading chanctrl | 122 | * In-use bit automatically set by reading chanctrl |
124 | * If 0, we got it, if 1, someone else did | 123 | * If 0, we got it, if 1, someone else did |
125 | */ | 124 | */ |
126 | chanctrl = ioatdma_chan_read16(ioat_chan, IOAT_CHANCTRL_OFFSET); | 125 | chanctrl = readw(ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); |
127 | if (chanctrl & IOAT_CHANCTRL_CHANNEL_IN_USE) | 126 | if (chanctrl & IOAT_CHANCTRL_CHANNEL_IN_USE) |
128 | return -EBUSY; | 127 | return -EBUSY; |
129 | 128 | ||
@@ -132,12 +131,12 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) | |||
132 | IOAT_CHANCTRL_ERR_INT_EN | | 131 | IOAT_CHANCTRL_ERR_INT_EN | |
133 | IOAT_CHANCTRL_ANY_ERR_ABORT_EN | | 132 | IOAT_CHANCTRL_ANY_ERR_ABORT_EN | |
134 | IOAT_CHANCTRL_ERR_COMPLETION_EN; | 133 | IOAT_CHANCTRL_ERR_COMPLETION_EN; |
135 | ioatdma_chan_write16(ioat_chan, IOAT_CHANCTRL_OFFSET, chanctrl); | 134 | writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); |
136 | 135 | ||
137 | chanerr = ioatdma_chan_read32(ioat_chan, IOAT_CHANERR_OFFSET); | 136 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
138 | if (chanerr) { | 137 | if (chanerr) { |
139 | printk("IOAT: CHANERR = %x, clearing\n", chanerr); | 138 | printk("IOAT: CHANERR = %x, clearing\n", chanerr); |
140 | ioatdma_chan_write32(ioat_chan, IOAT_CHANERR_OFFSET, chanerr); | 139 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
141 | } | 140 | } |
142 | 141 | ||
143 | /* Allocate descriptors */ | 142 | /* Allocate descriptors */ |
@@ -161,10 +160,10 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) | |||
161 | &ioat_chan->completion_addr); | 160 | &ioat_chan->completion_addr); |
162 | memset(ioat_chan->completion_virt, 0, | 161 | memset(ioat_chan->completion_virt, 0, |
163 | sizeof(*ioat_chan->completion_virt)); | 162 | sizeof(*ioat_chan->completion_virt)); |
164 | ioatdma_chan_write32(ioat_chan, IOAT_CHANCMP_OFFSET_LOW, | 163 | writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF, |
165 | ((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF); | 164 | ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); |
166 | ioatdma_chan_write32(ioat_chan, IOAT_CHANCMP_OFFSET_HIGH, | 165 | writel(((u64) ioat_chan->completion_addr) >> 32, |
167 | ((u64) ioat_chan->completion_addr) >> 32); | 166 | ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); |
168 | 167 | ||
169 | ioat_start_null_desc(ioat_chan); | 168 | ioat_start_null_desc(ioat_chan); |
170 | return i; | 169 | return i; |
@@ -182,7 +181,7 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) | |||
182 | 181 | ||
183 | ioat_dma_memcpy_cleanup(ioat_chan); | 182 | ioat_dma_memcpy_cleanup(ioat_chan); |
184 | 183 | ||
185 | ioatdma_chan_write8(ioat_chan, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_RESET); | 184 | writeb(IOAT_CHANCMD_RESET, ioat_chan->reg_base + IOAT_CHANCMD_OFFSET); |
186 | 185 | ||
187 | spin_lock_bh(&ioat_chan->desc_lock); | 186 | spin_lock_bh(&ioat_chan->desc_lock); |
188 | list_for_each_entry_safe(desc, _desc, &ioat_chan->used_desc, node) { | 187 | list_for_each_entry_safe(desc, _desc, &ioat_chan->used_desc, node) { |
@@ -210,9 +209,9 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) | |||
210 | ioat_chan->last_completion = ioat_chan->completion_addr = 0; | 209 | ioat_chan->last_completion = ioat_chan->completion_addr = 0; |
211 | 210 | ||
212 | /* Tell hw the chan is free */ | 211 | /* Tell hw the chan is free */ |
213 | chanctrl = ioatdma_chan_read16(ioat_chan, IOAT_CHANCTRL_OFFSET); | 212 | chanctrl = readw(ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); |
214 | chanctrl &= ~IOAT_CHANCTRL_CHANNEL_IN_USE; | 213 | chanctrl &= ~IOAT_CHANCTRL_CHANNEL_IN_USE; |
215 | ioatdma_chan_write16(ioat_chan, IOAT_CHANCTRL_OFFSET, chanctrl); | 214 | writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); |
216 | } | 215 | } |
217 | 216 | ||
218 | /** | 217 | /** |
@@ -318,9 +317,8 @@ static dma_cookie_t do_ioat_dma_memcpy(struct ioat_dma_chan *ioat_chan, | |||
318 | spin_unlock_bh(&ioat_chan->desc_lock); | 317 | spin_unlock_bh(&ioat_chan->desc_lock); |
319 | 318 | ||
320 | if (append) | 319 | if (append) |
321 | ioatdma_chan_write8(ioat_chan, | 320 | writeb(IOAT_CHANCMD_APPEND, |
322 | IOAT_CHANCMD_OFFSET, | 321 | ioat_chan->reg_base + IOAT_CHANCMD_OFFSET); |
323 | IOAT_CHANCMD_APPEND); | ||
324 | return cookie; | 322 | return cookie; |
325 | } | 323 | } |
326 | 324 | ||
@@ -417,9 +415,8 @@ static void ioat_dma_memcpy_issue_pending(struct dma_chan *chan) | |||
417 | 415 | ||
418 | if (ioat_chan->pending != 0) { | 416 | if (ioat_chan->pending != 0) { |
419 | ioat_chan->pending = 0; | 417 | ioat_chan->pending = 0; |
420 | ioatdma_chan_write8(ioat_chan, | 418 | writeb(IOAT_CHANCMD_APPEND, |
421 | IOAT_CHANCMD_OFFSET, | 419 | ioat_chan->reg_base + IOAT_CHANCMD_OFFSET); |
422 | IOAT_CHANCMD_APPEND); | ||
423 | } | 420 | } |
424 | } | 421 | } |
425 | 422 | ||
@@ -449,7 +446,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *chan) | |||
449 | if ((chan->completion_virt->full & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == | 446 | if ((chan->completion_virt->full & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == |
450 | IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { | 447 | IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { |
451 | printk("IOAT: Channel halted, chanerr = %x\n", | 448 | printk("IOAT: Channel halted, chanerr = %x\n", |
452 | ioatdma_chan_read32(chan, IOAT_CHANERR_OFFSET)); | 449 | readl(chan->reg_base + IOAT_CHANERR_OFFSET)); |
453 | 450 | ||
454 | /* TODO do something to salvage the situation */ | 451 | /* TODO do something to salvage the situation */ |
455 | } | 452 | } |
@@ -569,21 +566,21 @@ static irqreturn_t ioat_do_interrupt(int irq, void *data) | |||
569 | unsigned long attnstatus; | 566 | unsigned long attnstatus; |
570 | u8 intrctrl; | 567 | u8 intrctrl; |
571 | 568 | ||
572 | intrctrl = ioatdma_read8(instance, IOAT_INTRCTRL_OFFSET); | 569 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); |
573 | 570 | ||
574 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) | 571 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) |
575 | return IRQ_NONE; | 572 | return IRQ_NONE; |
576 | 573 | ||
577 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { | 574 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { |
578 | ioatdma_write8(instance, IOAT_INTRCTRL_OFFSET, intrctrl); | 575 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); |
579 | return IRQ_NONE; | 576 | return IRQ_NONE; |
580 | } | 577 | } |
581 | 578 | ||
582 | attnstatus = ioatdma_read32(instance, IOAT_ATTNSTATUS_OFFSET); | 579 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); |
583 | 580 | ||
584 | printk(KERN_ERR "ioatdma error: interrupt! status %lx\n", attnstatus); | 581 | printk(KERN_ERR "ioatdma error: interrupt! status %lx\n", attnstatus); |
585 | 582 | ||
586 | ioatdma_write8(instance, IOAT_INTRCTRL_OFFSET, intrctrl); | 583 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); |
587 | return IRQ_HANDLED; | 584 | return IRQ_HANDLED; |
588 | } | 585 | } |
589 | 586 | ||
@@ -612,14 +609,13 @@ static void ioat_start_null_desc(struct ioat_dma_chan *ioat_chan) | |||
612 | spin_unlock_bh(&ioat_chan->desc_lock); | 609 | spin_unlock_bh(&ioat_chan->desc_lock); |
613 | 610 | ||
614 | #if (BITS_PER_LONG == 64) | 611 | #if (BITS_PER_LONG == 64) |
615 | ioatdma_chan_write64(ioat_chan, IOAT_CHAINADDR_OFFSET, desc->phys); | 612 | writeq(desc->phys, ioat_chan->reg_base + IOAT_CHAINADDR_OFFSET); |
616 | #else | 613 | #else |
617 | ioatdma_chan_write32(ioat_chan, | 614 | writel((u32) desc->phys, |
618 | IOAT_CHAINADDR_OFFSET_LOW, | 615 | ioat_chan->reg_base + IOAT_CHAINADDR_OFFSET_LOW); |
619 | (u32) desc->phys); | 616 | writel(0, ioat_chan->reg_base + IOAT_CHAINADDR_OFFSET_HIGH); |
620 | ioatdma_chan_write32(ioat_chan, IOAT_CHAINADDR_OFFSET_HIGH, 0); | ||
621 | #endif | 617 | #endif |
622 | ioatdma_chan_write8(ioat_chan, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_START); | 618 | writeb(IOAT_CHANCMD_START, ioat_chan->reg_base + IOAT_CHANCMD_OFFSET); |
623 | } | 619 | } |
624 | 620 | ||
625 | /* | 621 | /* |
@@ -748,7 +744,7 @@ static int __devinit ioat_probe(struct pci_dev *pdev, | |||
748 | 744 | ||
749 | device->reg_base = reg_base; | 745 | device->reg_base = reg_base; |
750 | 746 | ||
751 | ioatdma_write8(device, IOAT_INTRCTRL_OFFSET, IOAT_INTRCTRL_MASTER_INT_EN); | 747 | writeb(IOAT_INTRCTRL_MASTER_INT_EN, device->reg_base + IOAT_INTRCTRL_OFFSET); |
752 | pci_set_master(pdev); | 748 | pci_set_master(pdev); |
753 | 749 | ||
754 | INIT_LIST_HEAD(&device->common.channels); | 750 | INIT_LIST_HEAD(&device->common.channels); |