I/OAT: I/OAT version 3.0 support

This patch adds to ioatdma and dca modules
support for Intel I/OAT DMA engine ver.3 (aka CB3 device).
The main features of I/OAT ver.3 are:
 * 8 single channel DMA devices (8 channels total)
 * 8 DCA providers, each can accept 2 requesters
 * 8-bit TAG values and 32-bit extended APIC IDs

Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

1 files changed, 237 insertions, 7 deletions

diff --git a/drivers/dma/ioat_dca.c b/drivers/dma/ioat_dca.c
index 9e922760b7f..6cf622da028 100644
--- a/drivers/dma/ioat_dca.c
+++ b/drivers/dma/ioat_dca.c
@@ -37,12 +37,18 @@
 #include "ioatdma_registers.h"
 
 /*
- * Bit 16 of a tag map entry is the "valid" bit, if it is set then bits 0:15
+ * Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6
  * contain the bit number of the APIC ID to map into the DCA tag.  If the valid
  * bit is not set, then the value must be 0 or 1 and defines the bit in the tag.
  */
 #define DCA_TAG_MAP_VALID 0x80
 
+#define DCA3_TAG_MAP_BIT_TO_INV 0x80
+#define DCA3_TAG_MAP_BIT_TO_SEL 0x40
+#define DCA3_TAG_MAP_LITERAL_VAL 0x1
+
+#define DCA_TAG_MAP_MASK 0xDF
+
 /*
  * "Legacy" DCA systems do not implement the DCA register set in the
  * I/OAT device.  Software needs direct support for their tag mappings.
@@ -95,6 +101,7 @@ struct ioat_dca_slot {
 };
 
 #define IOAT_DCA_MAX_REQ 6
+#define IOAT3_DCA_MAX_REQ 2
 
 struct ioat_dca_priv {
         void __iomem            *iobase;
@@ -171,7 +178,9 @@ static int ioat_dca_remove_requester(struct dca_provider *dca,
         return -ENODEV;
 }
 
-static u8 ioat_dca_get_tag(struct dca_provider *dca, int cpu)
+static u8 ioat_dca_get_tag(struct dca_provider *dca,
+                           struct device *dev,
+                           int cpu)
 {
         struct ioat_dca_priv *ioatdca = dca_priv(dca);
         int i, apic_id, bit, value;
@@ -193,10 +202,26 @@ static u8 ioat_dca_get_tag(struct dca_provider *dca, int cpu)
         return tag;
 }
 
+static int ioat_dca_dev_managed(struct dca_provider *dca,
+                                struct device *dev)
+{
+        struct ioat_dca_priv *ioatdca = dca_priv(dca);
+        struct pci_dev *pdev;
+        int i;
+
+        pdev = to_pci_dev(dev);
+        for (i = 0; i < ioatdca->max_requesters; i++) {
+                if (ioatdca->req_slots[i].pdev == pdev)
+                        return 1;
+        }
+        return 0;
+}
+
 static struct dca_ops ioat_dca_ops = {
         .add_requester          = ioat_dca_add_requester,
         .remove_requester       = ioat_dca_remove_requester,
         .get_tag                = ioat_dca_get_tag,
+        .dev_managed            = ioat_dca_dev_managed,
 };
 
 
@@ -207,6 +232,8 @@ struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase)
         u8 *tag_map = NULL;
         int i;
         int err;
+        u8 version;
+        u8 max_requesters;
 
         if (!system_has_dca_enabled(pdev))
                 return NULL;
@@ -237,15 +264,20 @@ struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase)
         if (tag_map == NULL)
                 return NULL;
 
+        version = readb(iobase + IOAT_VER_OFFSET);
+        if (version == IOAT_VER_3_0)
+                max_requesters = IOAT3_DCA_MAX_REQ;
+        else
+                max_requesters = IOAT_DCA_MAX_REQ;
+
         dca = alloc_dca_provider(&ioat_dca_ops,
                         sizeof(*ioatdca) +
-                        (sizeof(struct ioat_dca_slot) * IOAT_DCA_MAX_REQ));
+                        (sizeof(struct ioat_dca_slot) * max_requesters));
         if (!dca)
                 return NULL;
 
         ioatdca = dca_priv(dca);
-        ioatdca->max_requesters = IOAT_DCA_MAX_REQ;
-
+        ioatdca->max_requesters = max_requesters;
         ioatdca->dca_base = iobase + 0x54;
 
         /* copy over the APIC ID to DCA tag mapping */
@@ -323,11 +355,13 @@ static int ioat2_dca_remove_requester(struct dca_provider *dca,
         return -ENODEV;
 }
 
-static u8 ioat2_dca_get_tag(struct dca_provider *dca, int cpu)
+static u8 ioat2_dca_get_tag(struct dca_provider *dca,
+                            struct device *dev,
+                            int cpu)
 {
         u8 tag;
 
-        tag = ioat_dca_get_tag(dca, cpu);
+        tag = ioat_dca_get_tag(dca, dev, cpu);
         tag = (~tag) & 0x1F;
         return tag;
 }
@@ -336,6 +370,7 @@ static struct dca_ops ioat2_dca_ops = {
         .add_requester          = ioat2_dca_add_requester,
         .remove_requester       = ioat2_dca_remove_requester,
         .get_tag                = ioat2_dca_get_tag,
+        .dev_managed            = ioat_dca_dev_managed,
 };
 
 static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset)
@@ -425,3 +460,198 @@ struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase)
 
         return dca;
 }
+
+static int ioat3_dca_add_requester(struct dca_provider *dca, struct device *dev)
+{
+        struct ioat_dca_priv *ioatdca = dca_priv(dca);
+        struct pci_dev *pdev;
+        int i;
+        u16 id;
+        u16 global_req_table;
+
+        /* This implementation only supports PCI-Express */
+        if (dev->bus != &pci_bus_type)
+                return -ENODEV;
+        pdev = to_pci_dev(dev);
+        id = dcaid_from_pcidev(pdev);
+
+        if (ioatdca->requester_count == ioatdca->max_requesters)
+                return -ENODEV;
+
+        for (i = 0; i < ioatdca->max_requesters; i++) {
+                if (ioatdca->req_slots[i].pdev == NULL) {
+                        /* found an empty slot */
+                        ioatdca->requester_count++;
+                        ioatdca->req_slots[i].pdev = pdev;
+                        ioatdca->req_slots[i].rid = id;
+                        global_req_table =
+                              readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
+                        writel(id | IOAT_DCA_GREQID_VALID,
+                               ioatdca->iobase + global_req_table + (i * 4));
+                        return i;
+                }
+        }
+        /* Error, ioatdma->requester_count is out of whack */
+        return -EFAULT;
+}
+
+static int ioat3_dca_remove_requester(struct dca_provider *dca,
+                                      struct device *dev)
+{
+        struct ioat_dca_priv *ioatdca = dca_priv(dca);
+        struct pci_dev *pdev;
+        int i;
+        u16 global_req_table;
+
+        /* This implementation only supports PCI-Express */
+        if (dev->bus != &pci_bus_type)
+                return -ENODEV;
+        pdev = to_pci_dev(dev);
+
+        for (i = 0; i < ioatdca->max_requesters; i++) {
+                if (ioatdca->req_slots[i].pdev == pdev) {
+                        global_req_table =
+                              readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
+                        writel(0, ioatdca->iobase + global_req_table + (i * 4));
+                        ioatdca->req_slots[i].pdev = NULL;
+                        ioatdca->req_slots[i].rid = 0;
+                        ioatdca->requester_count--;
+                        return i;
+                }
+        }
+        return -ENODEV;
+}
+
+static u8 ioat3_dca_get_tag(struct dca_provider *dca,
+                            struct device *dev,
+                            int cpu)
+{
+        u8 tag;
+
+        struct ioat_dca_priv *ioatdca = dca_priv(dca);
+        int i, apic_id, bit, value;
+        u8 entry;
+
+        tag = 0;
+        apic_id = cpu_physical_id(cpu);
+
+        for (i = 0; i < IOAT_TAG_MAP_LEN; i++) {
+                entry = ioatdca->tag_map[i];
+                if (entry & DCA3_TAG_MAP_BIT_TO_SEL) {
+                        bit = entry &
+                                ~(DCA3_TAG_MAP_BIT_TO_SEL | DCA3_TAG_MAP_BIT_TO_INV);
+                        value = (apic_id & (1 << bit)) ? 1 : 0;
+                } else if (entry & DCA3_TAG_MAP_BIT_TO_INV) {
+                        bit = entry & ~DCA3_TAG_MAP_BIT_TO_INV;
+                        value = (apic_id & (1 << bit)) ? 0 : 1;
+                } else {
+                        value = (entry & DCA3_TAG_MAP_LITERAL_VAL) ? 1 : 0;
+                }
+                tag |= (value << i);
+        }
+
+        return tag;
+}
+
+static struct dca_ops ioat3_dca_ops = {
+        .add_requester          = ioat3_dca_add_requester,
+        .remove_requester       = ioat3_dca_remove_requester,
+        .get_tag                = ioat3_dca_get_tag,
+        .dev_managed            = ioat_dca_dev_managed,
+};
+
+static int ioat3_dca_count_dca_slots(void *iobase, u16 dca_offset)
+{
+        int slots = 0;
+        u32 req;
+        u16 global_req_table;
+
+        global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET);
+        if (global_req_table == 0)
+                return 0;
+
+        do {
+                req = readl(iobase + global_req_table + (slots * sizeof(u32)));
+                slots++;
+        } while ((req & IOAT_DCA_GREQID_LASTID) == 0);
+
+        return slots;
+}
+
+struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase)
+{
+        struct dca_provider *dca;
+        struct ioat_dca_priv *ioatdca;
+        int slots;
+        int i;
+        int err;
+        u16 dca_offset;
+        u16 csi_fsb_control;
+        u16 pcie_control;
+        u8 bit;
+
+        union {
+                u64 full;
+                struct {
+                        u32 low;
+                        u32 high;
+                };
+        } tag_map;
+
+        if (!system_has_dca_enabled(pdev))
+                return NULL;
+
+        dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
+        if (dca_offset == 0)
+                return NULL;
+
+        slots = ioat3_dca_count_dca_slots(iobase, dca_offset);
+        if (slots == 0)
+                return NULL;
+
+        dca = alloc_dca_provider(&ioat3_dca_ops,
+                                 sizeof(*ioatdca)
+                                      + (sizeof(struct ioat_dca_slot) * slots));
+        if (!dca)
+                return NULL;
+
+        ioatdca = dca_priv(dca);
+        ioatdca->iobase = iobase;
+        ioatdca->dca_base = iobase + dca_offset;
+        ioatdca->max_requesters = slots;
+
+        /* some bios might not know to turn these on */
+        csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
+        if ((csi_fsb_control & IOAT3_CSI_CONTROL_PREFETCH) == 0) {
+                csi_fsb_control |= IOAT3_CSI_CONTROL_PREFETCH;
+                writew(csi_fsb_control,
+                       ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
+        }
+        pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
+        if ((pcie_control & IOAT3_PCI_CONTROL_MEMWR) == 0) {
+                pcie_control |= IOAT3_PCI_CONTROL_MEMWR;
+                writew(pcie_control,
+                       ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
+        }
+
+
+        /* TODO version, compatibility and configuration checks */
+
+        /* copy out the APIC to DCA tag map */
+        tag_map.low =
+                readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW);
+        tag_map.high =
+                readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH);
+        for (i = 0; i < 8; i++) {
+                bit = tag_map.full >> (8 * i);
+                ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK;
+        }
+
+        err = register_dca_provider(dca, &pdev->dev);
+        if (err) {
+                free_dca_provider(dca);
+                return NULL;
+        }
+
+        return dca;
+}