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authorMark Lord <liml@rtr.ca>2007-11-07 10:52:55 -0500
committerJeff Garzik <jeff@garzik.org>2007-11-08 13:08:41 -0500
commit12ee7d3ceb08e9ab99a6c17c5c6a387645a32658 (patch)
tree5a67ff8aa4f46a9fd82dec3d738fe13ce9e86e37 /drivers/ata/sata_qstor.c
parent647c595dadb20d2c46e18bbd8d2a11e32f2a46e1 (diff)
libata sata_qstor nuke idle state
sata_qstor nuke idle state. We're really only ever in one of two hardware states: packet, or mmio. Get rid of unnecessary "qs_state_idle" state. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/sata_qstor.c')
-rw-r--r--drivers/ata/sata_qstor.c15
1 files changed, 4 insertions, 11 deletions
diff --git a/drivers/ata/sata_qstor.c b/drivers/ata/sata_qstor.c
index 6d43ba79e15..9d3128ca344 100644
--- a/drivers/ata/sata_qstor.c
+++ b/drivers/ata/sata_qstor.c
@@ -103,7 +103,7 @@ enum {
103 QS_DMA_BOUNDARY = ~0UL 103 QS_DMA_BOUNDARY = ~0UL
104}; 104};
105 105
106typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t; 106typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
107 107
108struct qs_port_priv { 108struct qs_port_priv {
109 u8 *pkt; 109 u8 *pkt;
@@ -219,7 +219,9 @@ static void qs_irq_clear(struct ata_port *ap)
219static inline void qs_enter_reg_mode(struct ata_port *ap) 219static inline void qs_enter_reg_mode(struct ata_port *ap)
220{ 220{
221 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000); 221 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
222 struct qs_port_priv *pp = ap->private_data;
222 223
224 pp->state = qs_state_mmio;
223 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); 225 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
224 readb(chan + QS_CCT_CTR0); /* flush */ 226 readb(chan + QS_CCT_CTR0); /* flush */
225} 227}
@@ -235,19 +237,12 @@ static inline void qs_reset_channel_logic(struct ata_port *ap)
235 237
236static void qs_phy_reset(struct ata_port *ap) 238static void qs_phy_reset(struct ata_port *ap)
237{ 239{
238 struct qs_port_priv *pp = ap->private_data;
239
240 pp->state = qs_state_idle;
241 qs_reset_channel_logic(ap); 240 qs_reset_channel_logic(ap);
242 sata_phy_reset(ap); 241 sata_phy_reset(ap);
243} 242}
244 243
245static void qs_eng_timeout(struct ata_port *ap) 244static void qs_eng_timeout(struct ata_port *ap)
246{ 245{
247 struct qs_port_priv *pp = ap->private_data;
248
249 if (pp->state != qs_state_idle) /* healthy paranoia */
250 pp->state = qs_state_mmio;
251 qs_reset_channel_logic(ap); 246 qs_reset_channel_logic(ap);
252 ata_eng_timeout(ap); 247 ata_eng_timeout(ap);
253} 248}
@@ -406,7 +401,6 @@ static inline unsigned int qs_intr_pkt(struct ata_host *host)
406 switch (sHST) { 401 switch (sHST) {
407 case 0: /* successful CPB */ 402 case 0: /* successful CPB */
408 case 3: /* device error */ 403 case 3: /* device error */
409 pp->state = qs_state_idle;
410 qs_enter_reg_mode(qc->ap); 404 qs_enter_reg_mode(qc->ap);
411 qc->err_mask |= ac_err_mask(sDST); 405 qc->err_mask |= ac_err_mask(sDST);
412 ata_qc_complete(qc); 406 ata_qc_complete(qc);
@@ -445,7 +439,6 @@ static inline unsigned int qs_intr_mmio(struct ata_host *host)
445 ap->print_id, qc->tf.protocol, status); 439 ap->print_id, qc->tf.protocol, status);
446 440
447 /* complete taskfile transaction */ 441 /* complete taskfile transaction */
448 pp->state = qs_state_idle;
449 qc->err_mask |= ac_err_mask(status); 442 qc->err_mask |= ac_err_mask(status);
450 ata_qc_complete(qc); 443 ata_qc_complete(qc);
451 handled = 1; 444 handled = 1;
@@ -501,7 +494,6 @@ static int qs_port_start(struct ata_port *ap)
501 rc = ata_port_start(ap); 494 rc = ata_port_start(ap);
502 if (rc) 495 if (rc)
503 return rc; 496 return rc;
504 qs_enter_reg_mode(ap);
505 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 497 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
506 if (!pp) 498 if (!pp)
507 return -ENOMEM; 499 return -ENOMEM;
@@ -512,6 +504,7 @@ static int qs_port_start(struct ata_port *ap)
512 memset(pp->pkt, 0, QS_PKT_BYTES); 504 memset(pp->pkt, 0, QS_PKT_BYTES);
513 ap->private_data = pp; 505 ap->private_data = pp;
514 506
507 qs_enter_reg_mode(ap);
515 addr = (u64)pp->pkt_dma; 508 addr = (u64)pp->pkt_dma;
516 writel((u32) addr, chan + QS_CCF_CPBA); 509 writel((u32) addr, chan + QS_CCF_CPBA);
517 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4); 510 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);