[MIPS] Use real cache invalidate

R10k non coherent machines need a real dma cache invalidate to get rid of
speculative stores in cache.  For other machines this promises a slight
speedup.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index c91b5968069..06074948450 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -589,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                 if (size >= scache_size)
                         r4k_blast_scache();
                 else
-                        blast_scache_range(addr, addr + size);
+                        blast_inv_scache_range(addr, addr + size);
                 return;
         }
 
@@ -597,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                 r4k_blast_dcache();
         } else {
                 R4600_HIT_CACHEOP_WAR_IMPL;
-                blast_dcache_range(addr, addr + size);
+                blast_inv_dcache_range(addr, addr + size);
         }
 
         bc_inv(addr, size);