diff options
author | Will Deacon <will.deacon@arm.com> | 2010-09-27 13:12:12 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-10-04 14:21:37 -0400 |
commit | ccdf2e1bca8a45eaf89eb142dbed3551886413fe (patch) | |
tree | e4e73da9cfeb2851a523f4a2914d00ac21657520 /arch | |
parent | 7f58217bb6d39edac68ae0988cdb96a520ad916f (diff) |
ARM: 6412/1: kprobes-decode: add support for MOVW instruction
The MOVW instruction moves a 16-bit immediate into the bottom halfword
of the destination register.
This patch ensures that kprobes leaves the 16-bit immediate intact, rather
than assume a 12-bit immediate and mask out the upper 4 bits.
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/kernel/kprobes-decode.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c index 8bccbfa693f..2c1f0050c9c 100644 --- a/arch/arm/kernel/kprobes-decode.c +++ b/arch/arm/kernel/kprobes-decode.c | |||
@@ -1162,11 +1162,12 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) | |||
1162 | { | 1162 | { |
1163 | /* | 1163 | /* |
1164 | * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx | 1164 | * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx |
1165 | * Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx | 1165 | * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx |
1166 | * ALU op with S bit and Rd == 15 : | 1166 | * ALU op with S bit and Rd == 15 : |
1167 | * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx | 1167 | * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx |
1168 | */ | 1168 | */ |
1169 | if ((insn & 0x0f900000) == 0x03200000 || /* MSR & Undef */ | 1169 | if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */ |
1170 | (insn & 0x0ff00000) == 0x03400000 || /* Undef */ | ||
1170 | (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */ | 1171 | (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */ |
1171 | return INSN_REJECTED; | 1172 | return INSN_REJECTED; |
1172 | 1173 | ||
@@ -1177,7 +1178,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) | |||
1177 | * *S (bit 20) updates condition codes | 1178 | * *S (bit 20) updates condition codes |
1178 | * ADC/SBC/RSC reads the C flag | 1179 | * ADC/SBC/RSC reads the C flag |
1179 | */ | 1180 | */ |
1180 | insn &= 0xfff00fff; /* Rn = r0, Rd = r0 */ | 1181 | insn &= 0xffff0fff; /* Rd = r0 */ |
1181 | asi->insn[0] = insn; | 1182 | asi->insn[0] = insn; |
1182 | asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ | 1183 | asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ |
1183 | emulate_alu_imm_rwflags : emulate_alu_imm_rflags; | 1184 | emulate_alu_imm_rwflags : emulate_alu_imm_rflags; |