[MIPS] Define MIPS_CPU_IRQ_BASE in generic header

The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

24 files changed, 55 insertions, 78 deletions

diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
index 2e2061a286c..1ecab635042 100644
--- a/arch/mips/basler/excite/excite_irq.c
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -47,9 +47,9 @@ extern asmlinkage void excite_handle_int(void);
  */
 void __init arch_init_irq(void)
 {
-        mips_cpu_irq_init(0);
-        rm7k_cpu_irq_init(8);
-        rm9k_cpu_irq_init(12);
+        mips_cpu_irq_init();
+        rm7k_cpu_irq_init();
+        rm9k_cpu_irq_init();
 
 #ifdef CONFIG_KGDB
         excite_kgdb_init();
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 4c46f0e7378..fe93b846923 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -104,7 +104,7 @@ void __init arch_init_irq(void)
         GT_WRITE(GT_INTRMASK_OFS, 0);
 
         init_i8259_irqs();                              /*  0 ... 15 */
-        mips_cpu_irq_init(COBALT_CPU_IRQ);              /* 16 ... 23 */
+        mips_cpu_irq_init();            /* 16 ... 23 */
 
         /*
          * Mask all cpu interrupts
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
index a8bd2e66705..bd7cd7c5f48 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -17,6 +17,7 @@
 #include <linux/ptrace.h>
 
 #include <asm/i8259.h>
+#include <asm/irq_cpu.h>
 #include <asm/system.h>
 #include <asm/mipsregs.h>
 #include <asm/debug.h>
@@ -73,7 +74,6 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
 }
 
 extern void vrc5477_irq_init(u32 base);
-extern void mips_cpu_irq_init(u32 base);
 static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
 
 void __init arch_init_irq(void)
@@ -125,7 +125,7 @@ void __init arch_init_irq(void)
 
         /* init all controllers */
         init_i8259_irqs();
-        mips_cpu_irq_init(CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         vrc5477_irq_init(VRC5477_IRQ_BASE);
 
 
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index d34032ac492..1058e2f409b 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -234,7 +234,7 @@ static void __init dec_init_kn01(void)
         memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
                 sizeof(kn01_cpu_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
 
 }                               /* dec_init_kn01 */
 
@@ -309,7 +309,7 @@ static void __init dec_init_kn230(void)
         memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
                 sizeof(kn230_cpu_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
 
 }                               /* dec_init_kn230 */
 
@@ -403,7 +403,7 @@ static void __init dec_init_kn02(void)
         memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
                 sizeof(kn02_asic_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         init_kn02_irqs(KN02_IRQ_BASE);
 
 }                               /* dec_init_kn02 */
@@ -504,7 +504,7 @@ static void __init dec_init_kn02ba(void)
         memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
                 sizeof(kn02ba_asic_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         init_ioasic_irqs(IO_IRQ_BASE);
 
 }                               /* dec_init_kn02ba */
@@ -601,7 +601,7 @@ static void __init dec_init_kn02ca(void)
         memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
                 sizeof(kn02ca_asic_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         init_ioasic_irqs(IO_IRQ_BASE);
 
 }                               /* dec_init_kn02ca */
@@ -702,7 +702,7 @@ static void __init dec_init_kn03(void)
         memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
                 sizeof(kn03_asic_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         init_ioasic_irqs(IO_IRQ_BASE);
 
 }                               /* dec_init_kn03 */
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
index c93369cb411..3299b6dfe76 100644
--- a/arch/mips/emma2rh/markeins/irq.c
+++ b/arch/mips/emma2rh/markeins/irq.c
@@ -106,7 +106,7 @@ void __init arch_init_irq(void)
         emma2rh_irq_init(EMMA2RH_IRQ_BASE);
         emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
         emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
-        mips_cpu_irq_init(CPU_IRQ_BASE);
+        mips_cpu_irq_init();
 
         /* setup cascade interrupts */
         setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c
index d9294401ccb..2585d9dbda3 100644
--- a/arch/mips/gt64120/momenco_ocelot/irq.c
+++ b/arch/mips/gt64120/momenco_ocelot/irq.c
@@ -90,6 +90,6 @@ void __init arch_init_irq(void)
         clear_c0_status(ST0_IM);
         local_irq_disable();
 
-        mips_cpu_irq_init(0);
-        rm7k_cpu_irq_init(8);
+        mips_cpu_irq_init();
+        rm7k_cpu_irq_init();
 }
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
index eedfc24e1ea..d3d96591780 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -63,7 +63,7 @@ void gt64120_init_pic(void)
 void __init arch_init_irq(void)
 {
         /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
-        mips_cpu_irq_init(0);
+        mips_cpu_irq_init();
 
         gt64120_init_pic();
 }
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 123324ba8c1..a60cfe5f4d1 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -17,16 +17,14 @@
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 
-static int irq_base;
-
 static inline void unmask_rm7k_irq(unsigned int irq)
 {
-        set_c0_intcontrol(0x100 << (irq - irq_base));
+        set_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE));
 }
 
 static inline void mask_rm7k_irq(unsigned int irq)
 {
-        clear_c0_intcontrol(0x100 << (irq - irq_base));
+        clear_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE));
 }
 
 static struct irq_chip rm7k_irq_controller = {
@@ -37,8 +35,9 @@ static struct irq_chip rm7k_irq_controller = {
         .unmask = unmask_rm7k_irq,
 };
 
-void __init rm7k_cpu_irq_init(int base)
+void __init rm7k_cpu_irq_init(void)
 {
+        int base = RM7K_CPU_IRQ_BASE;
         int i;
 
         clear_c0_intcontrol(0x00000f00);                /* Mask all */
@@ -46,6 +45,4 @@ void __init rm7k_cpu_irq_init(int base)
         for (i = base; i < base + 4; i++)
                 set_irq_chip_and_handler(i, &rm7k_irq_controller,
                                          handle_level_irq);
-
-        irq_base = base;
 }
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 2e68e4b639f..27886db89a6 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -18,16 +18,14 @@
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 
-static int irq_base;
-
 static inline void unmask_rm9k_irq(unsigned int irq)
 {
-        set_c0_intcontrol(0x1000 << (irq - irq_base));
+        set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
 }
 
 static inline void mask_rm9k_irq(unsigned int irq)
 {
-        clear_c0_intcontrol(0x1000 << (irq - irq_base));
+        clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
 }
 
 static inline void rm9k_cpu_irq_enable(unsigned int irq)
@@ -93,8 +91,9 @@ unsigned int rm9000_perfcount_irq;
 
 EXPORT_SYMBOL(rm9000_perfcount_irq);
 
-void __init rm9k_cpu_irq_init(int base)
+void __init rm9k_cpu_irq_init(void)
 {
+        int base = RM9K_CPU_IRQ_BASE;
         int i;
 
         clear_c0_intcontrol(0x0000f000);                /* Mask all */
@@ -106,6 +105,4 @@ void __init rm9k_cpu_irq_init(int base)
         rm9000_perfcount_irq = base + 1;
         set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
                                  handle_level_irq);
-
-        irq_base = base;
 }
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index fcc86b96ccf..6e73ddaeae7 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -25,7 +25,7 @@
  * Don't even think about using this on SMP.  You have been warned.
  *
  * This file exports one global function:
- *      void mips_cpu_irq_init(int irq_base);
+ *      void mips_cpu_irq_init(void);
  */
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -36,17 +36,15 @@
 #include <asm/mipsmtregs.h>
 #include <asm/system.h>
 
-static int mips_cpu_irq_base;
-
 static inline void unmask_mips_irq(unsigned int irq)
 {
-        set_c0_status(0x100 << (irq - mips_cpu_irq_base));
+        set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
         irq_enable_hazard();
 }
 
 static inline void mask_mips_irq(unsigned int irq)
 {
-        clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
+        clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
         irq_disable_hazard();
 }
 
@@ -70,7 +68,7 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
 {
         unsigned int vpflags = dvpe();
 
-        clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
+        clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
         evpe(vpflags);
         unmask_mips_mt_irq(irq);
 
@@ -84,7 +82,7 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
 static void mips_mt_cpu_irq_ack(unsigned int irq)
 {
         unsigned int vpflags = dvpe();
-        clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
+        clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
         evpe(vpflags);
         mask_mips_mt_irq(irq);
 }
@@ -99,8 +97,9 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
         .eoi            = unmask_mips_mt_irq,
 };
 
-void __init mips_cpu_irq_init(int irq_base)
+void __init mips_cpu_irq_init(void)
 {
+        int irq_base = MIPS_CPU_IRQ_BASE;
         int i;
 
         /* Mask interrupts. */
@@ -118,6 +117,4 @@ void __init mips_cpu_irq_init(int irq_base)
         for (i = irq_base + 2; i < irq_base + 8; i++)
                 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
                                          handle_level_irq);
-
-        mips_cpu_irq_base = irq_base;
 }
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 5a99e3e0c96..8610f4a925e 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -63,7 +63,7 @@ extern void *vpe_get_shared(int index);
 
 static void rtlx_dispatch(void)
 {
-        do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ);
+        do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);
 }
 
 
@@ -491,7 +491,7 @@ static struct irqaction rtlx_irq = {
         .name           = "RTLX",
 };
 
-static int rtlx_irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ;
+static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;
 
 static char register_chrdev_failed[] __initdata =
         KERN_ERR "rtlx_module_init: unable to register device\n";
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 1ee689c0e0c..64b62bdfb4f 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -35,7 +35,6 @@
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/mips_mt.h>
-#include <asm/mips-boards/maltaint.h>  /* This is f*cking wrong */
 
 #define MIPS_CPU_IPI_RESCHED_IRQ 0
 #define MIPS_CPU_IPI_CALL_IRQ 1
@@ -108,12 +107,12 @@ void __init sanitize_tlb_entries(void)
 
 static void ipi_resched_dispatch(void)
 {
-        do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
+        do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
 }
 
 static void ipi_call_dispatch(void)
 {
-        do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ);
+        do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
 }
 
 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
@@ -270,8 +269,8 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
                 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
         }
 
-        cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
-        cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
+        cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
+        cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
 
         setup_irq(cpu_ipi_resched_irq, &irq_resched);
         setup_irq(cpu_ipi_call_irq, &irq_call);
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 6a857bf030b..6a276314377 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -26,16 +26,6 @@
  * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
  */
 
-/*
- * MIPSCPU_INT_BASE is identically defined in both
- * asm-mips/mips-boards/maltaint.h and asm-mips/mips-boards/simint.h,
- * but as yet there's no properly organized include structure that
- * will ensure that the right *int.h file will be included for a
- * given platform build.
- */
-
-#define MIPSCPU_INT_BASE        16
-
 #define MIPS_CPU_IPI_IRQ        1
 
 #define LOCK_MT_PRA() \
@@ -921,7 +911,7 @@ void smtc_timer_broadcast(int vpe)
  * interrupts.
  */
 
-static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ;
+static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
 
 static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
 {
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 43dba6ce660..85482a631e8 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -238,7 +238,7 @@ void __init arch_init_irq(void)
         init_atlas_irqs(ATLAS_INT_BASE);
 
         if (!cpu_has_veic)
-                mips_cpu_irq_init(MIPSCPU_INT_BASE);
+                mips_cpu_irq_init();
 
         switch(mips_revision_corid) {
         case MIPS_REVISION_CORID_CORE_MSC:
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 90ad5bf3e2f..d9ddb170e59 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -310,7 +310,7 @@ void __init arch_init_irq(void)
         init_i8259_irqs();
 
         if (!cpu_has_veic)
-                mips_cpu_irq_init (MIPSCPU_INT_BASE);
+                mips_cpu_irq_init();
 
         switch(mips_revision_corid) {
         case MIPS_REVISION_CORID_CORE_MSC:
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 874ccb0066b..c4b9de3a7f2 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -113,5 +113,5 @@ asmlinkage void plat_irq_dispatch(void)
 
 void __init arch_init_irq(void)
 {
-        mips_cpu_irq_init(MIPSCPU_INT_BASE);
+        mips_cpu_irq_init();
 }
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c
index 2ce449dce6f..15ac0655c1f 100644
--- a/arch/mips/mips-boards/sim/sim_int.c
+++ b/arch/mips/mips-boards/sim/sim_int.c
@@ -21,9 +21,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include <asm/mips-boards/simint.h>
-
-
-extern void mips_cpu_irq_init(int);
+#include <asm/irq_cpu.h>
 
 static inline int clz(unsigned long x)
 {
@@ -86,5 +84,5 @@ asmlinkage void plat_irq_dispatch(void)
 
 void __init arch_init_irq(void)
 {
-        mips_cpu_irq_init(MIPSCPU_INT_BASE);
+        mips_cpu_irq_init();
 }
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c
index 2efb25aa1ae..f2b432585df 100644
--- a/arch/mips/momentum/jaguar_atx/irq.c
+++ b/arch/mips/momentum/jaguar_atx/irq.c
@@ -82,8 +82,8 @@ void __init arch_init_irq(void)
          */
         clear_c0_status(ST0_IM);
 
-        mips_cpu_irq_init(0);
-        rm7k_cpu_irq_init(8);
+        mips_cpu_irq_init();
+        rm7k_cpu_irq_init();
 
         /* set up the cascading interrupts */
         setup_irq(8, &cascade_mv64340);
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c
index cea0e5deb80..3862d1d1add 100644
--- a/arch/mips/momentum/ocelot_3/irq.c
+++ b/arch/mips/momentum/ocelot_3/irq.c
@@ -65,7 +65,7 @@ void __init arch_init_irq(void)
          */
         clear_c0_status(ST0_IM | ST0_BEV);
 
-        rm7k_cpu_irq_init(8);
+        rm7k_cpu_irq_init();
 
         /* set up the cascading interrupts */
         setup_irq(8, &cascade_mv64340);         /* unmask intControl IM8, IRQ 9 */
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index ea65223a6d2..40472f7944d 100644
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -94,7 +94,7 @@ void __init arch_init_irq(void)
          */
         clear_c0_status(ST0_IM);
 
-        mips_cpu_irq_init(0);
+        mips_cpu_irq_init();
 
         /* set up the cascading interrupts */
         setup_irq(3, &cascade_fpga);
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c
index da46524e87c..273541fe708 100644
--- a/arch/mips/momentum/ocelot_g/irq.c
+++ b/arch/mips/momentum/ocelot_g/irq.c
@@ -94,8 +94,8 @@ void __init arch_init_irq(void)
         clear_c0_status(ST0_IM);
         local_irq_disable();
 
-        mips_cpu_irq_init(0);
-        rm7k_cpu_irq_init(8);
+        mips_cpu_irq_init();
+        rm7k_cpu_irq_init();
 
         gt64240_irq_init();
 }
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index adb048527e7..428d1f45a28 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -148,9 +148,9 @@ void __init arch_init_irq(void)
 {
         clear_c0_status(ST0_IM);
 
-        mips_cpu_irq_init(0);
-        rm7k_cpu_irq_init(8);
-        rm9k_cpu_irq_init(12);
+        mips_cpu_irq_init();
+        rm7k_cpu_irq_init();
+        rm9k_cpu_irq_init();
 
 #ifdef CONFIG_KGDB
         /* At this point, initialize the second serial port */
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index c44f8be0644..f3d2ae374c7 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -19,6 +19,7 @@
 
 #include <asm/mipsregs.h>
 #include <asm/addrspace.h>
+#include <asm/irq_cpu.h>
 
 #include <asm/sgi/ioc.h>
 #include <asm/sgi/hpc3.h>
@@ -253,8 +254,6 @@ asmlinkage void plat_irq_dispatch(void)
                 indy_8254timer_irq();
 }
 
-extern void mips_cpu_irq_init(unsigned int irq_base);
-
 void __init arch_init_irq(void)
 {
         int i;
@@ -316,7 +315,7 @@ void __init arch_init_irq(void)
         sgint->cmeimask1 = 0;
 
         /* init CPU irqs */
-        mips_cpu_irq_init(SGINT_CPU);
+        mips_cpu_irq_init();
 
         for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
                 struct irq_chip *handler;
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 16decf4ac2f..697fcc26014 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -117,5 +117,5 @@ asmlinkage void plat_irq_dispatch(void)
 
 void __init arch_init_irq(void)
 {
-        mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
 }