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authorPaul Mundt <lethal@linux-sh.org>2009-06-15 17:26:08 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-06-15 17:26:08 -0400
commit66765fe1b62e4c0eee3b7e3aa1eb34e5428f52ec (patch)
tree8952f6a5502cf1fd3f7c3fa0a063a2cb66fe9b83 /arch
parent8c6b44d00aca45edf69b35220ba4dce962c482f8 (diff)
sh: pci: SH7786 PCI ops.
This adds in preliminary support for the SH7786 PCIe module PCI ops, and the corresponding module definitions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/drivers/pci/Makefile1
-rw-r--r--arch/sh/drivers/pci/ops-sh7786.c134
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.h589
3 files changed, 724 insertions, 0 deletions
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index d2ffc477549..d6303d0e494 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += ops-sh7786.o
11obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o 12obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
12 13
13obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ 14obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c
new file mode 100644
index 00000000000..48f594b9582
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-sh7786.c
@@ -0,0 +1,134 @@
1/*
2 * Generic SH7786 PCI-Express operations.
3 *
4 * Copyright (C) 2009 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License v2. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/io.h>
14#include <linux/spinlock.h>
15#include "pcie-sh7786.h"
16
17enum {
18 PCI_ACCESS_READ,
19 PCI_ACCESS_WRITE,
20};
21
22static DEFINE_SPINLOCK(sh7786_pcie_lock);
23
24static int sh7786_pcie_config_access(unsigned char access_type,
25 struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
26{
27 struct pci_channel *chan = bus->sysdata;
28 int dev, func;
29
30 dev = PCI_SLOT(devfn);
31 func = PCI_FUNC(devfn);
32
33 if (bus->number > 255 || dev > 31 || func > 7)
34 return PCIBIOS_FUNC_NOT_SUPPORTED;
35 if (devfn)
36 return PCIBIOS_DEVICE_NOT_FOUND;
37
38 /* Set the PIO address */
39 pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
40 (func << 16) | (where & ~3), SH4A_PCIEPAR);
41
42 /* Enable the configuration access */
43 pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
44
45 if (access_type == PCI_ACCESS_READ)
46 *data = pci_read_reg(chan, SH4A_PCIEPDR);
47 else
48 pci_write_reg(chan, *data, SH4A_PCIEPDR);
49
50 /* Check for master and target aborts */
51 if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
52 return PCIBIOS_DEVICE_NOT_FOUND;
53
54 return PCIBIOS_SUCCESSFUL;
55}
56
57static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
58 int where, int size, u32 *val)
59{
60 unsigned long flags;
61 int ret;
62 u32 data;
63
64 if ((size == 2) && (where & 1))
65 return PCIBIOS_BAD_REGISTER_NUMBER;
66 else if ((size == 4) && (where & 3))
67 return PCIBIOS_BAD_REGISTER_NUMBER;
68
69 spin_lock_irqsave(&sh7786_pcie_lock, flags);
70 ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
71 devfn, where, &data);
72 if (ret != PCIBIOS_SUCCESSFUL)
73 goto out;
74
75 if (size == 1)
76 *val = (data >> ((where & 3) << 3)) & 0xff;
77 else if (size == 2)
78 *val = (data >> ((where & 2) << 3)) & 0xffff;
79 else
80 *val = data;
81
82 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
83 "where=0x%04x size=%d val=0x%08lx\n", bus->number,
84 devfn, where, size, (unsigned long)*val);
85
86out:
87 spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
88 return ret;
89}
90
91static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
92 int where, int size, u32 val)
93{
94 unsigned long flags;
95 int shift, ret;
96 u32 data;
97
98 if ((size == 2) && (where & 1))
99 return PCIBIOS_BAD_REGISTER_NUMBER;
100 else if ((size == 4) && (where & 3))
101 return PCIBIOS_BAD_REGISTER_NUMBER;
102
103 spin_lock_irqsave(&sh7786_pcie_lock, flags);
104 ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
105 devfn, where, &data);
106 if (ret != PCIBIOS_SUCCESSFUL)
107 goto out;
108
109 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
110 "where=0x%04x size=%d val=%08lx\n", bus->number,
111 devfn, where, size, (unsigned long)val);
112
113 if (size == 1) {
114 shift = (where & 3) << 3;
115 data &= ~(0xff << shift);
116 data |= ((val & 0xff) << shift);
117 } else if (size == 2) {
118 shift = (where & 2) << 3;
119 data &= ~(0xffff << shift);
120 data |= ((val & 0xffff) << shift);
121 } else
122 data = val;
123
124 ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
125 devfn, where, &data);
126out:
127 spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
128 return ret;
129}
130
131struct pci_ops sh7786_pci_ops = {
132 .read = sh7786_pcie_read,
133 .write = sh7786_pcie_write,
134};
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
new file mode 100644
index 00000000000..c655290a775
--- /dev/null
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -0,0 +1,589 @@
1/*
2 * SH7786 PCI-Express controller definitions.
3 *
4 * Copyright (C) 2008, 2009 Renesas Technology Corp.
5 * All rights reserved.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __PCI_SH7786_H
12#define __PCI_SH7786_H
13
14/* PCIe bus-0(x4) on SH7786 */ // Rev1.171
15#define SH4A_PCIE_SPW_BASE 0xFE000000 /* spw config address for controller 0 */
16#define SH4A_PCIE_SPW_BASE1 0xFE200000 /* spw config address for controller 1 (Rev1.14)*/
17#define SH4A_PCIE_SPW_BASE2 0xFCC00000 /* spw config address for controller 2 (Rev1.171)*/
18#define SH4A_PCIE_SPW_BASE_LEN 0x00080000
19
20#define SH4A_PCI_CNFG_BASE 0xFE040000 /* pci config address for controller 0 */
21#define SH4A_PCI_CNFG_BASE1 0xFE240000 /* pci config address for controller 1 (Rev1.14)*/
22#define SH4A_PCI_CNFG_BASE2 0xFCC40000 /* pci config address for controller 2 (Rev1.171)*/
23#define SH4A_PCI_CNFG_BASE_LEN 0x00040000
24
25#define SH4A_PCIPIO_ADDR_OFFSET 0x000001c0 /* offset to pci config_address */
26#define SH4A_PCIPIO_DATA_OFFSET 0x00000220 /* offset to pci config_data */
27
28/*
29 * for PEX8111(Max Payload Size=128B,PCIIO_SIZE=64K),
30 * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
31 */
32
33/* PCI0-0: PCI I/O space */
34#define SH4A_PCIIO_BASE 0xFD000000 /* PCI I/O for controller 0 */
35#define SH4A_PCIIO_BASE1 0xFD800000 /* PCI I/O for controller 1 (Rev1.14)*/
36#define SH4A_PCIIO_BASE2 0xFC800000 /* PCI I/O for controller 2 (Rev1.171)*/
37
38#define SH4A_PCIIO_SIZE64 0x00010000 /* PLX allows only 64K */
39#define SH4A_PCIIO_SIZE 0x00800000 /* 8M */
40#define SH4A_PCIIO_SIZE2 0x00400000 /* 4M (Rev1.171)*/
41
42/* PCI0-1: PCI memory space 29-bit address */
43#define SH4A_PCIMEM_BASE 0x10000000
44#define SH4A_PCIMEM_SIZE 0x04000000 /* 64M */
45
46/* PCI0-2: PCI memory space 32-bit address */
47#define SH4A_PCIMEM_BASEA 0xC0000000 /* for controller 0 */
48#define SH4A_PCIMEM_BASEA1 0xA0000000 /* for controller 1 (Rev1.14)*/
49#define SH4A_PCIMEM_BASEA2 0x80000000 /* for controller 2 (Rev1.171)*/
50#define SH4A_PCIMEM_SIZEA 0x20000000 /* 512M */
51
52/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
53#define SH4A_PCIBMSTR_TRANSLATION 0x20000000
54
55#define SH4A_PCI_DEVICE_ID 0x0002
56#define SH4A_PCI_VENDOR_ID 0x1912
57
58// PCI compatible 000-03f
59#define PCI_CMD 0x004
60#define PCI_RID 0x008
61#define PCI_IBAR 0x010
62#define PCI_MBAR0 0x014
63#define PCI_MBAR1 0x018
64
65/* PCI power management/MSI/capablity 040-0ff */
66/* PCIE extended 100-fff */
67
68/* SH7786 device identification */ // Rev1.171
69#define SH4A_PVR (0xFF000030)
70#define SH4A_PVR_SHX3 (0x10400000)
71#define SH4A_PRR (0xFF000044)
72#define SH4A_PRR_SH7786 (0x00000400) // Rev1.171
73
74/* SPVCR0 */
75#define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */
76#define BITS_TOP_MB (24)
77#define MASK_TOP_MB (0xff<<BITS_TOP_MB)
78#define BITS_BOT_MB (16)
79#define MASK_BOT_MB (0xff<<BITS_BOT_MB)
80#define BITS_VC_ID (0)
81#define MASK_VC_ID (0xffff<<BITS_VC_ID)
82
83/* SPVCR1 */
84#define SH4A_PCIEVCR1 (0x000004) /* R - 0x0000 0000 32*/
85#define BITS_BADOPC (5) /* 5 BADOPC 0 R/W */
86#define MASK_BADOPC (1<<BITS_BADOPC)
87#define BITS_BADDEST (4) /*4 BADDEST 0 R/W */
88#define MASK_BADDEST (1<<BITS_BADDEST)
89#define BITS_UNSOLRESP (3) /* 3 UNSOLRESP 0 R/W */
90#define MASK_UNSOLRESP (1<<BITS_UNSOLRESP)
91#define BITS_ERRSNT (1) /* 1 ERRSNT 0 */
92#define MASK_ERRSNT (1<<BITS_ERRSNT)
93#define BITS_ERRRCV (0) /* 0 ERRRCV 0 */
94#define MASK_ERRRCV (1<<BITS_ERRRCV)
95
96/* PCIEECR */
97#define SH4A_PCIEECR (0x000008) /* R/W - 0x0000 0000 32 */
98#define BITS_ENBL (0) /* 0 ENBL 0 R/W */
99#define MASK_ENBL (1<<BITS_ENBL)
100
101/* PCIEPAR */
102#define SH4A_PCIEPAR (0x000010) /* R/W - 0x0000 0000 32 */
103#define BITS_BN (24)
104#define MASK_BN (0xff<<BITS_BN)
105#define BITS_DN (19)
106#define MASK_DN (0x1f<<BITS_DN)
107#define BITS_FN (16)
108#define MASK_FN (0x7<<BITS_FN)
109#define BITS_EREGNO (8)
110#define MASK_EREGNO (0xff<<BITS_EREGNO)
111#define BITS_REGNO (2)
112#define MASK_REGNO (0x3f<<BITS_REGNO)
113
114/* PCIEPCTLR */
115#define SH4A_PCIEPCTLR (0x000018) /* R/W - 0x0000 0000 32 */
116#define BITS_CCIE (31) /* 31 CCIE */
117#define MASK_CCIE (1<<BITS_CCIE)
118#define BITS_TYPE (8)
119#define MASK_TYPE (1<<BITS_TYPE)
120#define BITS_C_VC (0)
121#define MASK_C_VC (1<<BITS_C_VC)
122
123/* PCIEPDR */
124#define SH4A_PCIEPDR (0x000020) /* R/W - 0x0000 0000 32 */
125#define BITS_PDR (0)
126#define MASK_PDR (0xffffffff<<BITS_PDR)
127
128/* PCIEMSGALR */
129#define SH4A_PCIEMSGALR (0x000030) /* R/W - 0x0000 0000 32 */
130#define BITS_MSGADRL (0)
131#define MASK_MSGADRL (0xffffffff<<BITS_MSGADRL)
132
133/* PCIEMSGAHR */
134#define SH4A_PCIEMSGAHR (0x000034) /* R/W - 0x0000 0000 32 */
135#define BITS_MSGADRH (0)
136#define MASK_MSGADRH (0xffffffff<<BITS_MSGADRH)
137
138/* PCIEMSGCTLR */
139#define SH4A_PCIEMSGCTLR (0x000038) /* R/W - 0x0000 0000 32 */
140#define BITS_MSGIE (31)
141#define MASK_MSGIE (1<<BITS_MSGIE)
142#define BITS_MROUTE (16)
143#define MASK_MROUTE (0x7<<BITS_MROUTE)
144#define BITS_MCODE (8)
145#define MASK_MCODE (0xff<<BITS_MCODE)
146#define BITS_M_VC (0)
147#define MASK_M_VC (1<<BITS_M_VC)
148
149/* PCIEMSG */
150#define SH4A_PCIEMSG (0x000040) /* W - - 32 */
151#define BITS_MDATA (0)
152#define MASK_MDATA (0xffffffff<<BITS_MDATA)
153
154/* PCIEPHYCTLR */
155#define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
156#define BITS_CKE (0)
157#define MASK_CKE (1<<BITS_CKE)
158
159/* PCIERMSGIER */
160#define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */
161
162/* PCIEPHYADRR */
163#define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */
164#define BITS_ACK (24) // Rev1.171
165#define MASK_ACK (1<<BITS_ACK) // Rev1.171
166#define BITS_CMD (16) // Rev1.171
167#define MASK_CMD (0x03<<BITS_CMD) // Rev1.171
168#define BITS_LANE (8)
169#define MASK_LANE (0x0f<<BITS_LANE)
170#define BITS_ADR (0)
171#define MASK_ADR (0xff<<BITS_ADR)
172
173/* PCIEPHYDINR */ // Rev1.171 start.
174#define SH4A_PCIEPHYDINR (0x010008) /* R/W - 0x0000 0000 32 */
175
176/* PCIEPHYDOUTR */
177#define SH4A_PCIEPHYDOUTR (0x01000C) /* R/W - 0x0000 0000 32 */
178
179/* PCIEPHYSR */
180#define SH4A_PCIEPHYSR (0x010010) /* R/W - 0x0000 0000 32 */ // Rev1.171 end.
181
182/* PCIEPHYDATAR */
183#define SH4A_PCIEPHYDATAR (0x00008) /* R/W - 0xxxxx xxxx 32 */
184#define BITS_DATA (0)
185#define MASK_DATA (0xffffffff<<BITS_DATA)
186
187/* PCIETCTLR */
188#define SH4A_PCIETCTLR (0x020000) /* R/W R/W 0x0000 0000 32 */
189#define BITS_CFINT (0)
190#define MASK_CFINT (1<<BITS_CFINT)
191
192/* PCIETSTR */
193#define SH4A_PCIETSTR (0x020004) /* R/W R/W 0x0000 0000 32 */
194
195/* PCIEINTR */
196#define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */
197#define BITS_INT_RX_ERP (31)
198#define MASK_INT_RX_ERP (1<<BITS_INT_RX_ERP)
199#define BITS_INT_RX_VCX_Posted (30)
200#define MASK_INT_RX_VCX_Posted (1<<BITS_INT_RX_VCX_Posted)
201#define BITS_INT_RX_VCX_NonPosted (29)
202#define MASK_INT_RX_VCX_NonPosted (1<<BITS_INT_RX_VCX_NonPosted)
203#define BITS_INT_RX_VCX_CPL (28)
204#define MASK_INT_RX_VCX_CPL (1<<BITS_INT_RX_VCX_CPL)
205#define BITS_INT_TX_VCX_Posted (26)
206#define MASK_INT_TX_VCX_Posted (1<<BITS_INT_TX_VCX_Posted)
207#define BITS_INT_TX_VCX_NonPosted (25)
208#define MASK_INT_TX_VCX_NonPosted (1<<BITS_INT_TX_VCX_NonPosted)
209#define BITS_INT_TX_VCX_CPL (24)
210#define MASK_INT_TX_VCX_CPL (1<<BITS_INT_TX_VCX_CPL)
211#define BITS_INT_RX_VC0_Posted (22)
212#define MASK_INT_RX_VC0_Posted (1<<BITS_INT_RX_VC0_Posted)
213#define BITS_INT_RX_VC0_NonPosted (21)
214#define MASK_INT_RX_VC0_NonPosted (1<<BITS_INT_RX_VC0_NonPosted)
215#define BITS_INT_RX_VC0_CPL (20)
216#define MASK_INT_RX_VC0_CPL (1<<BITS_INT_RX_VC0_CPL)
217#define BITS_INT_TX_VC0_Posted (18)
218#define MASK_INT_TX_VC0_Posted (1<<BITS_INT_TX_VC0_Posted)
219#define BITS_INT_TX_VC0_NonPosted (17)
220#define MASK_INT_TX_VC0_NonPosted (1<<BITS_INT_TX_VC0_NonPosted)
221#define BITS_INT_TX_VC0_CPL (16)
222#define MASK_INT_TX_VC0_CPL (1<<BITS_INT_TX_VC0_CPL)
223#define BITS_INT_RX_CTRL (15)
224#define MASK_INT_RX_CTRL (1<<BITS_INT_RX_CTRL)
225#define BITS_INT_TX_CTRL (14)
226#define MASK_INT_TX_CTRL (1<<BITS_INT_TX_CTRL)
227#define BITS_INTTL (11)
228#define MASK_INTTL (1<<BITS_INTTL)
229#define BITS_INTDL (10)
230#define MASK_INTDL (1<<BITS_INTDL)
231#define BITS_INTMAC (9)
232#define MASK_INTMAC (1<<BITS_INTMAC)
233#define BITS_INTPM (8)
234#define MASK_INTPM (1<<BITS_INTPM)
235
236/* PCIEINTER */
237#define SH4A_PCIEINTER (0x02000C) /* R/W R/W 0x0000 0000 32 */
238#define BITS_INT_RX_ERP (31)
239#define MASK_INT_RX_ERP (1<<BITS_INT_RX_ERP)
240#define BITS_INT_RX_VCX_Posted (30)
241#define MASK_INT_RX_VCX_Posted (1<<BITS_INT_RX_VCX_Posted)
242#define BITS_INT_RX_VCX_NonPosted (29)
243#define MASK_INT_RX_VCX_NonPosted (1<<BITS_INT_RX_VCX_NonPosted)
244#define BITS_INT_RX_VCX_CPL (28)
245#define MASK_INT_RX_VCX_CPL (1<<BITS_INT_RX_VCX_CPL)
246#define BITS_INT_TX_VCX_Posted (26)
247#define MASK_INT_TX_VCX_Posted (1<<BITS_INT_TX_VCX_Posted)
248#define BITS_INT_TX_VCX_NonPosted (25)
249#define MASK_INT_TX_VCX_NonPosted (1<<BITS_INT_TX_VCX_NonPosted)
250#define BITS_INT_TX_VCX_CPL (24)
251#define MASK_INT_TX_VCX_CPL (1<<BITS_INT_TX_VCX_CPL)
252#define BITS_INT_RX_VC0_Posted (22)
253#define MASK_INT_RX_VC0_Posted (1<<BITS_INT_RX_VC0_Posted)
254#define BITS_INT_RX_VC0_NonPosted (21)
255#define MASK_INT_RX_VC0_NonPosted (1<<BITS_INT_RX_VC0_NonPosted)
256#define BITS_INT_RX_VC0_CPL (20)
257#define MASK_INT_RX_VC0_CPL (1<<BITS_INT_RX_VC0_CPL)
258#define BITS_INT_TX_VC0_Posted (18)
259#define MASK_INT_TX_VC0_Posted (1<<BITS_INT_TX_VC0_Posted)
260#define BITS_INT_TX_VC0_NonPosted (17)
261#define MASK_INT_TX_VC0_NonPosted (1<<BITS_INT_TX_VC0_NonPosted)
262#define BITS_INT_TX_VC0_CPL (16)
263#define MASK_INT_TX_VC0_CPL (1<<BITS_INT_TX_VC0_CPL)
264#define BITS_INT_RX_CTRL (15)
265#define MASK_INT_RX_CTRL (1<<BITS_INT_RX_CTRL)
266#define BITS_INT_TX_CTRL (14)
267#define MASK_INT_TX_CTRL (1<<BITS_INT_TX_CTRL)
268#define BITS_INTTL (11)
269#define MASK_INTTL (1<<BITS_INTTL)
270#define BITS_INTDL (10)
271#define MASK_INTDL (1<<BITS_INTDL)
272#define BITS_INTMAC (9)
273#define MASK_INTMAC (1<<BITS_INTMAC)
274#define BITS_INTPM (8)
275#define MASK_INTPM (1<<BITS_INTPM)
276
277/* PCIEAIR */
278#define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */
279
280/* PCIECIR */
281#define SH4A_PCIECIR (SH4A_PCIE_BASE) /* R/W R/W 0xxxxx xxxx 32 */
282
283/* PCIEERRFR */ // Rev1.18
284#define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18
285 // Rev1.18
286/* PCIELAR0 */
287#define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */
288#define BITS_LARn (20)
289#define MASK_LARn (0xfff<<BITS_LARn)
290
291#define SH4A_PCIE_020204 (0x020204) /* R/W R/W 0x0000 0000 32 */
292
293/* PCIELAMR0 */
294#define SH4A_PCIELAMR0 (0x020208) /* R/W R/W 0x0000 0000 32 */
295#define BITS_LAMRn (20)
296#define MASK_LAMRn (0x1ff<<BITS_LAMRn)
297#define BITS_LAREn (0)
298#define MASK_LAREn (0x1<<BITS_LAREn)
299
300/* PCIECSCR0 */
301#define SH4A_PCIECSCR0 (0x020210) /* R/W R/W 0x0000 0000 32 */
302#define BITS_RANGE (2)
303#define MASK_RANGE (0x7<<BITS_RANGE)
304#define BITS_SNPMD (0)
305#define MASK_SNPMD (0x3<<BITS_SNPMD)
306
307/* PCIECSAR0 */
308#define SH4A_PCIECSAR0 (0x020214) /* R/W R/W 0x0000 0000 32 */
309#define BITS_CSADR (0)
310#define MASK_CSADR (0xffffffff<<BITS_CSADR)
311
312/* PCIESTCTLR0 */
313#define SH4A_PCIESTCTLR0 (0x020218) /* R/W R/W 0x0000 0000 32 */
314#define BITS_SHPRI (8)
315#define MASK_SHPRI (0x0f<<BITS_SHPRI)
316
317#define SH4A_PCIE_020224 (0x020224) /* R/W R/W 0x0000 0000 32 */
318
319#define SH4A_PCIELAR1 (0x020220) /* R/W R/W 0x0000 0000 32 */
320#define SH4A_PCIELAMR1 (0x020228) /* R/W R/W 0x0000 0000 32 */
321#define SH4A_PCIECSCR1 (0x020230) /* R/W R/W 0x0000 0000 32 */
322#define SH4A_PCIECSAR1 (0x020234) /* R/W R/W 0x0000 0000 32 */
323#define SH4A_PCIESTCTLR1 (0x020238) /* R/W R/W 0x0000 0000 32 */
324
325#define SH4A_PCIELAR2 (0x020240) /* R/W R/W 0x0000 0000 32 */
326#define SH4A_PCIE_020244 (0x020244) /* R/W R/W 0x0000 0000 32 */
327#define SH4A_PCIELAMR2 (0x020248) /* R/W R/W 0x0000 0000 32 */
328#define SH4A_PCIECSCR2 (0x020250) /* R/W R/W 0x0000 0000 32 */
329#define SH4A_PCIECSAR2 (0x020254) /* R/W R/W 0x0000 0000 32 */
330#define SH4A_PCIESTCTLR2 (0x020258) /* R/W R/W 0x0000 0000 32 */
331
332#define SH4A_PCIELAR3 (0x020260) /* R/W R/W 0x0000 0000 32 */
333#define SH4A_PCIE_020264 (0x020264) /* R/W R/W 0x0000 0000 32 */
334#define SH4A_PCIELAMR3 (0x020268) /* R/W R/W 0x0000 0000 32 */
335#define SH4A_PCIECSCR3 (0x020270) /* R/W R/W 0x0000 0000 32 */
336#define SH4A_PCIECSAR3 (0x020274) /* R/W R/W 0x0000 0000 32 */
337#define SH4A_PCIESTCTLR3 (0x020278) /* R/W R/W 0x0000 0000 32 */
338
339#define SH4A_PCIELAR4 (0x020280) /* R/W R/W 0x0000 0000 32 */
340#define SH4A_PCIE_020284 (0x020284) /* R/W R/W 0x0000 0000 32 */
341#define SH4A_PCIELAMR4 (0x020288) /* R/W R/W 0x0000 0000 32 */
342#define SH4A_PCIECSCR4 (0x020290) /* R/W R/W 0x0000 0000 32 */
343#define SH4A_PCIECSAR4 (0x020294) /* R/W R/W 0x0000 0000 32 */
344#define SH4A_PCIESTCTLR4 (0x020298) /* R/W R/W 0x0000 0000 32 */
345
346#define SH4A_PCIELAR5 (0x0202A0) /* R/W R/W 0x0000 0000 32 */
347#define SH4A_PCIE_0202A4 (0x0202A4) /* R/W R/W 0x0000 0000 32 */
348#define SH4A_PCIELAMR5 (0x0202A8) /* R/W R/W 0x0000 0000 32 */
349#define SH4A_PCIECSCR5 (0x0202B0) /* R/W R/W 0x0000 0000 32 */
350#define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */
351#define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */
352
353/* PCIEPARL0 */
354#define SH4A_PCIEPARL0 (0x020400) /* R/W R/W 0x0000 0000 32 */
355#define BITS_PAL (18)
356#define MASK_PAL (0x3fff<<BITS_PAL)
357
358/* PCIEPARH0 */
359#define SH4A_PCIEPARH0 (0x020404) /* R/W R/W 0x0000 0000 32 */
360#define BITS_PAH (0)
361#define MASK_PAH (0xffffffff<<BITS_PAH)
362
363/* PCIEPAMR0 */
364#define SH4A_PCIEPAMR0 (0x020408) /* R/W R/W 0x0000 0000 32 */
365#define BITS_PAM (18)
366#define MASK_PAM (0x3fff<<BITS_PAM)
367
368/* PCIEPTCTLR0 */
369#define SH4A_PCIEPTCTLR0 (0x02040C) /* R/W R/W 0x0000 0000 32 */
370#define BITS_PARE (31)
371#define MASK_PARE (0x1<<BITS_PARE)
372#define BITS_TC (20)
373#define MASK_TC (0x7<<BITS_TC)
374#define BITS_T_VC (16)
375#define MASK_T_VC (0x1<<BITS_T_VC)
376#define BITS_LOCK (12)
377#define MASK_LOCK (0x1<<BITS_LOCK)
378#define BITS_SPC (8)
379#define MASK_SPC (0x1<<BITS_SPC)
380
381#define SH4A_PCIEPARL1 (0x020420) /* R/W R/W 0x0000 0000 32 */
382#define SH4A_PCIEPARH1 (0x020424) /* R/W R/W 0x0000 0000 32 */
383#define SH4A_PCIEPAMR1 (0x020428) /* R/W R/W 0x0000 0000 32 */
384#define SH4A_PCIEPTCTLR1 (0x02042C) /* R/W R/W 0x0000 0000 32 */
385#define SH4A_PCIEPARL2 (0x020440) /* R/W R/W 0x0000 0000 32 */
386#define SH4A_PCIEPARH2 (0x020444) /* R/W R/W 0x0000 0000 32 */
387#define SH4A_PCIEPAMR2 (0x020448) /* R/W R/W 0x0000 0000 32 */
388#define SH4A_PCIEPTCTLR2 (0x02044C) /* R/W R/W 0x0000 0000 32 */
389#define SH4A_PCIEPARL3 (0x020460) /* R/W R/W 0x0000 0000 32 */
390#define SH4A_PCIEPARH3 (0x020464) /* R/W R/W 0x0000 0000 32 */
391#define SH4A_PCIEPAMR3 (0x020468) /* R/W R/W 0x0000 0000 32 */
392#define SH4A_PCIEPTCTLR3 (0x02046C) /* R/W R/W 0x0000 0000 32 */
393#define SH4A_PCIEPARL4 (0x020480) /* R/W R/W 0x0000 0000 32 */
394#define SH4A_PCIEPARH4 (0x020484) /* R/W R/W 0x0000 0000 32 */
395#define SH4A_PCIEPAMR4 (0x020488) /* R/W R/W 0x0000 0000 32 */
396#define SH4A_PCIEPTCTLR4 (0x02048C) /* R/W R/W 0x0000 0000 32 */
397#define SH4A_PCIEPARL5 (0x0204A0) /* R/W R/W 0x0000 0000 32 */
398#define SH4A_PCIEPARH5 (0x0204A4) /* R/W R/W 0x0000 0000 32 */
399#define SH4A_PCIEPAMR5 (0x0204A8) /* R/W R/W 0x0000 0000 32 */
400#define SH4A_PCIEPTCTLR5 (0x0204AC) /* R/W R/W 0x0000 0000 32 */
401#define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */
402#define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */
403#define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */
404#define SH4A_PCIEDMDAR0 (0x021108) /* R/W R/W 0x0000 0000 32 */
405#define SH4A_PCIEDMDAHR0 (0x02110C) /* R/W R/W 0x0000 0000 32 */
406#define SH4A_PCIEDMBCNTR0 (0x021110) /* R/W R/W 0x0000 0000 32 */
407#define SH4A_PCIEDMSBCNTR0 (0x021114) /* R/W R/W 0x0000 0000 32 */
408#define SH4A_PCIEDMSTRR0 (0x021118) /* R/W R/W 0x0000 0000 32 */
409#define SH4A_PCIEDMCCAR0 (0x02111C) /* R/W R/W 0x0000 0000 32 */
410#define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */
411#define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */
412#define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */
413#define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */
414#define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */
415#define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */
416#define SH4A_PCIEDMDAHR1 (0x02114C) /* R/W R/W 0x0000 0000 32 */
417#define SH4A_PCIEDMBCNTR1 (0x021150) /* R/W R/W 0x0000 0000 32 */
418#define SH4A_PCIEDMSBCNTR1 (0x021154) /* R/W R/W 0x0000 0000 32 */
419#define SH4A_PCIEDMSTRR1 (0x021158) /* R/W R/W 0x0000 0000 32 */
420#define SH4A_PCIEDMCCAR1 (0x02115C) /* R/W R/W 0x0000 0000 32 */
421#define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */
422#define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */
423#define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */
424#define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */
425#define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */
426#define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */
427#define SH4A_PCIEDMDAHR2 (0x02118C) /* R/W R/W 0x0000 0000 32 */
428#define SH4A_PCIEDMBCNTR2 (0x021190) /* R/W R/W 0x0000 0000 32 */
429#define SH4A_PCIEDMSBCNTR2 (0x021194) /* R/W R/W 0x0000 0000 32 */
430#define SH4A_PCIEDMSTRR2 (0x021198) /* R/W R/W 0x0000 0000 32 */
431#define SH4A_PCIEDMCCAR2 (0x02119C) /* R/W R/W 0x0000 0000 32 */
432#define SH4A_PCIEDMCCR2 (0x0211A0) /* R/W R/W 0x0000 0000 32 */
433#define SH4A_PCIEDMCC2R2 (0x0211A4) /* R/W R/W 0x0000 0000 - */
434#define SH4A_PCIEDMCCCR2 (0x0211A8) /* R/W R/W 0x0000 0000 32 */
435#define SH4A_PCIEDMSAR3 (0x0211C0) /* R/W R/W 0x0000 0000 32 */
436#define SH4A_PCIEDMSAHR3 (0x0211C4) /* R/W R/W 0x0000 0000 32 */
437#define SH4A_PCIEDMDAR3 (0x0211C8) /* R/W R/W 0x0000 0000 32 */
438#define SH4A_PCIEDMDAHR3 (0x0211CC) /* R/W R/W 0x0000 0000 32 */
439#define SH4A_PCIEDMBCNTR3 (0x0211D0) /* R/W R/W 0x0000 0000 32 */
440#define SH4A_PCIEDMSBCNTR3 (0x0211D4) /* R/W R/W 0x0000 0000 32 */
441#define SH4A_PCIEDMSTRR3 (0x0211D8) /* R/W R/W 0x0000 0000 32 */
442#define SH4A_PCIEDMCCAR3 (0x0211DC) /* R/W R/W 0x0000 0000 32 */
443#define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */
444#define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */
445#define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */
446#define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */
447#define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */
448#define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */
449#define SH4A_PCIEPCICONF3 (0x04000C) /* R/W R/W 0x0000 0000 8/16/32 */
450#define SH4A_PCIEPCICONF4 (0x040010) /* - R/W - 8/16/32 */
451#define SH4A_PCIEPCICONF5 (0x040014) /* - R/W - 8/16/32 */
452#define SH4A_PCIEPCICONF6 (0x040018) /* - R/W - 8/16/32 */
453#define SH4A_PCIEPCICONF7 (0x04001C) /* - R/W - 8/16/32 */
454#define SH4A_PCIEPCICONF8 (0x040020) /* - R/W - 8/16/32 */
455#define SH4A_PCIEPCICONF9 (0x040024) /* - R/W - 8/16/32 */
456#define SH4A_PCIEPCICONF10 (0x040028) /* R/W R/W 0x0000 0000 8/16/32 */
457#define SH4A_PCIEPCICONF11 (0x04002C) /* R/W R/W 0x0000 0000 8/16/32 */
458#define SH4A_PCIEPCICONF12 (0x040030) /* R/W R/W 0x0000 0000 8/16/32 */
459#define SH4A_PCIEPCICONF13 (0x040034) /* R/W R/W 0x0000 0040 8/16/32 */
460#define SH4A_PCIEPCICONF14 (0x040038) /* R/W R/W 0x0000 0000 8/16/32 */
461#define SH4A_PCIEPCICONF15 (0x04003C) /* R/W R/W 0x0000 00FF 8/16/32 */
462#define SH4A_PCIEPMCAP0 (0x040040) /* R/W R 0x0003 5001 8/16/32 */
463#define SH4A_PCIEPMCAP1 (0x040044) /* R/W R/W 0x0000 0000 8/16/32 */
464#define SH4A_PCIEMSICAP0 (0x040050) /* R/W R/W 0x0180 7005 8/16/32 */
465#define SH4A_PCIEMSICAP1 (0x040054) /* R/W R/W 0x0000 0000 8/16/32 */
466#define SH4A_PCIEMSICAP2 (0x040058) /* R/W R/W 0x0000 0000 8/16/32 */
467#define SH4A_PCIEMSICAP3 (0x04005C) /* R/W R/W 0x0000 0000 8/16/32 */
468#define SH4A_PCIEMSICAP4 (0x040060) /* R/W R/W 0x0000 0000 8/16/32 */
469#define SH4A_PCIEMSICAP5 (0x040064) /* R/W R/W 0x0000 0000 8/16/32 */
470#define SH4A_PCIEEXPCAP0 (0x040070) /* R/W R/W 0x0001 0010 8/16/32 */
471#define SH4A_PCIEEXPCAP1 (0x040074) /* R/W R 0x0000 0005 8/16/32 */
472#define SH4A_PCIEEXPCAP2 (0x040078) /* R/W R/W 0x0000 0801 8/16/32 */
473#define SH4A_PCIEEXPCAP3 (0x04007C) /* R/W R 0x0003 F421 8/16/32 */
474#define SH4A_PCIEEXPCAP4 (0x040080) /* R/W R/W 0x0041 0000 8/16/32 */
475#define SH4A_PCIEEXPCAP5 (0x040084) /* R/W R/W 0x0000 0000 8/16/32 */
476#define SH4A_PCIEEXPCAP6 (0x040088) /* R/W R/W 0x0000 03C0 8/16/32 */
477#define SH4A_PCIEEXPCAP7 (0x04008C) /* R/W R/W 0x0000 0000 8/16/32 */
478#define SH4A_PCIEEXPCAP8 (0x040090) /* R/W R/W 0x0000 0000 8/16/32 */
479#define SH4A_PCIEVCCAP0 (0x040100) /* R/W R 0x1B01 0002 8/16/32 */
480#define SH4A_PCIEVCCAP1 (0x040104) /* R R 0x0000 0001 8/16/32 */
481#define SH4A_PCIEVCCAP2 (0x040108) /* R R 0x0000 0000 8/16/32 */
482#define SH4A_PCIEVCCAP3 (0x04010C) /* R R/W 0x0000 0000 8/16/32 */
483#define SH4A_PCIEVCCAP4 (0x040110) /* R/W R/W 0x0000 0000 8/16/32 */
484#define SH4A_PCIEVCCAP5 (0x040114) /* R/W R/W 0x8000 00FF 8/16/32 */
485#define SH4A_PCIEVCCAP6 (0x040118) /* R/W R 0x0002 0000 8/16/32 */
486#define SH4A_PCIEVCCAP7 (0x04011C) /* R/W R/W 0x0000 0000 8/16/32 */
487#define SH4A_PCIEVCCAP8 (0x040120) /* R/W R/W 0x0000 0000 8/16/32 */
488#define SH4A_PCIEVCCAP9 (0x040124) /* R/W R 0x0002 0000 8/16/32 */
489#define SH4A_PCIENUMCAP0 (0x0001B0) /* RW R 0x0001 0003 8/16/32 */
490#define SH4A_PCIENUMCAP1 (0x0001B4) /* R R 0x0000 0000 8/16/32 */
491#define SH4A_PCIENUMCAP2 (0x0001B8) /* R R 0x0000 0000 8/16/32 */
492#define SH4A_PCIEIDSETR0 (0x041000) /* R/W R 0x0000 FFFF 16/32 */
493#define SH4A_PCIEIDSETR1 (0x041004) /* R/W R 0xFF00 0000 16/32 */
494#define SH4A_PCIEBAR0SETR (0x041008) /* R/W R 0x0000 0000 16/32 */
495#define SH4A_PCIEBAR1SETR (0x04100C) /* R/W R 0x0000 0000 16/32 */
496#define SH4A_PCIEBAR2SETR (0x041010) /* R/W R 0x0000 0000 16/32 */
497#define SH4A_PCIEBAR3SETR (0x041014) /* R/W R 0x0000 0000 16/32 */
498#define SH4A_PCIEBAR4SETR (0x041018) /* R/W R 0x0000 0000 16/32 */
499#define SH4A_PCIEBAR5SETR (0x04101C) /* R/W R 0x0000 0000 16/32 */
500#define SH4A_PCIECISSETR (0x041020) /* R/W R 0x0000 0000 16/32 */
501#define SH4A_PCIEIDSETR2 (0x041024) /* R/W R 0x0000 0000 16/32 */
502#define SH4A_PCIEEROMSETR (0x041028) /* R/W R 0x0000 0000 16/32 */
503#define SH4A_PCIEDSERSETR0 (0x04102C) /* R/W R 0x0000 0000 16/32 */
504#define SH4A_PCIEDSERSETR1 (0x041030) /* R/W R 0x0000 0000 16/32 */
505#define SH4A_PCIECTLR (0x041040) /* R/W R 0x0000 0000 16/32 */
506#define SH4A_PCIETLSR (0x041044) /* R/W1C R 0x0000 0000 16/32 */
507#define SH4A_PCIETLCTLR (0x041048) /* R/W R 0x0000 0000 16/32 */
508#define SH4A_PCIEDLSR (0x04104C) /* R/W1C R 0x4003 0000 16/32 */
509#define SH4A_PCIEDLCTLR (0x041050) /* R R 0x0000 0000 16/32 */
510#define SH4A_PCIEMACSR (0x041054) /* R/W1C R 0x0041 0000 16/32 */
511#define SH4A_PCIEMACCTLR (0x041058) /* R/W R 0x0000 0000 16/32 */
512#define PCIEMACCTLR_SCR_DIS (1 << 27) /* scramble disable */
513#define SH4A_PCIEPMSTR (0x04105C) /* R/W1C R 0x0000 0000 16/32 */
514#define SH4A_PCIEPMCTLR (0x041060) /* R/W R 0x0000 0000 16/32 */
515#define SH4A_PCIETLINTENR (0x041064) /* R/W R 0x0000 0000 16/32 */
516#define SH4A_PCIEDLINTENR (0x041068) /* R/W R 0x0000 0000 16/32 */
517#define PCIEDLINTENR_DLL_ACT_ENABLE (1 << 31) /* DL active irq */
518#define SH4A_PCIEMACINTENR (0x04106C) /* R/W R 0x0000 0000 16/32 */
519#define SH4A_PCIEPMINTENR (0x041070) /* R/W R 0x0000 0000 16/32 */
520#define SH4A_PCIETXDCTLR (0x044000) /* R/W - H'00000000_00000000 32/64 */
521#define SH4A_PCIETXCTLR (0x044020) /* R/W - H'00000000_00000000 32/64 */
522#define SH4A_PCIETXSR (0x044028) /* R - H'00000000_00000000 32/64 */
523#define SH4A_PCIETXVC0DCTLR (0x044100) /* R/W - H'00000000_00000000 32/64 */
524#define SH4A_PCIETXVC0SR (0x044108) /* R/W - H'00888000_00000000 32/64 */
525#define SH4A_PCIEVC0PDTXR (0x044110) /* W - H'00000000_00000000 32/64 */
526#define SH4A_PCIEVC0PHTXR (0x044118) /* W - H'00000000_00000000 32/64 */
527#define SH4A_PCIEVC0NPDTXR (0x044120) /* W - H'00000000_00000000 32/64 */
528#define SH4A_PCIEVC0NPHTXR (0x044128) /* W - H'00000000_00000000 32/64 */
529#define SH4A_PCIEVC0CDTXR (0x044130) /* W - H'00000000_00000000 32/64 */
530#define SH4A_PCIEVC0CHTXR (0x044138) /* W - H'00000000_00000000 32/64 */
531#define SH4A_PCIETXVCXDCTLR (0x044200) /* R/W - H'00000000_00000000 32/64 */
532#define SH4A_PCIETXVCXSR (0x044208) /* R/W - H'00000000_00000000 32/64 */
533#define SH4A_PCIEVCXPDTXR (0x044210) /* W - H'00000000_00000000 32/64 */
534#define SH4A_PCIEVCXPHTXR (0x044218) /* W - H'00000000_00000000 32/64 */
535#define SH4A_PCIEVCXNPDTXR (0x044220) /* W - H'00000000_00000000 32/64 */
536#define SH4A_PCIEVCXNPHTXR (0x044228) /* W - H'00000000_00000000 32/64 */
537#define SH4A_PCIEVCXCDTXR (0x044230) /* W - H'00000000_00000000 32/64 */
538#define SH4A_PCIEVCXCHTXR (0x044238) /* W - H'00000000_00000000 32/64 */
539#define SH4A_PCIERDCTLR (0x046000) /* RW - H'00000000_00000000 32/64 */
540#define SH4A_PCIEERPCTLR (0x046008) /* RW - H'00000000_00000000 32/64 */
541#define SH4A_PCIEERPHR (0x046010) /* R - H'00000000_00000000 32/64 */
542#define SH4A_PCIEERPERR (0x046018) /* R - H'00000000_00000000 32/64 */
543#define SH4A_PCIERXVC0DCTLR (0x046100) /* RW - H'00000000_00000000 32/64 */
544#define SH4A_PCIERXVC0SR (0x046108) /* RW - H'00000000_00000000 32/64 */
545#define SH4A_PCIEVC0PDRXR (0x046140) /* R - H'00000000_00000000 32/64 */
546#define SH4A_PCIEVC0PHRXR (0x046148) /* R - H'00000000_00000000 32/64 */
547#define SH4A_PCIEVC0PERR (0x046150) /* R - H'00000000_00000000 32/64 */
548#define SH4A_PCIEVC0NPDRXR (0x046158) /* R - H'00000000_00000000 32/64 */
549#define SH4A_PCIEVC0NPHRXR (0x046160) /* R - H'00000000_00000000 32/64 */
550#define SH4A_PCIEVC0NPERR (0x046168) /* R - H'00000000_00000000 32/64 */
551#define SH4A_PCIEVC0CDRXR (0x046170) /* R - H'00000000_00000000 32/64 */
552#define SH4A_PCIEVC0CHRXR (0x046178) /* R - H'00000000_00000000 32/64 */
553#define SH4A_PCIEVC0CERR (0x046180) /* R - H'00000000_00000000 32/64 */
554#define SH4A_PCIERXVCXDCTLR (0x046200) /* RW - H'00000000_00000000 32/64 */
555#define SH4A_PCIERXVCXSR (0x046208) /* RW - H'00000000_00000000 32/64 */
556#define SH4A_PCIEVCXPDRXR (0x046240) /* R - H'00000000_00000000 32/64 */
557#define SH4A_PCIEVCXPHRXR (0x046248) /* R H'00000000_00000000 32/64 */
558#define SH4A_PCIEVCXPERR (0x046250) /* R H'00000000_00000000 32/64 */
559#define SH4A_PCIEVCXNPDRXR (0x046258) /* R H'00000000_00000000 32/64 */
560#define SH4A_PCIEVCXNPHRXR (0x046260) /* R H'00000000_00000000 32/64 */
561#define SH4A_PCIEVCXNPERR (0x046268) /* R H'00000000_00000000 32/64 */
562#define SH4A_PCIEVCXCDRXR (0x046270) /* R H'00000000_00000000 32/64 */
563#define SH4A_PCIEVCXCHRXR (0x046278) /* R H'00000000_00000000 32/64 */
564#define SH4A_PCIEVCXCERR (0x046280) /* R H'00000000_00000000 32/64 */
565
566/* SSI Register Definition for MSI WORK AROUND --hamada */
567#define SH4A_PCI_SSI_BASE 0xFFE00000 /* spw config address */
568#define SH4A_PCI_SSI_BASE_LEN 0x00100000 /* 1MB */
569
570#define SH4A_SSICR0 (0x000000)
571#define SH4A_SSICR1 (0x010000)
572#define SH4A_SSICR2 (0x020000)
573#define SH4A_SSICR3 (0x030000)
574
575#define PCI_REG(x) ((x) + 0x40000)
576
577static inline void
578pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg)
579{
580 __raw_writel(val, chan->reg_base + reg);
581}
582
583static inline unsigned long
584pci_read_reg(struct pci_channel *chan, unsigned long reg)
585{
586 return __raw_readl(chan->reg_base + reg);
587}
588
589#endif /* __PCI_SH7786_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 11:09:21 -0500