MIPS: Oprofile: Fix Loongson irq handler

    
    The interrupt enable bit for the performance counters is in the Control
    Register $24, not in the counter register.
    loongson2_perfcount_handler(), we need to use
    
    Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn>
    Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: http://patchwork.linux-mips.org/patch/1198/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index 29e2326b625..fa3bf661ae2 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
          */
 
         /* Check whether the irq belongs to me */
-        enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
+        enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
         if (!enabled)
                 return IRQ_NONE;
         enabled = reg.cnt1_enabled | reg.cnt2_enabled;