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authorSeungwhan Youn <sw.youn@samsung.com>2010-10-13 21:39:15 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-25 03:06:00 -0400
commit42a6e20e4fd4755e6b4539891a4f20905af18dcd (patch)
treef161440a87427b04fc3d85f75fdffe91bf2bca02 /arch
parentd4b34c6c849d67b7afaa90d55dc7fab981c72950 (diff)
ARM: S5PV210: Fix wrong EPLL rate getting on setup clocks
This patch fix wrong EPLL getting on setup clocks on S5PV210. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-s5pv210/clock.c3
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-clock.h1
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index b9c9f3bd295..00a721771a4 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -1082,7 +1082,8 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
1082 1082
1083 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); 1083 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1084 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); 1084 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1085 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); 1085 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1086 __raw_readl(S5P_EPLL_CON1), pll_4600);
1086 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 1087 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1087 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); 1088 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1088 1089
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 61b55c8e438..ebaabe021af 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -25,6 +25,7 @@
25#define S5P_APLL_CON S5P_CLKREG(0x100) 25#define S5P_APLL_CON S5P_CLKREG(0x100)
26#define S5P_MPLL_CON S5P_CLKREG(0x108) 26#define S5P_MPLL_CON S5P_CLKREG(0x108)
27#define S5P_EPLL_CON S5P_CLKREG(0x110) 27#define S5P_EPLL_CON S5P_CLKREG(0x110)
28#define S5P_EPLL_CON1 S5P_CLKREG(0x114)
28#define S5P_VPLL_CON S5P_CLKREG(0x120) 29#define S5P_VPLL_CON S5P_CLKREG(0x120)
29 30
30#define S5P_CLK_SRC0 S5P_CLKREG(0x200) 31#define S5P_CLK_SRC0 S5P_CLKREG(0x200)