diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-03-27 10:59:07 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-03-27 10:59:07 -0500 |
commit | 3747b36eeab93d8969e86987bbc1d44971229b26 (patch) | |
tree | 2d6360f93f03b945644fd8a9e002f0154643798b /arch | |
parent | 4682adcfb06448827fbdfd8b6c636796de569b7d (diff) |
[ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX.
Mark page table walks with outer-cacheable attribute, and enable no-execute
in page tables.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mm/proc-v6.S | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 9a7e7c096aa..ee6f1529873 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -21,6 +21,14 @@ | |||
21 | 21 | ||
22 | #define D_CACHE_LINE_SIZE 32 | 22 | #define D_CACHE_LINE_SIZE 32 |
23 | 23 | ||
24 | #define TTB_C (1 << 0) | ||
25 | #define TTB_S (1 << 1) | ||
26 | #define TTB_IMP (1 << 2) | ||
27 | #define TTB_RGN_NC (0 << 3) | ||
28 | #define TTB_RGN_WBWA (1 << 3) | ||
29 | #define TTB_RGN_WT (2 << 3) | ||
30 | #define TTB_RGN_WB (3 << 3) | ||
31 | |||
24 | .macro cpsie, flags | 32 | .macro cpsie, flags |
25 | .ifc \flags, f | 33 | .ifc \flags, f |
26 | .long 0xf1080040 | 34 | .long 0xf1080040 |
@@ -115,7 +123,7 @@ ENTRY(cpu_v6_switch_mm) | |||
115 | mov r2, #0 | 123 | mov r2, #0 |
116 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | 124 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id |
117 | #ifdef CONFIG_SMP | 125 | #ifdef CONFIG_SMP |
118 | orr r0, r0, #2 @ set shared pgtable | 126 | orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable |
119 | #endif | 127 | #endif |
120 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB | 128 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
121 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer | 129 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer |
@@ -161,8 +169,8 @@ ENTRY(cpu_v6_set_pte) | |||
161 | tst r1, #L_PTE_YOUNG | 169 | tst r1, #L_PTE_YOUNG |
162 | biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK | 170 | biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK |
163 | 171 | ||
164 | @ tst r1, #L_PTE_EXEC | 172 | tst r1, #L_PTE_EXEC |
165 | @ orreq r2, r2, #PTE_EXT_XN | 173 | orreq r2, r2, #PTE_EXT_XN |
166 | 174 | ||
167 | tst r1, #L_PTE_PRESENT | 175 | tst r1, #L_PTE_PRESENT |
168 | moveq r2, #0 | 176 | moveq r2, #0 |
@@ -221,7 +229,7 @@ __v6_setup: | |||
221 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs | 229 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs |
222 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register | 230 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register |
223 | #ifdef CONFIG_SMP | 231 | #ifdef CONFIG_SMP |
224 | orr r4, r4, #2 @ set shared pgtable | 232 | orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable |
225 | #endif | 233 | #endif |
226 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 234 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
227 | #ifdef CONFIG_VFP | 235 | #ifdef CONFIG_VFP |