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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-28 13:56:34 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-28 13:56:34 -0400
commit04830fccdcafa7e0ea913990ae56437253553fef (patch)
tree16d423628a516f544a0e5bb8fd4f00d88a55395f /arch
parent571503e10045c89af951962ea0bb783482663aad (diff)
parent1486a7409b42ec434be310e091ef68660a2f6cd0 (diff)
Merge branch 'gpio/next' of git://git.secretlab.ca/git/linux-2.6
* 'gpio/next' of git://git.secretlab.ca/git/linux-2.6: gpio/pch_gpio: Support new device ML7223 gpio: make gpio_{request,free}_array gpio array parameter const GPIO: OMAP: move to drivers/gpio GPIO: OMAP: move register offset defines into <plat/gpio.h> gpio: Convert gpio_is_valid to return bool gpio: Move the s5pc100 GPIO to drivers/gpio gpio: Move the s5pv210 GPIO to drivers/gpio gpio: Move the exynos4 GPIO to drivers/gpio gpio: Move to Samsung common GPIO library to drivers/gpio gpio/nomadik: add function to read GPIO pull down status gpio/nomadik: show all pins in debug gpio: move Nomadik GPIO driver to drivers/gpio gpio: move U300 GPIO driver to drivers/gpio langwell_gpio: add runtime pm support gpio/pca953x: Add support for pca9574 and pca9575 devices gpio/cs5535: Show explicit dependency between gpio_cs5535 and mfd_cs5535
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-exynos4/Makefile2
-rw-r--r--arch/arm/mach-exynos4/gpiolib.c365
-rw-r--r--arch/arm/mach-nomadik/Kconfig1
-rw-r--r--arch/arm/mach-s5pc100/Makefile2
-rw-r--r--arch/arm/mach-s5pc100/gpiolib.c355
-rw-r--r--arch/arm/mach-s5pv210/Makefile2
-rw-r--r--arch/arm/mach-s5pv210/gpiolib.c288
-rw-r--r--arch/arm/mach-u300/Makefile2
-rw-r--r--arch/arm/mach-u300/gpio.c700
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/plat-nomadik/Kconfig5
-rw-r--r--arch/arm/plat-nomadik/Makefile1
-rw-r--r--arch/arm/plat-nomadik/gpio.c1020
-rw-r--r--arch/arm/plat-nomadik/include/plat/gpio.h2
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/gpio.c2112
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h103
-rw-r--r--arch/arm/plat-samsung/Makefile1
-rw-r--r--arch/arm/plat-samsung/gpiolib.c206
19 files changed, 110 insertions, 5060 deletions
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 683fc387c8a..a9bb94fabaa 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,7 +13,7 @@ obj- :=
13# Core support for EXYNOS4 system 13# Core support for EXYNOS4 system
14 14
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o 16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o
17obj-$(CONFIG_PM) += pm.o sleep.o 17obj-$(CONFIG_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o 18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
19obj-$(CONFIG_CPU_IDLE) += cpuidle.o 19obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-exynos4/gpiolib.c b/arch/arm/mach-exynos4/gpiolib.c
deleted file mode 100644
index d54ca6adb66..00000000000
--- a/arch/arm/mach-exynos4/gpiolib.c
+++ /dev/null
@@ -1,365 +0,0 @@
1/* linux/arch/arm/mach-exynos4/gpiolib.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24static struct s3c_gpio_cfg gpio_cfg = {
25 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
26 .set_pull = s3c_gpio_setpull_updown,
27 .get_pull = s3c_gpio_getpull_updown,
28};
29
30static struct s3c_gpio_cfg gpio_cfg_noint = {
31 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
32 .set_pull = s3c_gpio_setpull_updown,
33 .get_pull = s3c_gpio_getpull_updown,
34};
35
36/*
37 * Following are the gpio banks in v310.
38 *
39 * The 'config' member when left to NULL, is initialized to the default
40 * structure gpio_cfg in the init function below.
41 *
42 * The 'base' member is also initialized in the init function below.
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here.
45 */
46static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
47 {
48 .chip = {
49 .base = EXYNOS4_GPA0(0),
50 .ngpio = EXYNOS4_GPIO_A0_NR,
51 .label = "GPA0",
52 },
53 }, {
54 .chip = {
55 .base = EXYNOS4_GPA1(0),
56 .ngpio = EXYNOS4_GPIO_A1_NR,
57 .label = "GPA1",
58 },
59 }, {
60 .chip = {
61 .base = EXYNOS4_GPB(0),
62 .ngpio = EXYNOS4_GPIO_B_NR,
63 .label = "GPB",
64 },
65 }, {
66 .chip = {
67 .base = EXYNOS4_GPC0(0),
68 .ngpio = EXYNOS4_GPIO_C0_NR,
69 .label = "GPC0",
70 },
71 }, {
72 .chip = {
73 .base = EXYNOS4_GPC1(0),
74 .ngpio = EXYNOS4_GPIO_C1_NR,
75 .label = "GPC1",
76 },
77 }, {
78 .chip = {
79 .base = EXYNOS4_GPD0(0),
80 .ngpio = EXYNOS4_GPIO_D0_NR,
81 .label = "GPD0",
82 },
83 }, {
84 .chip = {
85 .base = EXYNOS4_GPD1(0),
86 .ngpio = EXYNOS4_GPIO_D1_NR,
87 .label = "GPD1",
88 },
89 }, {
90 .chip = {
91 .base = EXYNOS4_GPE0(0),
92 .ngpio = EXYNOS4_GPIO_E0_NR,
93 .label = "GPE0",
94 },
95 }, {
96 .chip = {
97 .base = EXYNOS4_GPE1(0),
98 .ngpio = EXYNOS4_GPIO_E1_NR,
99 .label = "GPE1",
100 },
101 }, {
102 .chip = {
103 .base = EXYNOS4_GPE2(0),
104 .ngpio = EXYNOS4_GPIO_E2_NR,
105 .label = "GPE2",
106 },
107 }, {
108 .chip = {
109 .base = EXYNOS4_GPE3(0),
110 .ngpio = EXYNOS4_GPIO_E3_NR,
111 .label = "GPE3",
112 },
113 }, {
114 .chip = {
115 .base = EXYNOS4_GPE4(0),
116 .ngpio = EXYNOS4_GPIO_E4_NR,
117 .label = "GPE4",
118 },
119 }, {
120 .chip = {
121 .base = EXYNOS4_GPF0(0),
122 .ngpio = EXYNOS4_GPIO_F0_NR,
123 .label = "GPF0",
124 },
125 }, {
126 .chip = {
127 .base = EXYNOS4_GPF1(0),
128 .ngpio = EXYNOS4_GPIO_F1_NR,
129 .label = "GPF1",
130 },
131 }, {
132 .chip = {
133 .base = EXYNOS4_GPF2(0),
134 .ngpio = EXYNOS4_GPIO_F2_NR,
135 .label = "GPF2",
136 },
137 }, {
138 .chip = {
139 .base = EXYNOS4_GPF3(0),
140 .ngpio = EXYNOS4_GPIO_F3_NR,
141 .label = "GPF3",
142 },
143 },
144};
145
146static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
147 {
148 .chip = {
149 .base = EXYNOS4_GPJ0(0),
150 .ngpio = EXYNOS4_GPIO_J0_NR,
151 .label = "GPJ0",
152 },
153 }, {
154 .chip = {
155 .base = EXYNOS4_GPJ1(0),
156 .ngpio = EXYNOS4_GPIO_J1_NR,
157 .label = "GPJ1",
158 },
159 }, {
160 .chip = {
161 .base = EXYNOS4_GPK0(0),
162 .ngpio = EXYNOS4_GPIO_K0_NR,
163 .label = "GPK0",
164 },
165 }, {
166 .chip = {
167 .base = EXYNOS4_GPK1(0),
168 .ngpio = EXYNOS4_GPIO_K1_NR,
169 .label = "GPK1",
170 },
171 }, {
172 .chip = {
173 .base = EXYNOS4_GPK2(0),
174 .ngpio = EXYNOS4_GPIO_K2_NR,
175 .label = "GPK2",
176 },
177 }, {
178 .chip = {
179 .base = EXYNOS4_GPK3(0),
180 .ngpio = EXYNOS4_GPIO_K3_NR,
181 .label = "GPK3",
182 },
183 }, {
184 .chip = {
185 .base = EXYNOS4_GPL0(0),
186 .ngpio = EXYNOS4_GPIO_L0_NR,
187 .label = "GPL0",
188 },
189 }, {
190 .chip = {
191 .base = EXYNOS4_GPL1(0),
192 .ngpio = EXYNOS4_GPIO_L1_NR,
193 .label = "GPL1",
194 },
195 }, {
196 .chip = {
197 .base = EXYNOS4_GPL2(0),
198 .ngpio = EXYNOS4_GPIO_L2_NR,
199 .label = "GPL2",
200 },
201 }, {
202 .config = &gpio_cfg_noint,
203 .chip = {
204 .base = EXYNOS4_GPY0(0),
205 .ngpio = EXYNOS4_GPIO_Y0_NR,
206 .label = "GPY0",
207 },
208 }, {
209 .config = &gpio_cfg_noint,
210 .chip = {
211 .base = EXYNOS4_GPY1(0),
212 .ngpio = EXYNOS4_GPIO_Y1_NR,
213 .label = "GPY1",
214 },
215 }, {
216 .config = &gpio_cfg_noint,
217 .chip = {
218 .base = EXYNOS4_GPY2(0),
219 .ngpio = EXYNOS4_GPIO_Y2_NR,
220 .label = "GPY2",
221 },
222 }, {
223 .config = &gpio_cfg_noint,
224 .chip = {
225 .base = EXYNOS4_GPY3(0),
226 .ngpio = EXYNOS4_GPIO_Y3_NR,
227 .label = "GPY3",
228 },
229 }, {
230 .config = &gpio_cfg_noint,
231 .chip = {
232 .base = EXYNOS4_GPY4(0),
233 .ngpio = EXYNOS4_GPIO_Y4_NR,
234 .label = "GPY4",
235 },
236 }, {
237 .config = &gpio_cfg_noint,
238 .chip = {
239 .base = EXYNOS4_GPY5(0),
240 .ngpio = EXYNOS4_GPIO_Y5_NR,
241 .label = "GPY5",
242 },
243 }, {
244 .config = &gpio_cfg_noint,
245 .chip = {
246 .base = EXYNOS4_GPY6(0),
247 .ngpio = EXYNOS4_GPIO_Y6_NR,
248 .label = "GPY6",
249 },
250 }, {
251 .base = (S5P_VA_GPIO2 + 0xC00),
252 .config = &gpio_cfg_noint,
253 .irq_base = IRQ_EINT(0),
254 .chip = {
255 .base = EXYNOS4_GPX0(0),
256 .ngpio = EXYNOS4_GPIO_X0_NR,
257 .label = "GPX0",
258 .to_irq = samsung_gpiolib_to_irq,
259 },
260 }, {
261 .base = (S5P_VA_GPIO2 + 0xC20),
262 .config = &gpio_cfg_noint,
263 .irq_base = IRQ_EINT(8),
264 .chip = {
265 .base = EXYNOS4_GPX1(0),
266 .ngpio = EXYNOS4_GPIO_X1_NR,
267 .label = "GPX1",
268 .to_irq = samsung_gpiolib_to_irq,
269 },
270 }, {
271 .base = (S5P_VA_GPIO2 + 0xC40),
272 .config = &gpio_cfg_noint,
273 .irq_base = IRQ_EINT(16),
274 .chip = {
275 .base = EXYNOS4_GPX2(0),
276 .ngpio = EXYNOS4_GPIO_X2_NR,
277 .label = "GPX2",
278 .to_irq = samsung_gpiolib_to_irq,
279 },
280 }, {
281 .base = (S5P_VA_GPIO2 + 0xC60),
282 .config = &gpio_cfg_noint,
283 .irq_base = IRQ_EINT(24),
284 .chip = {
285 .base = EXYNOS4_GPX3(0),
286 .ngpio = EXYNOS4_GPIO_X3_NR,
287 .label = "GPX3",
288 .to_irq = samsung_gpiolib_to_irq,
289 },
290 },
291};
292
293static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
294 {
295 .chip = {
296 .base = EXYNOS4_GPZ(0),
297 .ngpio = EXYNOS4_GPIO_Z_NR,
298 .label = "GPZ",
299 },
300 },
301};
302
303static __init int exynos4_gpiolib_init(void)
304{
305 struct s3c_gpio_chip *chip;
306 int i;
307 int group = 0;
308 int nr_chips;
309
310 /* GPIO part 1 */
311
312 chip = exynos4_gpio_part1_4bit;
313 nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
314
315 for (i = 0; i < nr_chips; i++, chip++) {
316 if (chip->config == NULL) {
317 chip->config = &gpio_cfg;
318 /* Assign the GPIO interrupt group */
319 chip->group = group++;
320 }
321 if (chip->base == NULL)
322 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
323 }
324
325 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
326
327 /* GPIO part 2 */
328
329 chip = exynos4_gpio_part2_4bit;
330 nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
331
332 for (i = 0; i < nr_chips; i++, chip++) {
333 if (chip->config == NULL) {
334 chip->config = &gpio_cfg;
335 /* Assign the GPIO interrupt group */
336 chip->group = group++;
337 }
338 if (chip->base == NULL)
339 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
340 }
341
342 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
343
344 /* GPIO part 3 */
345
346 chip = exynos4_gpio_part3_4bit;
347 nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
348
349 for (i = 0; i < nr_chips; i++, chip++) {
350 if (chip->config == NULL) {
351 chip->config = &gpio_cfg;
352 /* Assign the GPIO interrupt group */
353 chip->group = group++;
354 }
355 if (chip->base == NULL)
356 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
357 }
358
359 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
360 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
361 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
362
363 return 0;
364}
365core_initcall(exynos4_gpiolib_init);
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 71f3ea62397..3c5e0f522e9 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -6,7 +6,6 @@ config MACH_NOMADIK_8815NHK
6 bool "ST 8815 Nomadik Hardware Kit (evaluation board)" 6 bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
7 select NOMADIK_8815 7 select NOMADIK_8815
8 select HAS_MTU 8 select HAS_MTU
9 select NOMADIK_GPIO
10 9
11endmenu 10endmenu
12 11
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index eecab57d2e5..a5e6e608b49 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,7 +11,7 @@ obj- :=
11 11
12# Core support for S5PC100 system 12# Core support for S5PC100 system
13 13
14obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o 14obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o
15obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o 15obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
16obj-$(CONFIG_CPU_S5PC100) += dma.o 16obj-$(CONFIG_CPU_S5PC100) += dma.o
17 17
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
deleted file mode 100644
index 2842394b28b..00000000000
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ /dev/null
@@ -1,355 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2009 Samsung Electronics Co
7 * Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * S5PC100 - GPIOlib support
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19#include <linux/gpio.h>
20
21#include <mach/map.h>
22#include <mach/regs-gpio.h>
23
24#include <plat/gpio-core.h>
25#include <plat/gpio-cfg.h>
26#include <plat/gpio-cfg-helpers.h>
27
28/* S5PC100 GPIO bank summary:
29 *
30 * Bank GPIOs Style INT Type
31 * A0 8 4Bit GPIO_INT0
32 * A1 5 4Bit GPIO_INT1
33 * B 8 4Bit GPIO_INT2
34 * C 5 4Bit GPIO_INT3
35 * D 7 4Bit GPIO_INT4
36 * E0 8 4Bit GPIO_INT5
37 * E1 6 4Bit GPIO_INT6
38 * F0 8 4Bit GPIO_INT7
39 * F1 8 4Bit GPIO_INT8
40 * F2 8 4Bit GPIO_INT9
41 * F3 4 4Bit GPIO_INT10
42 * G0 8 4Bit GPIO_INT11
43 * G1 3 4Bit GPIO_INT12
44 * G2 7 4Bit GPIO_INT13
45 * G3 7 4Bit GPIO_INT14
46 * H0 8 4Bit WKUP_INT
47 * H1 8 4Bit WKUP_INT
48 * H2 8 4Bit WKUP_INT
49 * H3 8 4Bit WKUP_INT
50 * I 8 4Bit GPIO_INT15
51 * J0 8 4Bit GPIO_INT16
52 * J1 5 4Bit GPIO_INT17
53 * J2 8 4Bit GPIO_INT18
54 * J3 8 4Bit GPIO_INT19
55 * J4 4 4Bit GPIO_INT20
56 * K0 8 4Bit None
57 * K1 6 4Bit None
58 * K2 8 4Bit None
59 * K3 8 4Bit None
60 * L0 8 4Bit None
61 * L1 8 4Bit None
62 * L2 8 4Bit None
63 * L3 8 4Bit None
64 */
65
66static struct s3c_gpio_cfg gpio_cfg = {
67 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
68 .set_pull = s3c_gpio_setpull_updown,
69 .get_pull = s3c_gpio_getpull_updown,
70};
71
72static struct s3c_gpio_cfg gpio_cfg_eint = {
73 .cfg_eint = 0xf,
74 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
75 .set_pull = s3c_gpio_setpull_updown,
76 .get_pull = s3c_gpio_getpull_updown,
77};
78
79static struct s3c_gpio_cfg gpio_cfg_noint = {
80 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
81 .set_pull = s3c_gpio_setpull_updown,
82 .get_pull = s3c_gpio_getpull_updown,
83};
84
85/*
86 * GPIO bank's base address given the index of the bank in the
87 * list of all gpio banks.
88 */
89#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
90
91/*
92 * Following are the gpio banks in S5PC100.
93 *
94 * The 'config' member when left to NULL, is initialized to the default
95 * structure gpio_cfg in the init function below.
96 *
97 * The 'base' member is also initialized in the init function below.
98 * Note: The initialization of 'base' member of s3c_gpio_chip structure
99 * uses the above macro and depends on the banks being listed in order here.
100 */
101static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
102 {
103 .chip = {
104 .base = S5PC100_GPA0(0),
105 .ngpio = S5PC100_GPIO_A0_NR,
106 .label = "GPA0",
107 },
108 }, {
109 .chip = {
110 .base = S5PC100_GPA1(0),
111 .ngpio = S5PC100_GPIO_A1_NR,
112 .label = "GPA1",
113 },
114 }, {
115 .chip = {
116 .base = S5PC100_GPB(0),
117 .ngpio = S5PC100_GPIO_B_NR,
118 .label = "GPB",
119 },
120 }, {
121 .chip = {
122 .base = S5PC100_GPC(0),
123 .ngpio = S5PC100_GPIO_C_NR,
124 .label = "GPC",
125 },
126 }, {
127 .chip = {
128 .base = S5PC100_GPD(0),
129 .ngpio = S5PC100_GPIO_D_NR,
130 .label = "GPD",
131 },
132 }, {
133 .chip = {
134 .base = S5PC100_GPE0(0),
135 .ngpio = S5PC100_GPIO_E0_NR,
136 .label = "GPE0",
137 },
138 }, {
139 .chip = {
140 .base = S5PC100_GPE1(0),
141 .ngpio = S5PC100_GPIO_E1_NR,
142 .label = "GPE1",
143 },
144 }, {
145 .chip = {
146 .base = S5PC100_GPF0(0),
147 .ngpio = S5PC100_GPIO_F0_NR,
148 .label = "GPF0",
149 },
150 }, {
151 .chip = {
152 .base = S5PC100_GPF1(0),
153 .ngpio = S5PC100_GPIO_F1_NR,
154 .label = "GPF1",
155 },
156 }, {
157 .chip = {
158 .base = S5PC100_GPF2(0),
159 .ngpio = S5PC100_GPIO_F2_NR,
160 .label = "GPF2",
161 },
162 }, {
163 .chip = {
164 .base = S5PC100_GPF3(0),
165 .ngpio = S5PC100_GPIO_F3_NR,
166 .label = "GPF3",
167 },
168 }, {
169 .chip = {
170 .base = S5PC100_GPG0(0),
171 .ngpio = S5PC100_GPIO_G0_NR,
172 .label = "GPG0",
173 },
174 }, {
175 .chip = {
176 .base = S5PC100_GPG1(0),
177 .ngpio = S5PC100_GPIO_G1_NR,
178 .label = "GPG1",
179 },
180 }, {
181 .chip = {
182 .base = S5PC100_GPG2(0),
183 .ngpio = S5PC100_GPIO_G2_NR,
184 .label = "GPG2",
185 },
186 }, {
187 .chip = {
188 .base = S5PC100_GPG3(0),
189 .ngpio = S5PC100_GPIO_G3_NR,
190 .label = "GPG3",
191 },
192 }, {
193 .chip = {
194 .base = S5PC100_GPI(0),
195 .ngpio = S5PC100_GPIO_I_NR,
196 .label = "GPI",
197 },
198 }, {
199 .chip = {
200 .base = S5PC100_GPJ0(0),
201 .ngpio = S5PC100_GPIO_J0_NR,
202 .label = "GPJ0",
203 },
204 }, {
205 .chip = {
206 .base = S5PC100_GPJ1(0),
207 .ngpio = S5PC100_GPIO_J1_NR,
208 .label = "GPJ1",
209 },
210 }, {
211 .chip = {
212 .base = S5PC100_GPJ2(0),
213 .ngpio = S5PC100_GPIO_J2_NR,
214 .label = "GPJ2",
215 },
216 }, {
217 .chip = {
218 .base = S5PC100_GPJ3(0),
219 .ngpio = S5PC100_GPIO_J3_NR,
220 .label = "GPJ3",
221 },
222 }, {
223 .chip = {
224 .base = S5PC100_GPJ4(0),
225 .ngpio = S5PC100_GPIO_J4_NR,
226 .label = "GPJ4",
227 },
228 }, {
229 .config = &gpio_cfg_noint,
230 .chip = {
231 .base = S5PC100_GPK0(0),
232 .ngpio = S5PC100_GPIO_K0_NR,
233 .label = "GPK0",
234 },
235 }, {
236 .config = &gpio_cfg_noint,
237 .chip = {
238 .base = S5PC100_GPK1(0),
239 .ngpio = S5PC100_GPIO_K1_NR,
240 .label = "GPK1",
241 },
242 }, {
243 .config = &gpio_cfg_noint,
244 .chip = {
245 .base = S5PC100_GPK2(0),
246 .ngpio = S5PC100_GPIO_K2_NR,
247 .label = "GPK2",
248 },
249 }, {
250 .config = &gpio_cfg_noint,
251 .chip = {
252 .base = S5PC100_GPK3(0),
253 .ngpio = S5PC100_GPIO_K3_NR,
254 .label = "GPK3",
255 },
256 }, {
257 .config = &gpio_cfg_noint,
258 .chip = {
259 .base = S5PC100_GPL0(0),
260 .ngpio = S5PC100_GPIO_L0_NR,
261 .label = "GPL0",
262 },
263 }, {
264 .config = &gpio_cfg_noint,
265 .chip = {
266 .base = S5PC100_GPL1(0),
267 .ngpio = S5PC100_GPIO_L1_NR,
268 .label = "GPL1",
269 },
270 }, {
271 .config = &gpio_cfg_noint,
272 .chip = {
273 .base = S5PC100_GPL2(0),
274 .ngpio = S5PC100_GPIO_L2_NR,
275 .label = "GPL2",
276 },
277 }, {
278 .config = &gpio_cfg_noint,
279 .chip = {
280 .base = S5PC100_GPL3(0),
281 .ngpio = S5PC100_GPIO_L3_NR,
282 .label = "GPL3",
283 },
284 }, {
285 .config = &gpio_cfg_noint,
286 .chip = {
287 .base = S5PC100_GPL4(0),
288 .ngpio = S5PC100_GPIO_L4_NR,
289 .label = "GPL4",
290 },
291 }, {
292 .base = (S5P_VA_GPIO + 0xC00),
293 .config = &gpio_cfg_eint,
294 .irq_base = IRQ_EINT(0),
295 .chip = {
296 .base = S5PC100_GPH0(0),
297 .ngpio = S5PC100_GPIO_H0_NR,
298 .label = "GPH0",
299 .to_irq = samsung_gpiolib_to_irq,
300 },
301 }, {
302 .base = (S5P_VA_GPIO + 0xC20),
303 .config = &gpio_cfg_eint,
304 .irq_base = IRQ_EINT(8),
305 .chip = {
306 .base = S5PC100_GPH1(0),
307 .ngpio = S5PC100_GPIO_H1_NR,
308 .label = "GPH1",
309 .to_irq = samsung_gpiolib_to_irq,
310 },
311 }, {
312 .base = (S5P_VA_GPIO + 0xC40),
313 .config = &gpio_cfg_eint,
314 .irq_base = IRQ_EINT(16),
315 .chip = {
316 .base = S5PC100_GPH2(0),
317 .ngpio = S5PC100_GPIO_H2_NR,
318 .label = "GPH2",
319 .to_irq = samsung_gpiolib_to_irq,
320 },
321 }, {
322 .base = (S5P_VA_GPIO + 0xC60),
323 .config = &gpio_cfg_eint,
324 .irq_base = IRQ_EINT(24),
325 .chip = {
326 .base = S5PC100_GPH3(0),
327 .ngpio = S5PC100_GPIO_H3_NR,
328 .label = "GPH3",
329 .to_irq = samsung_gpiolib_to_irq,
330 },
331 },
332};
333
334static __init int s5pc100_gpiolib_init(void)
335{
336 struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
337 int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
338 int gpioint_group = 0;
339 int i;
340
341 for (i = 0; i < nr_chips; i++, chip++) {
342 if (chip->config == NULL) {
343 chip->config = &gpio_cfg;
344 chip->group = gpioint_group++;
345 }
346 if (chip->base == NULL)
347 chip->base = S5PC100_BANK_BASE(i);
348 }
349
350 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
351 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
352
353 return 0;
354}
355core_initcall(s5pc100_gpiolib_init);
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 11f17907b4e..50907aca006 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -12,7 +12,7 @@ obj- :=
12 12
13# Core support for S5PV210 system 13# Core support for S5PV210 system
14 14
15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o 15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o 16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o 17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o 18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
deleted file mode 100644
index 1ba20a703e0..00000000000
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ /dev/null
@@ -1,288 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17#include <plat/gpio-core.h>
18#include <plat/gpio-cfg.h>
19#include <plat/gpio-cfg-helpers.h>
20#include <mach/map.h>
21
22static struct s3c_gpio_cfg gpio_cfg = {
23 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
24 .set_pull = s3c_gpio_setpull_updown,
25 .get_pull = s3c_gpio_getpull_updown,
26};
27
28static struct s3c_gpio_cfg gpio_cfg_noint = {
29 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
30 .set_pull = s3c_gpio_setpull_updown,
31 .get_pull = s3c_gpio_getpull_updown,
32};
33
34/* GPIO bank's base address given the index of the bank in the
35 * list of all gpio banks.
36 */
37#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
38
39/*
40 * Following are the gpio banks in v210.
41 *
42 * The 'config' member when left to NULL, is initialized to the default
43 * structure gpio_cfg in the init function below.
44 *
45 * The 'base' member is also initialized in the init function below.
46 * Note: The initialization of 'base' member of s3c_gpio_chip structure
47 * uses the above macro and depends on the banks being listed in order here.
48 */
49static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
50 {
51 .chip = {
52 .base = S5PV210_GPA0(0),
53 .ngpio = S5PV210_GPIO_A0_NR,
54 .label = "GPA0",
55 },
56 }, {
57 .chip = {
58 .base = S5PV210_GPA1(0),
59 .ngpio = S5PV210_GPIO_A1_NR,
60 .label = "GPA1",
61 },
62 }, {
63 .chip = {
64 .base = S5PV210_GPB(0),
65 .ngpio = S5PV210_GPIO_B_NR,
66 .label = "GPB",
67 },
68 }, {
69 .chip = {
70 .base = S5PV210_GPC0(0),
71 .ngpio = S5PV210_GPIO_C0_NR,
72 .label = "GPC0",
73 },
74 }, {
75 .chip = {
76 .base = S5PV210_GPC1(0),
77 .ngpio = S5PV210_GPIO_C1_NR,
78 .label = "GPC1",
79 },
80 }, {
81 .chip = {
82 .base = S5PV210_GPD0(0),
83 .ngpio = S5PV210_GPIO_D0_NR,
84 .label = "GPD0",
85 },
86 }, {
87 .chip = {
88 .base = S5PV210_GPD1(0),
89 .ngpio = S5PV210_GPIO_D1_NR,
90 .label = "GPD1",
91 },
92 }, {
93 .chip = {
94 .base = S5PV210_GPE0(0),
95 .ngpio = S5PV210_GPIO_E0_NR,
96 .label = "GPE0",
97 },
98 }, {
99 .chip = {
100 .base = S5PV210_GPE1(0),
101 .ngpio = S5PV210_GPIO_E1_NR,
102 .label = "GPE1",
103 },
104 }, {
105 .chip = {
106 .base = S5PV210_GPF0(0),
107 .ngpio = S5PV210_GPIO_F0_NR,
108 .label = "GPF0",
109 },
110 }, {
111 .chip = {
112 .base = S5PV210_GPF1(0),
113 .ngpio = S5PV210_GPIO_F1_NR,
114 .label = "GPF1",
115 },
116 }, {
117 .chip = {
118 .base = S5PV210_GPF2(0),
119 .ngpio = S5PV210_GPIO_F2_NR,
120 .label = "GPF2",
121 },
122 }, {
123 .chip = {
124 .base = S5PV210_GPF3(0),
125 .ngpio = S5PV210_GPIO_F3_NR,
126 .label = "GPF3",
127 },
128 }, {
129 .chip = {
130 .base = S5PV210_GPG0(0),
131 .ngpio = S5PV210_GPIO_G0_NR,
132 .label = "GPG0",
133 },
134 }, {
135 .chip = {
136 .base = S5PV210_GPG1(0),
137 .ngpio = S5PV210_GPIO_G1_NR,
138 .label = "GPG1",
139 },
140 }, {
141 .chip = {
142 .base = S5PV210_GPG2(0),
143 .ngpio = S5PV210_GPIO_G2_NR,
144 .label = "GPG2",
145 },
146 }, {
147 .chip = {
148 .base = S5PV210_GPG3(0),
149 .ngpio = S5PV210_GPIO_G3_NR,
150 .label = "GPG3",
151 },
152 }, {
153 .config = &gpio_cfg_noint,
154 .chip = {
155 .base = S5PV210_GPI(0),
156 .ngpio = S5PV210_GPIO_I_NR,
157 .label = "GPI",
158 },
159 }, {
160 .chip = {
161 .base = S5PV210_GPJ0(0),
162 .ngpio = S5PV210_GPIO_J0_NR,
163 .label = "GPJ0",
164 },
165 }, {
166 .chip = {
167 .base = S5PV210_GPJ1(0),
168 .ngpio = S5PV210_GPIO_J1_NR,
169 .label = "GPJ1",
170 },
171 }, {
172 .chip = {
173 .base = S5PV210_GPJ2(0),
174 .ngpio = S5PV210_GPIO_J2_NR,
175 .label = "GPJ2",
176 },
177 }, {
178 .chip = {
179 .base = S5PV210_GPJ3(0),
180 .ngpio = S5PV210_GPIO_J3_NR,
181 .label = "GPJ3",
182 },
183 }, {
184 .chip = {
185 .base = S5PV210_GPJ4(0),
186 .ngpio = S5PV210_GPIO_J4_NR,
187 .label = "GPJ4",
188 },
189 }, {
190 .config = &gpio_cfg_noint,
191 .chip = {
192 .base = S5PV210_MP01(0),
193 .ngpio = S5PV210_GPIO_MP01_NR,
194 .label = "MP01",
195 },
196 }, {
197 .config = &gpio_cfg_noint,
198 .chip = {
199 .base = S5PV210_MP02(0),
200 .ngpio = S5PV210_GPIO_MP02_NR,
201 .label = "MP02",
202 },
203 }, {
204 .config = &gpio_cfg_noint,
205 .chip = {
206 .base = S5PV210_MP03(0),
207 .ngpio = S5PV210_GPIO_MP03_NR,
208 .label = "MP03",
209 },
210 }, {
211 .config = &gpio_cfg_noint,
212 .chip = {
213 .base = S5PV210_MP04(0),
214 .ngpio = S5PV210_GPIO_MP04_NR,
215 .label = "MP04",
216 },
217 }, {
218 .config = &gpio_cfg_noint,
219 .chip = {
220 .base = S5PV210_MP05(0),
221 .ngpio = S5PV210_GPIO_MP05_NR,
222 .label = "MP05",
223 },
224 }, {
225 .base = (S5P_VA_GPIO + 0xC00),
226 .config = &gpio_cfg_noint,
227 .irq_base = IRQ_EINT(0),
228 .chip = {
229 .base = S5PV210_GPH0(0),
230 .ngpio = S5PV210_GPIO_H0_NR,
231 .label = "GPH0",
232 .to_irq = samsung_gpiolib_to_irq,
233 },
234 }, {
235 .base = (S5P_VA_GPIO + 0xC20),
236 .config = &gpio_cfg_noint,
237 .irq_base = IRQ_EINT(8),
238 .chip = {
239 .base = S5PV210_GPH1(0),
240 .ngpio = S5PV210_GPIO_H1_NR,
241 .label = "GPH1",
242 .to_irq = samsung_gpiolib_to_irq,
243 },
244 }, {
245 .base = (S5P_VA_GPIO + 0xC40),
246 .config = &gpio_cfg_noint,
247 .irq_base = IRQ_EINT(16),
248 .chip = {
249 .base = S5PV210_GPH2(0),
250 .ngpio = S5PV210_GPIO_H2_NR,
251 .label = "GPH2",
252 .to_irq = samsung_gpiolib_to_irq,
253 },
254 }, {
255 .base = (S5P_VA_GPIO + 0xC60),
256 .config = &gpio_cfg_noint,
257 .irq_base = IRQ_EINT(24),
258 .chip = {
259 .base = S5PV210_GPH3(0),
260 .ngpio = S5PV210_GPIO_H3_NR,
261 .label = "GPH3",
262 .to_irq = samsung_gpiolib_to_irq,
263 },
264 },
265};
266
267static __init int s5pv210_gpiolib_init(void)
268{
269 struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
270 int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
271 int gpioint_group = 0;
272 int i = 0;
273
274 for (i = 0; i < nr_chips; i++, chip++) {
275 if (chip->config == NULL) {
276 chip->config = &gpio_cfg;
277 chip->group = gpioint_group++;
278 }
279 if (chip->base == NULL)
280 chip->base = S5PV210_BANK_BASE(i);
281 }
282
283 samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
284 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
285
286 return 0;
287}
288core_initcall(s5pv210_gpiolib_init);
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index fab46fe9a71..8fd354aaf0a 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel, U300 machine. 2# Makefile for the linux kernel, U300 machine.
3# 3#
4 4
5obj-y := core.o clock.o timer.o gpio.o padmux.o 5obj-y := core.o clock.o timer.o padmux.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
deleted file mode 100644
index d92790140fe..00000000000
--- a/arch/arm/mach-u300/gpio.c
+++ /dev/null
@@ -1,700 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/gpio.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 GPIO module.
9 * This can driver either of the two basic GPIO cores
10 * available in the U300 platforms:
11 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
12 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
13 * Notice that you also have inline macros in <asm-arch/gpio.h>
14 * Author: Linus Walleij <linus.walleij@stericsson.com>
15 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
16 *
17 */
18#include <linux/module.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27
28/* Reference to GPIO block clock */
29static struct clk *clk;
30
31/* Memory resource */
32static struct resource *memres;
33static void __iomem *virtbase;
34static struct device *gpiodev;
35
36struct u300_gpio_port {
37 const char *name;
38 int irq;
39 int number;
40};
41
42
43static struct u300_gpio_port gpio_ports[] = {
44 {
45 .name = "gpio0",
46 .number = 0,
47 },
48 {
49 .name = "gpio1",
50 .number = 1,
51 },
52 {
53 .name = "gpio2",
54 .number = 2,
55 },
56#ifdef U300_COH901571_3
57 {
58 .name = "gpio3",
59 .number = 3,
60 },
61 {
62 .name = "gpio4",
63 .number = 4,
64 },
65#ifdef CONFIG_MACH_U300_BS335
66 {
67 .name = "gpio5",
68 .number = 5,
69 },
70 {
71 .name = "gpio6",
72 .number = 6,
73 },
74#endif
75#endif
76
77};
78
79
80#ifdef U300_COH901571_3
81
82/* Default input value */
83#define DEFAULT_OUTPUT_LOW 0
84#define DEFAULT_OUTPUT_HIGH 1
85
86/* GPIO Pull-Up status */
87#define DISABLE_PULL_UP 0
88#define ENABLE_PULL_UP 1
89
90#define GPIO_NOT_USED 0
91#define GPIO_IN 1
92#define GPIO_OUT 2
93
94struct u300_gpio_configuration_data {
95 unsigned char pin_usage;
96 unsigned char default_output_value;
97 unsigned char pull_up;
98};
99
100/* Initial configuration */
101const struct u300_gpio_configuration_data
102u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
103#ifdef CONFIG_MACH_U300_BS335
104 /* Port 0, pins 0-7 */
105 {
106 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
107 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
108 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
109 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
110 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
111 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
112 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
113 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
114 },
115 /* Port 1, pins 0-7 */
116 {
117 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
118 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
119 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
120 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
121 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
122 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
123 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
124 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
125 },
126 /* Port 2, pins 0-7 */
127 {
128 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
129 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
130 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
131 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
132 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
133 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
134 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
135 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
136 },
137 /* Port 3, pins 0-7 */
138 {
139 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
140 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
141 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
142 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
143 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
144 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
145 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
146 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
147 },
148 /* Port 4, pins 0-7 */
149 {
150 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
151 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
152 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
153 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
154 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
155 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
156 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
157 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
158 },
159 /* Port 5, pins 0-7 */
160 {
161 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
162 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
163 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
164 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
165 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
166 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
167 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
168 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
169 },
170 /* Port 6, pind 0-7 */
171 {
172 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
173 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
174 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
175 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
176 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
177 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
178 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
179 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
180 }
181#endif
182
183#ifdef CONFIG_MACH_U300_BS365
184 /* Port 0, pins 0-7 */
185 {
186 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
187 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
188 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
189 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
190 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
191 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
192 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
193 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
194 },
195 /* Port 1, pins 0-7 */
196 {
197 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
198 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
199 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
200 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
201 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
202 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
203 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
204 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
205 },
206 /* Port 2, pins 0-7 */
207 {
208 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
209 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
210 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
211 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
212 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
213 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
214 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
215 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
216 },
217 /* Port 3, pins 0-7 */
218 {
219 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
220 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
221 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
222 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
223 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
224 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
225 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
226 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
227 },
228 /* Port 4, pins 0-7 */
229 {
230 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
231 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
232 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
233 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
234 /* These 4 pins doesn't exist on DB3210 */
235 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
236 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
237 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
238 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
239 }
240#endif
241};
242#endif
243
244
245/* No users == we can power down GPIO */
246static int gpio_users;
247
248struct gpio_struct {
249 int (*callback)(void *);
250 void *data;
251 int users;
252};
253
254static struct gpio_struct gpio_pin[U300_GPIO_MAX];
255
256/*
257 * Let drivers register callback in order to get notified when there is
258 * an interrupt on the gpio pin
259 */
260int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data)
261{
262 if (gpio_pin[gpio].callback)
263 dev_warn(gpiodev, "%s: WARNING: callback already "
264 "registered for gpio pin#%d\n", __func__, gpio);
265 gpio_pin[gpio].callback = func;
266 gpio_pin[gpio].data = data;
267
268 return 0;
269}
270EXPORT_SYMBOL(gpio_register_callback);
271
272int gpio_unregister_callback(unsigned gpio)
273{
274 if (!gpio_pin[gpio].callback)
275 dev_warn(gpiodev, "%s: WARNING: callback already "
276 "unregistered for gpio pin#%d\n", __func__, gpio);
277 gpio_pin[gpio].callback = NULL;
278 gpio_pin[gpio].data = NULL;
279
280 return 0;
281}
282EXPORT_SYMBOL(gpio_unregister_callback);
283
284/* Non-zero means valid */
285int gpio_is_valid(int number)
286{
287 if (number >= 0 &&
288 number < (U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT))
289 return 1;
290 return 0;
291}
292EXPORT_SYMBOL(gpio_is_valid);
293
294int gpio_request(unsigned gpio, const char *label)
295{
296 if (gpio_pin[gpio].users)
297 return -EINVAL;
298 else
299 gpio_pin[gpio].users++;
300
301 gpio_users++;
302
303 return 0;
304}
305EXPORT_SYMBOL(gpio_request);
306
307void gpio_free(unsigned gpio)
308{
309 gpio_users--;
310 gpio_pin[gpio].users--;
311 if (unlikely(gpio_pin[gpio].users < 0)) {
312 dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
313 gpio);
314 gpio_pin[gpio].users = 0;
315 }
316
317 return;
318}
319EXPORT_SYMBOL(gpio_free);
320
321/* This returns zero or nonzero */
322int gpio_get_value(unsigned gpio)
323{
324 return readl(virtbase + U300_GPIO_PXPDIR +
325 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07));
326}
327EXPORT_SYMBOL(gpio_get_value);
328
329/*
330 * We hope that the compiler will optimize away the unused branch
331 * in case "value" is a constant
332 */
333void gpio_set_value(unsigned gpio, int value)
334{
335 u32 val;
336 unsigned long flags;
337
338 local_irq_save(flags);
339 if (value) {
340 /* set */
341 val = readl(virtbase + U300_GPIO_PXPDOR +
342 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
343 & (1 << (gpio & 0x07));
344 writel(val | (1 << (gpio & 0x07)), virtbase +
345 U300_GPIO_PXPDOR +
346 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
347 } else {
348 /* clear */
349 val = readl(virtbase + U300_GPIO_PXPDOR +
350 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
351 & (1 << (gpio & 0x07));
352 writel(val & ~(1 << (gpio & 0x07)), virtbase +
353 U300_GPIO_PXPDOR +
354 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
355 }
356 local_irq_restore(flags);
357}
358EXPORT_SYMBOL(gpio_set_value);
359
360int gpio_direction_input(unsigned gpio)
361{
362 unsigned long flags;
363 u32 val;
364
365 if (gpio > U300_GPIO_MAX)
366 return -EINVAL;
367
368 local_irq_save(flags);
369 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
370 U300_GPIO_PORTX_SPACING);
371 /* Mask out this pin*/
372 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
373 /* This is not needed since it sets the bits to zero.*/
374 /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */
375 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
376 U300_GPIO_PORTX_SPACING);
377 local_irq_restore(flags);
378 return 0;
379}
380EXPORT_SYMBOL(gpio_direction_input);
381
382int gpio_direction_output(unsigned gpio, int value)
383{
384 unsigned long flags;
385 u32 val;
386
387 if (gpio > U300_GPIO_MAX)
388 return -EINVAL;
389
390 local_irq_save(flags);
391 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
392 U300_GPIO_PORTX_SPACING);
393 /* Mask out this pin */
394 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
395 /*
396 * FIXME: configure for push/pull, open drain or open source per pin
397 * in setup. The current driver will only support push/pull.
398 */
399 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
400 << ((gpio & 0x07) << 1));
401 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
402 U300_GPIO_PORTX_SPACING);
403 gpio_set_value(gpio, value);
404 local_irq_restore(flags);
405 return 0;
406}
407EXPORT_SYMBOL(gpio_direction_output);
408
409/*
410 * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
411 */
412void enable_irq_on_gpio_pin(unsigned gpio, int edge)
413{
414 u32 val;
415 unsigned long flags;
416 local_irq_save(flags);
417
418 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
419 U300_GPIO_PORTX_SPACING);
420 val |= (1 << (gpio & 0x07));
421 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
422 U300_GPIO_PORTX_SPACING);
423 val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
424 U300_GPIO_PORTX_SPACING);
425 if (edge)
426 val |= (1 << (gpio & 0x07));
427 else
428 val &= ~(1 << (gpio & 0x07));
429 writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
430 U300_GPIO_PORTX_SPACING);
431 local_irq_restore(flags);
432}
433EXPORT_SYMBOL(enable_irq_on_gpio_pin);
434
435void disable_irq_on_gpio_pin(unsigned gpio)
436{
437 u32 val;
438 unsigned long flags;
439
440 local_irq_save(flags);
441 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
442 U300_GPIO_PORTX_SPACING);
443 val &= ~(1 << (gpio & 0x07));
444 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
445 U300_GPIO_PORTX_SPACING);
446 local_irq_restore(flags);
447}
448EXPORT_SYMBOL(disable_irq_on_gpio_pin);
449
450/* Enable (value == 0) or disable (value == 1) internal pullup */
451void gpio_pullup(unsigned gpio, int value)
452{
453 u32 val;
454 unsigned long flags;
455
456 local_irq_save(flags);
457 if (value) {
458 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
459 U300_GPIO_PORTX_SPACING);
460 writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
461 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
462 } else {
463 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
464 U300_GPIO_PORTX_SPACING);
465 writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
466 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
467 }
468 local_irq_restore(flags);
469}
470EXPORT_SYMBOL(gpio_pullup);
471
472static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
473{
474 struct u300_gpio_port *port = dev_id;
475 u32 val;
476 int pin;
477
478 /* Read event register */
479 val = readl(virtbase + U300_GPIO_PXIEV + port->number *
480 U300_GPIO_PORTX_SPACING);
481 /* Mask with enable register */
482 val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
483 U300_GPIO_PORTX_SPACING);
484 /* Mask relevant bits */
485 val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK;
486 /* ACK IRQ (clear event) */
487 writel(val, virtbase + U300_GPIO_PXIEV + port->number *
488 U300_GPIO_PORTX_SPACING);
489 /* Print message */
490 while (val != 0) {
491 unsigned gpio;
492
493 pin = __ffs(val);
494 /* mask off this pin */
495 val &= ~(1 << pin);
496 gpio = (port->number << 3) + pin;
497
498 if (gpio_pin[gpio].callback)
499 (void)gpio_pin[gpio].callback(gpio_pin[gpio].data);
500 else
501 dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n",
502 gpio);
503 }
504 return IRQ_HANDLED;
505}
506
507static void gpio_set_initial_values(void)
508{
509#ifdef U300_COH901571_3
510 int i, j;
511 unsigned long flags;
512 u32 val;
513
514 /* Write default values to all pins */
515 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
516 val = 0;
517 for (j = 0; j < 8; j++)
518 val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j;
519 local_irq_save(flags);
520 writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING);
521 local_irq_restore(flags);
522 }
523
524 /*
525 * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
526 * to output and 'GPIO_IN' to input for each port. And initialize
527 * default value on outputs.
528 */
529 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
530 for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) {
531 local_irq_save(flags);
532 val = readl(virtbase + U300_GPIO_PXPCR +
533 i * U300_GPIO_PORTX_SPACING);
534 /* Mask out this pin */
535 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1));
536
537 if (u300_gpio_config[i][j].pin_usage != GPIO_IN)
538 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1));
539 writel(val, virtbase + U300_GPIO_PXPCR +
540 i * U300_GPIO_PORTX_SPACING);
541 local_irq_restore(flags);
542 }
543 }
544
545 /* Enable or disable the internal pull-ups in the GPIO ASIC block */
546 for (i = 0; i < U300_GPIO_MAX; i++) {
547 val = 0;
548 for (j = 0; j < 8; j++)
549 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j);
550 local_irq_save(flags);
551 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
552 local_irq_restore(flags);
553 }
554#endif
555}
556
557static int __init gpio_probe(struct platform_device *pdev)
558{
559 u32 val;
560 int err = 0;
561 int i;
562 int num_irqs;
563
564 gpiodev = &pdev->dev;
565 memset(gpio_pin, 0, sizeof(gpio_pin));
566
567 /* Get GPIO clock */
568 clk = clk_get(&pdev->dev, NULL);
569 if (IS_ERR(clk)) {
570 err = PTR_ERR(clk);
571 dev_err(gpiodev, "could not get GPIO clock\n");
572 goto err_no_clk;
573 }
574 err = clk_enable(clk);
575 if (err) {
576 dev_err(gpiodev, "could not enable GPIO clock\n");
577 goto err_no_clk_enable;
578 }
579
580 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
581 if (!memres)
582 goto err_no_resource;
583
584 if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller")
585 == NULL) {
586 err = -ENODEV;
587 goto err_no_ioregion;
588 }
589
590 virtbase = ioremap(memres->start, resource_size(memres));
591 if (!virtbase) {
592 err = -ENOMEM;
593 goto err_no_ioremap;
594 }
595 dev_info(gpiodev, "remapped 0x%08x to %p\n",
596 memres->start, virtbase);
597
598#ifdef U300_COH901335
599 dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n");
600 /* Turn on the GPIO block */
601 writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR);
602#endif
603
604#ifdef U300_COH901571_3
605 dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n");
606 val = readl(virtbase + U300_GPIO_CR);
607 dev_info(gpiodev, "COH901571/3 block version: %d, " \
608 "number of cores: %d\n",
609 ((val & 0x0000FE00) >> 9),
610 ((val & 0x000001FC) >> 2));
611 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR);
612#endif
613
614 gpio_set_initial_values();
615
616 for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) {
617
618 gpio_ports[num_irqs].irq =
619 platform_get_irq_byname(pdev,
620 gpio_ports[num_irqs].name);
621
622 err = request_irq(gpio_ports[num_irqs].irq,
623 gpio_irq_handler, IRQF_DISABLED,
624 gpio_ports[num_irqs].name,
625 &gpio_ports[num_irqs]);
626 if (err) {
627 dev_err(gpiodev, "cannot allocate IRQ for %s!\n",
628 gpio_ports[num_irqs].name);
629 goto err_no_irq;
630 }
631 /* Turns off PortX_irq_force */
632 writel(0x0, virtbase + U300_GPIO_PXIFR +
633 num_irqs * U300_GPIO_PORTX_SPACING);
634 }
635
636 return 0;
637
638 err_no_irq:
639 for (i = 0; i < num_irqs; i++)
640 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
641 iounmap(virtbase);
642 err_no_ioremap:
643 release_mem_region(memres->start, memres->end - memres->start);
644 err_no_ioregion:
645 err_no_resource:
646 clk_disable(clk);
647 err_no_clk_enable:
648 clk_put(clk);
649 err_no_clk:
650 dev_info(gpiodev, "module ERROR:%d\n", err);
651 return err;
652}
653
654static int __exit gpio_remove(struct platform_device *pdev)
655{
656 int i;
657
658 /* Turn off the GPIO block */
659 writel(0x00000000U, virtbase + U300_GPIO_CR);
660 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
661 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
662 iounmap(virtbase);
663 release_mem_region(memres->start, memres->end - memres->start);
664 clk_disable(clk);
665 clk_put(clk);
666 return 0;
667}
668
669static struct platform_driver gpio_driver = {
670 .driver = {
671 .name = "u300-gpio",
672 },
673 .remove = __exit_p(gpio_remove),
674};
675
676
677static int __init u300_gpio_init(void)
678{
679 return platform_driver_probe(&gpio_driver, gpio_probe);
680}
681
682static void __exit u300_gpio_exit(void)
683{
684 platform_driver_unregister(&gpio_driver);
685}
686
687arch_initcall(u300_gpio_init);
688module_exit(u300_gpio_exit);
689
690MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
691
692#ifdef U300_COH901571_3
693MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
694#endif
695
696#ifdef U300_COH901335
697MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
698#endif
699
700MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 54429d01595..f8b9392ee34 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -5,7 +5,6 @@ config UX500_SOC_COMMON
5 default y 5 default y
6 select ARM_GIC 6 select ARM_GIC
7 select HAS_MTU 7 select HAS_MTU
8 select NOMADIK_GPIO
9 select ARM_ERRATA_753970 8 select ARM_ERRATA_753970
10 9
11menu "Ux500 SoC" 10menu "Ux500 SoC"
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index 18296ee6880..ce659015535 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -21,9 +21,4 @@ config HAS_MTU
21 to multiple interrupt generating programmable 21 to multiple interrupt generating programmable
22 32-bit free running decrementing counters. 22 32-bit free running decrementing counters.
23 23
24config NOMADIK_GPIO
25 bool
26 help
27 Support for the Nomadik GPIO controller.
28
29endif 24endif
diff --git a/arch/arm/plat-nomadik/Makefile b/arch/arm/plat-nomadik/Makefile
index c33547361bd..37c7cdd0f8f 100644
--- a/arch/arm/plat-nomadik/Makefile
+++ b/arch/arm/plat-nomadik/Makefile
@@ -3,4 +3,3 @@
3# Licensed under GPLv2 3# Licensed under GPLv2
4 4
5obj-$(CONFIG_HAS_MTU) += timer.o 5obj-$(CONFIG_HAS_MTU) += timer.o
6obj-$(CONFIG_NOMADIK_GPIO) += gpio.o
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
deleted file mode 100644
index 307b8131aa8..00000000000
--- a/arch/arm/plat-nomadik/gpio.c
+++ /dev/null
@@ -1,1020 +0,0 @@
1/*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/device.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/gpio.h>
21#include <linux/spinlock.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/slab.h>
25
26#include <asm/mach/irq.h>
27
28#include <plat/pincfg.h>
29#include <mach/hardware.h>
30#include <mach/gpio.h>
31
32/*
33 * The GPIO module in the Nomadik family of Systems-on-Chip is an
34 * AMBA device, managing 32 pins and alternate functions. The logic block
35 * is currently used in the Nomadik and ux500.
36 *
37 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
38 */
39
40#define NMK_GPIO_PER_CHIP 32
41
42struct nmk_gpio_chip {
43 struct gpio_chip chip;
44 void __iomem *addr;
45 struct clk *clk;
46 unsigned int bank;
47 unsigned int parent_irq;
48 int secondary_parent_irq;
49 u32 (*get_secondary_status)(unsigned int bank);
50 void (*set_ioforce)(bool enable);
51 spinlock_t lock;
52 /* Keep track of configured edges */
53 u32 edge_rising;
54 u32 edge_falling;
55 u32 real_wake;
56 u32 rwimsc;
57 u32 fwimsc;
58 u32 slpm;
59 u32 enabled;
60};
61
62static struct nmk_gpio_chip *
63nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
64
65static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
66
67#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
68
69static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
70 unsigned offset, int gpio_mode)
71{
72 u32 bit = 1 << offset;
73 u32 afunc, bfunc;
74
75 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
76 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
77 if (gpio_mode & NMK_GPIO_ALT_A)
78 afunc |= bit;
79 if (gpio_mode & NMK_GPIO_ALT_B)
80 bfunc |= bit;
81 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
82 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
83}
84
85static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
86 unsigned offset, enum nmk_gpio_slpm mode)
87{
88 u32 bit = 1 << offset;
89 u32 slpm;
90
91 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
92 if (mode == NMK_GPIO_SLPM_NOCHANGE)
93 slpm |= bit;
94 else
95 slpm &= ~bit;
96 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
97}
98
99static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
100 unsigned offset, enum nmk_gpio_pull pull)
101{
102 u32 bit = 1 << offset;
103 u32 pdis;
104
105 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
106 if (pull == NMK_GPIO_PULL_NONE)
107 pdis |= bit;
108 else
109 pdis &= ~bit;
110 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
111
112 if (pull == NMK_GPIO_PULL_UP)
113 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
114 else if (pull == NMK_GPIO_PULL_DOWN)
115 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
116}
117
118static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
119 unsigned offset)
120{
121 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
122}
123
124static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
125 unsigned offset, int val)
126{
127 if (val)
128 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
129 else
130 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
131}
132
133static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
134 unsigned offset, int val)
135{
136 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
137 __nmk_gpio_set_output(nmk_chip, offset, val);
138}
139
140static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
141 unsigned offset, int gpio_mode,
142 bool glitch)
143{
144 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
145 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
146
147 if (glitch && nmk_chip->set_ioforce) {
148 u32 bit = BIT(offset);
149
150 /* Prevent spurious wakeups */
151 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
152 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
153
154 nmk_chip->set_ioforce(true);
155 }
156
157 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
158
159 if (glitch && nmk_chip->set_ioforce) {
160 nmk_chip->set_ioforce(false);
161
162 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
163 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
164 }
165}
166
167static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
168 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
169{
170 static const char *afnames[] = {
171 [NMK_GPIO_ALT_GPIO] = "GPIO",
172 [NMK_GPIO_ALT_A] = "A",
173 [NMK_GPIO_ALT_B] = "B",
174 [NMK_GPIO_ALT_C] = "C"
175 };
176 static const char *pullnames[] = {
177 [NMK_GPIO_PULL_NONE] = "none",
178 [NMK_GPIO_PULL_UP] = "up",
179 [NMK_GPIO_PULL_DOWN] = "down",
180 [3] /* illegal */ = "??"
181 };
182 static const char *slpmnames[] = {
183 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
184 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
185 };
186
187 int pin = PIN_NUM(cfg);
188 int pull = PIN_PULL(cfg);
189 int af = PIN_ALT(cfg);
190 int slpm = PIN_SLPM(cfg);
191 int output = PIN_DIR(cfg);
192 int val = PIN_VAL(cfg);
193 bool glitch = af == NMK_GPIO_ALT_C;
194
195 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
196 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
197 output ? "output " : "input",
198 output ? (val ? "high" : "low") : "");
199
200 if (sleep) {
201 int slpm_pull = PIN_SLPM_PULL(cfg);
202 int slpm_output = PIN_SLPM_DIR(cfg);
203 int slpm_val = PIN_SLPM_VAL(cfg);
204
205 af = NMK_GPIO_ALT_GPIO;
206
207 /*
208 * The SLPM_* values are normal values + 1 to allow zero to
209 * mean "same as normal".
210 */
211 if (slpm_pull)
212 pull = slpm_pull - 1;
213 if (slpm_output)
214 output = slpm_output - 1;
215 if (slpm_val)
216 val = slpm_val - 1;
217
218 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
219 pin,
220 slpm_pull ? pullnames[pull] : "same",
221 slpm_output ? (output ? "output" : "input") : "same",
222 slpm_val ? (val ? "high" : "low") : "same");
223 }
224
225 if (output)
226 __nmk_gpio_make_output(nmk_chip, offset, val);
227 else {
228 __nmk_gpio_make_input(nmk_chip, offset);
229 __nmk_gpio_set_pull(nmk_chip, offset, pull);
230 }
231
232 /*
233 * If we've backed up the SLPM registers (glitch workaround), modify
234 * the backups since they will be restored.
235 */
236 if (slpmregs) {
237 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
238 slpmregs[nmk_chip->bank] |= BIT(offset);
239 else
240 slpmregs[nmk_chip->bank] &= ~BIT(offset);
241 } else
242 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
243
244 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
245}
246
247/*
248 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
249 * - Save SLPM registers
250 * - Set SLPM=0 for the IOs you want to switch and others to 1
251 * - Configure the GPIO registers for the IOs that are being switched
252 * - Set IOFORCE=1
253 * - Modify the AFLSA/B registers for the IOs that are being switched
254 * - Set IOFORCE=0
255 * - Restore SLPM registers
256 * - Any spurious wake up event during switch sequence to be ignored and
257 * cleared
258 */
259static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
260{
261 int i;
262
263 for (i = 0; i < NUM_BANKS; i++) {
264 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
265 unsigned int temp = slpm[i];
266
267 if (!chip)
268 break;
269
270 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
271 writel(temp, chip->addr + NMK_GPIO_SLPC);
272 }
273}
274
275static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
276{
277 int i;
278
279 for (i = 0; i < NUM_BANKS; i++) {
280 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
281
282 if (!chip)
283 break;
284
285 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
286 }
287}
288
289static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
290{
291 static unsigned int slpm[NUM_BANKS];
292 unsigned long flags;
293 bool glitch = false;
294 int ret = 0;
295 int i;
296
297 for (i = 0; i < num; i++) {
298 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
299 glitch = true;
300 break;
301 }
302 }
303
304 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
305
306 if (glitch) {
307 memset(slpm, 0xff, sizeof(slpm));
308
309 for (i = 0; i < num; i++) {
310 int pin = PIN_NUM(cfgs[i]);
311 int offset = pin % NMK_GPIO_PER_CHIP;
312
313 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
314 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
315 }
316
317 nmk_gpio_glitch_slpm_init(slpm);
318 }
319
320 for (i = 0; i < num; i++) {
321 struct nmk_gpio_chip *nmk_chip;
322 int pin = PIN_NUM(cfgs[i]);
323
324 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
325 if (!nmk_chip) {
326 ret = -EINVAL;
327 break;
328 }
329
330 spin_lock(&nmk_chip->lock);
331 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
332 cfgs[i], sleep, glitch ? slpm : NULL);
333 spin_unlock(&nmk_chip->lock);
334 }
335
336 if (glitch)
337 nmk_gpio_glitch_slpm_restore(slpm);
338
339 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
340
341 return ret;
342}
343
344/**
345 * nmk_config_pin - configure a pin's mux attributes
346 * @cfg: pin confguration
347 *
348 * Configures a pin's mode (alternate function or GPIO), its pull up status,
349 * and its sleep mode based on the specified configuration. The @cfg is
350 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
351 * are constructed using, and can be further enhanced with, the macros in
352 * plat/pincfg.h.
353 *
354 * If a pin's mode is set to GPIO, it is configured as an input to avoid
355 * side-effects. The gpio can be manipulated later using standard GPIO API
356 * calls.
357 */
358int nmk_config_pin(pin_cfg_t cfg, bool sleep)
359{
360 return __nmk_config_pins(&cfg, 1, sleep);
361}
362EXPORT_SYMBOL(nmk_config_pin);
363
364/**
365 * nmk_config_pins - configure several pins at once
366 * @cfgs: array of pin configurations
367 * @num: number of elments in the array
368 *
369 * Configures several pins using nmk_config_pin(). Refer to that function for
370 * further information.
371 */
372int nmk_config_pins(pin_cfg_t *cfgs, int num)
373{
374 return __nmk_config_pins(cfgs, num, false);
375}
376EXPORT_SYMBOL(nmk_config_pins);
377
378int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
379{
380 return __nmk_config_pins(cfgs, num, true);
381}
382EXPORT_SYMBOL(nmk_config_pins_sleep);
383
384/**
385 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
386 * @gpio: pin number
387 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
388 *
389 * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is
390 * changed to an input (with pullup/down enabled) in sleep and deep sleep. If
391 * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
392 * configured even when in sleep and deep sleep.
393 *
394 * On DB8500v2 onwards, this setting loses the previous meaning and instead
395 * indicates if wakeup detection is enabled on the pin. Note that
396 * enable_irq_wake() will automatically enable wakeup detection.
397 */
398int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
399{
400 struct nmk_gpio_chip *nmk_chip;
401 unsigned long flags;
402
403 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
404 if (!nmk_chip)
405 return -EINVAL;
406
407 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
408 spin_lock(&nmk_chip->lock);
409
410 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
411
412 spin_unlock(&nmk_chip->lock);
413 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
414
415 return 0;
416}
417
418/**
419 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
420 * @gpio: pin number
421 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
422 *
423 * Enables/disables pull up/down on a specified pin. This only takes effect if
424 * the pin is configured as an input (either explicitly or by the alternate
425 * function).
426 *
427 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
428 * configured as an input. Otherwise, due to the way the controller registers
429 * work, this function will change the value output on the pin.
430 */
431int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
432{
433 struct nmk_gpio_chip *nmk_chip;
434 unsigned long flags;
435
436 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
437 if (!nmk_chip)
438 return -EINVAL;
439
440 spin_lock_irqsave(&nmk_chip->lock, flags);
441 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
442 spin_unlock_irqrestore(&nmk_chip->lock, flags);
443
444 return 0;
445}
446
447/* Mode functions */
448/**
449 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
450 * @gpio: pin number
451 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
452 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
453 *
454 * Sets the mode of the specified pin to one of the alternate functions or
455 * plain GPIO.
456 */
457int nmk_gpio_set_mode(int gpio, int gpio_mode)
458{
459 struct nmk_gpio_chip *nmk_chip;
460 unsigned long flags;
461
462 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
463 if (!nmk_chip)
464 return -EINVAL;
465
466 spin_lock_irqsave(&nmk_chip->lock, flags);
467 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
468 spin_unlock_irqrestore(&nmk_chip->lock, flags);
469
470 return 0;
471}
472EXPORT_SYMBOL(nmk_gpio_set_mode);
473
474int nmk_gpio_get_mode(int gpio)
475{
476 struct nmk_gpio_chip *nmk_chip;
477 u32 afunc, bfunc, bit;
478
479 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
480 if (!nmk_chip)
481 return -EINVAL;
482
483 bit = 1 << (gpio - nmk_chip->chip.base);
484
485 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
486 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
487
488 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
489}
490EXPORT_SYMBOL(nmk_gpio_get_mode);
491
492
493/* IRQ functions */
494static inline int nmk_gpio_get_bitmask(int gpio)
495{
496 return 1 << (gpio % 32);
497}
498
499static void nmk_gpio_irq_ack(struct irq_data *d)
500{
501 int gpio;
502 struct nmk_gpio_chip *nmk_chip;
503
504 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
505 nmk_chip = irq_data_get_irq_chip_data(d);
506 if (!nmk_chip)
507 return;
508 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
509}
510
511enum nmk_gpio_irq_type {
512 NORMAL,
513 WAKE,
514};
515
516static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
517 int gpio, enum nmk_gpio_irq_type which,
518 bool enable)
519{
520 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
521 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
522 u32 bitmask = nmk_gpio_get_bitmask(gpio);
523 u32 reg;
524
525 /* we must individually set/clear the two edges */
526 if (nmk_chip->edge_rising & bitmask) {
527 reg = readl(nmk_chip->addr + rimsc);
528 if (enable)
529 reg |= bitmask;
530 else
531 reg &= ~bitmask;
532 writel(reg, nmk_chip->addr + rimsc);
533 }
534 if (nmk_chip->edge_falling & bitmask) {
535 reg = readl(nmk_chip->addr + fimsc);
536 if (enable)
537 reg |= bitmask;
538 else
539 reg &= ~bitmask;
540 writel(reg, nmk_chip->addr + fimsc);
541 }
542}
543
544static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
545 int gpio, bool on)
546{
547 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
548}
549
550static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
551{
552 int gpio;
553 struct nmk_gpio_chip *nmk_chip;
554 unsigned long flags;
555 u32 bitmask;
556
557 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
558 nmk_chip = irq_data_get_irq_chip_data(d);
559 bitmask = nmk_gpio_get_bitmask(gpio);
560 if (!nmk_chip)
561 return -EINVAL;
562
563 if (enable)
564 nmk_chip->enabled |= bitmask;
565 else
566 nmk_chip->enabled &= ~bitmask;
567
568 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
569 spin_lock(&nmk_chip->lock);
570
571 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
572
573 if (!(nmk_chip->real_wake & bitmask))
574 __nmk_gpio_set_wake(nmk_chip, gpio, enable);
575
576 spin_unlock(&nmk_chip->lock);
577 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
578
579 return 0;
580}
581
582static void nmk_gpio_irq_mask(struct irq_data *d)
583{
584 nmk_gpio_irq_maskunmask(d, false);
585}
586
587static void nmk_gpio_irq_unmask(struct irq_data *d)
588{
589 nmk_gpio_irq_maskunmask(d, true);
590}
591
592static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
593{
594 struct nmk_gpio_chip *nmk_chip;
595 unsigned long flags;
596 u32 bitmask;
597 int gpio;
598
599 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
600 nmk_chip = irq_data_get_irq_chip_data(d);
601 if (!nmk_chip)
602 return -EINVAL;
603 bitmask = nmk_gpio_get_bitmask(gpio);
604
605 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
606 spin_lock(&nmk_chip->lock);
607
608 if (!(nmk_chip->enabled & bitmask))
609 __nmk_gpio_set_wake(nmk_chip, gpio, on);
610
611 if (on)
612 nmk_chip->real_wake |= bitmask;
613 else
614 nmk_chip->real_wake &= ~bitmask;
615
616 spin_unlock(&nmk_chip->lock);
617 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
618
619 return 0;
620}
621
622static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
623{
624 bool enabled, wake = irqd_is_wakeup_set(d);
625 int gpio;
626 struct nmk_gpio_chip *nmk_chip;
627 unsigned long flags;
628 u32 bitmask;
629
630 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
631 nmk_chip = irq_data_get_irq_chip_data(d);
632 bitmask = nmk_gpio_get_bitmask(gpio);
633 if (!nmk_chip)
634 return -EINVAL;
635
636 if (type & IRQ_TYPE_LEVEL_HIGH)
637 return -EINVAL;
638 if (type & IRQ_TYPE_LEVEL_LOW)
639 return -EINVAL;
640
641 enabled = nmk_chip->enabled & bitmask;
642
643 spin_lock_irqsave(&nmk_chip->lock, flags);
644
645 if (enabled)
646 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
647
648 if (enabled || wake)
649 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
650
651 nmk_chip->edge_rising &= ~bitmask;
652 if (type & IRQ_TYPE_EDGE_RISING)
653 nmk_chip->edge_rising |= bitmask;
654
655 nmk_chip->edge_falling &= ~bitmask;
656 if (type & IRQ_TYPE_EDGE_FALLING)
657 nmk_chip->edge_falling |= bitmask;
658
659 if (enabled)
660 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
661
662 if (enabled || wake)
663 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
664
665 spin_unlock_irqrestore(&nmk_chip->lock, flags);
666
667 return 0;
668}
669
670static struct irq_chip nmk_gpio_irq_chip = {
671 .name = "Nomadik-GPIO",
672 .irq_ack = nmk_gpio_irq_ack,
673 .irq_mask = nmk_gpio_irq_mask,
674 .irq_unmask = nmk_gpio_irq_unmask,
675 .irq_set_type = nmk_gpio_irq_set_type,
676 .irq_set_wake = nmk_gpio_irq_set_wake,
677};
678
679static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
680 u32 status)
681{
682 struct nmk_gpio_chip *nmk_chip;
683 struct irq_chip *host_chip = irq_get_chip(irq);
684 unsigned int first_irq;
685
686 chained_irq_enter(host_chip, desc);
687
688 nmk_chip = irq_get_handler_data(irq);
689 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
690 while (status) {
691 int bit = __ffs(status);
692
693 generic_handle_irq(first_irq + bit);
694 status &= ~BIT(bit);
695 }
696
697 chained_irq_exit(host_chip, desc);
698}
699
700static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
701{
702 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
703 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
704
705 __nmk_gpio_irq_handler(irq, desc, status);
706}
707
708static void nmk_gpio_secondary_irq_handler(unsigned int irq,
709 struct irq_desc *desc)
710{
711 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
712 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
713
714 __nmk_gpio_irq_handler(irq, desc, status);
715}
716
717static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
718{
719 unsigned int first_irq;
720 int i;
721
722 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
723 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
724 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
725 handle_edge_irq);
726 set_irq_flags(i, IRQF_VALID);
727 irq_set_chip_data(i, nmk_chip);
728 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
729 }
730
731 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
732 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
733
734 if (nmk_chip->secondary_parent_irq >= 0) {
735 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
736 nmk_gpio_secondary_irq_handler);
737 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
738 }
739
740 return 0;
741}
742
743/* I/O Functions */
744static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
745{
746 struct nmk_gpio_chip *nmk_chip =
747 container_of(chip, struct nmk_gpio_chip, chip);
748
749 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
750 return 0;
751}
752
753static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
754{
755 struct nmk_gpio_chip *nmk_chip =
756 container_of(chip, struct nmk_gpio_chip, chip);
757 u32 bit = 1 << offset;
758
759 return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
760}
761
762static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
763 int val)
764{
765 struct nmk_gpio_chip *nmk_chip =
766 container_of(chip, struct nmk_gpio_chip, chip);
767
768 __nmk_gpio_set_output(nmk_chip, offset, val);
769}
770
771static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
772 int val)
773{
774 struct nmk_gpio_chip *nmk_chip =
775 container_of(chip, struct nmk_gpio_chip, chip);
776
777 __nmk_gpio_make_output(nmk_chip, offset, val);
778
779 return 0;
780}
781
782static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
783{
784 struct nmk_gpio_chip *nmk_chip =
785 container_of(chip, struct nmk_gpio_chip, chip);
786
787 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
788}
789
790#ifdef CONFIG_DEBUG_FS
791
792#include <linux/seq_file.h>
793
794static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
795{
796 int mode;
797 unsigned i;
798 unsigned gpio = chip->base;
799 int is_out;
800 struct nmk_gpio_chip *nmk_chip =
801 container_of(chip, struct nmk_gpio_chip, chip);
802 const char *modes[] = {
803 [NMK_GPIO_ALT_GPIO] = "gpio",
804 [NMK_GPIO_ALT_A] = "altA",
805 [NMK_GPIO_ALT_B] = "altB",
806 [NMK_GPIO_ALT_C] = "altC",
807 };
808
809 for (i = 0; i < chip->ngpio; i++, gpio++) {
810 const char *label = gpiochip_is_requested(chip, i);
811 bool pull;
812 u32 bit = 1 << i;
813
814 if (!label)
815 continue;
816
817 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
818 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
819 mode = nmk_gpio_get_mode(gpio);
820 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
821 gpio, label,
822 is_out ? "out" : "in ",
823 chip->get
824 ? (chip->get(chip, i) ? "hi" : "lo")
825 : "? ",
826 (mode < 0) ? "unknown" : modes[mode],
827 pull ? "pull" : "none");
828 seq_printf(s, "\n");
829 }
830}
831
832#else
833#define nmk_gpio_dbg_show NULL
834#endif
835
836/* This structure is replicated for each GPIO block allocated at probe time */
837static struct gpio_chip nmk_gpio_template = {
838 .direction_input = nmk_gpio_make_input,
839 .get = nmk_gpio_get_input,
840 .direction_output = nmk_gpio_make_output,
841 .set = nmk_gpio_set_output,
842 .to_irq = nmk_gpio_to_irq,
843 .dbg_show = nmk_gpio_dbg_show,
844 .can_sleep = 0,
845};
846
847/*
848 * Called from the suspend/resume path to only keep the real wakeup interrupts
849 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
850 * and not the rest of the interrupts which we needed to have as wakeups for
851 * cpuidle.
852 *
853 * PM ops are not used since this needs to be done at the end, after all the
854 * other drivers are done with their suspend callbacks.
855 */
856void nmk_gpio_wakeups_suspend(void)
857{
858 int i;
859
860 for (i = 0; i < NUM_BANKS; i++) {
861 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
862
863 if (!chip)
864 break;
865
866 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
867 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
868
869 writel(chip->rwimsc & chip->real_wake,
870 chip->addr + NMK_GPIO_RWIMSC);
871 writel(chip->fwimsc & chip->real_wake,
872 chip->addr + NMK_GPIO_FWIMSC);
873
874 if (cpu_is_u8500v2()) {
875 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
876
877 /* 0 -> wakeup enable */
878 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
879 }
880 }
881}
882
883void nmk_gpio_wakeups_resume(void)
884{
885 int i;
886
887 for (i = 0; i < NUM_BANKS; i++) {
888 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
889
890 if (!chip)
891 break;
892
893 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
894 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
895
896 if (cpu_is_u8500v2())
897 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
898 }
899}
900
901static int __devinit nmk_gpio_probe(struct platform_device *dev)
902{
903 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
904 struct nmk_gpio_chip *nmk_chip;
905 struct gpio_chip *chip;
906 struct resource *res;
907 struct clk *clk;
908 int secondary_irq;
909 int irq;
910 int ret;
911
912 if (!pdata)
913 return -ENODEV;
914
915 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
916 if (!res) {
917 ret = -ENOENT;
918 goto out;
919 }
920
921 irq = platform_get_irq(dev, 0);
922 if (irq < 0) {
923 ret = irq;
924 goto out;
925 }
926
927 secondary_irq = platform_get_irq(dev, 1);
928 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
929 ret = -EINVAL;
930 goto out;
931 }
932
933 if (request_mem_region(res->start, resource_size(res),
934 dev_name(&dev->dev)) == NULL) {
935 ret = -EBUSY;
936 goto out;
937 }
938
939 clk = clk_get(&dev->dev, NULL);
940 if (IS_ERR(clk)) {
941 ret = PTR_ERR(clk);
942 goto out_release;
943 }
944
945 clk_enable(clk);
946
947 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
948 if (!nmk_chip) {
949 ret = -ENOMEM;
950 goto out_clk;
951 }
952 /*
953 * The virt address in nmk_chip->addr is in the nomadik register space,
954 * so we can simply convert the resource address, without remapping
955 */
956 nmk_chip->bank = dev->id;
957 nmk_chip->clk = clk;
958 nmk_chip->addr = io_p2v(res->start);
959 nmk_chip->chip = nmk_gpio_template;
960 nmk_chip->parent_irq = irq;
961 nmk_chip->secondary_parent_irq = secondary_irq;
962 nmk_chip->get_secondary_status = pdata->get_secondary_status;
963 nmk_chip->set_ioforce = pdata->set_ioforce;
964 spin_lock_init(&nmk_chip->lock);
965
966 chip = &nmk_chip->chip;
967 chip->base = pdata->first_gpio;
968 chip->ngpio = pdata->num_gpio;
969 chip->label = pdata->name ?: dev_name(&dev->dev);
970 chip->dev = &dev->dev;
971 chip->owner = THIS_MODULE;
972
973 ret = gpiochip_add(&nmk_chip->chip);
974 if (ret)
975 goto out_free;
976
977 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
978
979 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
980 platform_set_drvdata(dev, nmk_chip);
981
982 nmk_gpio_init_irq(nmk_chip);
983
984 dev_info(&dev->dev, "Bits %i-%i at address %p\n",
985 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
986 return 0;
987
988out_free:
989 kfree(nmk_chip);
990out_clk:
991 clk_disable(clk);
992 clk_put(clk);
993out_release:
994 release_mem_region(res->start, resource_size(res));
995out:
996 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
997 pdata->first_gpio, pdata->first_gpio+31);
998 return ret;
999}
1000
1001static struct platform_driver nmk_gpio_driver = {
1002 .driver = {
1003 .owner = THIS_MODULE,
1004 .name = "gpio",
1005 },
1006 .probe = nmk_gpio_probe,
1007};
1008
1009static int __init nmk_gpio_init(void)
1010{
1011 return platform_driver_register(&nmk_gpio_driver);
1012}
1013
1014core_initcall(nmk_gpio_init);
1015
1016MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1017MODULE_DESCRIPTION("Nomadik GPIO Driver");
1018MODULE_LICENSE("GPL");
1019
1020
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 1b9f6f0843d..ea19a5b2f22 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -78,6 +78,8 @@ extern int nmk_gpio_get_mode(int gpio);
78extern void nmk_gpio_wakeups_suspend(void); 78extern void nmk_gpio_wakeups_suspend(void);
79extern void nmk_gpio_wakeups_resume(void); 79extern void nmk_gpio_wakeups_resume(void);
80 80
81extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up);
82
81/* 83/*
82 * Platform data to register a block: only the initial gpio/irq number. 84 * Platform data to register a block: only the initial gpio/irq number.
83 */ 85 */
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index a4a12859fdd..f0233e6abcd 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
7 usb.o fb.o io.o counter_32k.o 7 usb.o fb.o io.o counter_32k.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
deleted file mode 100644
index efb86939019..00000000000
--- a/arch/arm/plat-omap/gpio.c
+++ /dev/null
@@ -1,2112 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/interrupt.h>
20#include <linux/syscore_ops.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
26
27#include <mach/hardware.h>
28#include <asm/irq.h>
29#include <mach/irqs.h>
30#include <mach/gpio.h>
31#include <asm/mach/irq.h>
32
33/*
34 * OMAP1510 GPIO registers
35 */
36#define OMAP1510_GPIO_DATA_INPUT 0x00
37#define OMAP1510_GPIO_DATA_OUTPUT 0x04
38#define OMAP1510_GPIO_DIR_CONTROL 0x08
39#define OMAP1510_GPIO_INT_CONTROL 0x0c
40#define OMAP1510_GPIO_INT_MASK 0x10
41#define OMAP1510_GPIO_INT_STATUS 0x14
42#define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44#define OMAP1510_IH_GPIO_BASE 64
45
46/*
47 * OMAP1610 specific GPIO registers
48 */
49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014
52#define OMAP1610_GPIO_IRQSTATUS1 0x0018
53#define OMAP1610_GPIO_IRQENABLE1 0x001c
54#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55#define OMAP1610_GPIO_DATAIN 0x002c
56#define OMAP1610_GPIO_DATAOUT 0x0030
57#define OMAP1610_GPIO_DIRECTION 0x0034
58#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67/*
68 * OMAP7XX specific GPIO registers
69 */
70#define OMAP7XX_GPIO_DATA_INPUT 0x00
71#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
72#define OMAP7XX_GPIO_DIR_CONTROL 0x08
73#define OMAP7XX_GPIO_INT_CONTROL 0x0c
74#define OMAP7XX_GPIO_INT_MASK 0x10
75#define OMAP7XX_GPIO_INT_STATUS 0x14
76
77/*
78 * omap2+ specific GPIO registers
79 */
80#define OMAP24XX_GPIO_REVISION 0x0000
81#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
82#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
83#define OMAP24XX_GPIO_IRQENABLE2 0x002c
84#define OMAP24XX_GPIO_IRQENABLE1 0x001c
85#define OMAP24XX_GPIO_WAKE_EN 0x0020
86#define OMAP24XX_GPIO_CTRL 0x0030
87#define OMAP24XX_GPIO_OE 0x0034
88#define OMAP24XX_GPIO_DATAIN 0x0038
89#define OMAP24XX_GPIO_DATAOUT 0x003c
90#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
91#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
92#define OMAP24XX_GPIO_RISINGDETECT 0x0048
93#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
94#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
95#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
96#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
97#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
98#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
99#define OMAP24XX_GPIO_SETWKUENA 0x0084
100#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
101#define OMAP24XX_GPIO_SETDATAOUT 0x0094
102
103#define OMAP4_GPIO_REVISION 0x0000
104#define OMAP4_GPIO_EOI 0x0020
105#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
106#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
107#define OMAP4_GPIO_IRQSTATUS0 0x002c
108#define OMAP4_GPIO_IRQSTATUS1 0x0030
109#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
110#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
111#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
112#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
113#define OMAP4_GPIO_IRQWAKEN0 0x0044
114#define OMAP4_GPIO_IRQWAKEN1 0x0048
115#define OMAP4_GPIO_IRQENABLE1 0x011c
116#define OMAP4_GPIO_WAKE_EN 0x0120
117#define OMAP4_GPIO_IRQSTATUS2 0x0128
118#define OMAP4_GPIO_IRQENABLE2 0x012c
119#define OMAP4_GPIO_CTRL 0x0130
120#define OMAP4_GPIO_OE 0x0134
121#define OMAP4_GPIO_DATAIN 0x0138
122#define OMAP4_GPIO_DATAOUT 0x013c
123#define OMAP4_GPIO_LEVELDETECT0 0x0140
124#define OMAP4_GPIO_LEVELDETECT1 0x0144
125#define OMAP4_GPIO_RISINGDETECT 0x0148
126#define OMAP4_GPIO_FALLINGDETECT 0x014c
127#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
128#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
129#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
130#define OMAP4_GPIO_SETIRQENABLE1 0x0164
131#define OMAP4_GPIO_CLEARWKUENA 0x0180
132#define OMAP4_GPIO_SETWKUENA 0x0184
133#define OMAP4_GPIO_CLEARDATAOUT 0x0190
134#define OMAP4_GPIO_SETDATAOUT 0x0194
135
136struct gpio_bank {
137 unsigned long pbase;
138 void __iomem *base;
139 u16 irq;
140 u16 virtual_irq_start;
141 int method;
142#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
143 u32 suspend_wakeup;
144 u32 saved_wakeup;
145#endif
146 u32 non_wakeup_gpios;
147 u32 enabled_non_wakeup_gpios;
148
149 u32 saved_datain;
150 u32 saved_fallingdetect;
151 u32 saved_risingdetect;
152 u32 level_mask;
153 u32 toggle_mask;
154 spinlock_t lock;
155 struct gpio_chip chip;
156 struct clk *dbck;
157 u32 mod_usage;
158 u32 dbck_enable_mask;
159 struct device *dev;
160 bool dbck_flag;
161 int stride;
162};
163
164#ifdef CONFIG_ARCH_OMAP3
165struct omap3_gpio_regs {
166 u32 irqenable1;
167 u32 irqenable2;
168 u32 wake_en;
169 u32 ctrl;
170 u32 oe;
171 u32 leveldetect0;
172 u32 leveldetect1;
173 u32 risingdetect;
174 u32 fallingdetect;
175 u32 dataout;
176};
177
178static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
179#endif
180
181/*
182 * TODO: Cleanup gpio_bank usage as it is having information
183 * related to all instances of the device
184 */
185static struct gpio_bank *gpio_bank;
186
187static int bank_width;
188
189/* TODO: Analyze removing gpio_bank_count usage from driver code */
190int gpio_bank_count;
191
192static inline struct gpio_bank *get_gpio_bank(int gpio)
193{
194 if (cpu_is_omap15xx()) {
195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1];
198 }
199 if (cpu_is_omap16xx()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 4)];
203 }
204 if (cpu_is_omap7xx()) {
205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1 + (gpio >> 5)];
208 }
209 if (cpu_is_omap24xx())
210 return &gpio_bank[gpio >> 5];
211 if (cpu_is_omap34xx() || cpu_is_omap44xx())
212 return &gpio_bank[gpio >> 5];
213 BUG();
214 return NULL;
215}
216
217static inline int get_gpio_index(int gpio)
218{
219 if (cpu_is_omap7xx())
220 return gpio & 0x1f;
221 if (cpu_is_omap24xx())
222 return gpio & 0x1f;
223 if (cpu_is_omap34xx() || cpu_is_omap44xx())
224 return gpio & 0x1f;
225 return gpio & 0x0f;
226}
227
228static inline int gpio_valid(int gpio)
229{
230 if (gpio < 0)
231 return -1;
232 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
233 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
234 return -1;
235 return 0;
236 }
237 if (cpu_is_omap15xx() && gpio < 16)
238 return 0;
239 if ((cpu_is_omap16xx()) && gpio < 64)
240 return 0;
241 if (cpu_is_omap7xx() && gpio < 192)
242 return 0;
243 if (cpu_is_omap2420() && gpio < 128)
244 return 0;
245 if (cpu_is_omap2430() && gpio < 160)
246 return 0;
247 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
248 return 0;
249 return -1;
250}
251
252static int check_gpio(int gpio)
253{
254 if (unlikely(gpio_valid(gpio) < 0)) {
255 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
256 dump_stack();
257 return -1;
258 }
259 return 0;
260}
261
262static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
263{
264 void __iomem *reg = bank->base;
265 u32 l;
266
267 switch (bank->method) {
268#ifdef CONFIG_ARCH_OMAP1
269 case METHOD_MPUIO:
270 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
271 break;
272#endif
273#ifdef CONFIG_ARCH_OMAP15XX
274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
276 break;
277#endif
278#ifdef CONFIG_ARCH_OMAP16XX
279 case METHOD_GPIO_1610:
280 reg += OMAP1610_GPIO_DIRECTION;
281 break;
282#endif
283#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
284 case METHOD_GPIO_7XX:
285 reg += OMAP7XX_GPIO_DIR_CONTROL;
286 break;
287#endif
288#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
289 case METHOD_GPIO_24XX:
290 reg += OMAP24XX_GPIO_OE;
291 break;
292#endif
293#if defined(CONFIG_ARCH_OMAP4)
294 case METHOD_GPIO_44XX:
295 reg += OMAP4_GPIO_OE;
296 break;
297#endif
298 default:
299 WARN_ON(1);
300 return;
301 }
302 l = __raw_readl(reg);
303 if (is_input)
304 l |= 1 << gpio;
305 else
306 l &= ~(1 << gpio);
307 __raw_writel(l, reg);
308}
309
310static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
311{
312 void __iomem *reg = bank->base;
313 u32 l = 0;
314
315 switch (bank->method) {
316#ifdef CONFIG_ARCH_OMAP1
317 case METHOD_MPUIO:
318 reg += OMAP_MPUIO_OUTPUT / bank->stride;
319 l = __raw_readl(reg);
320 if (enable)
321 l |= 1 << gpio;
322 else
323 l &= ~(1 << gpio);
324 break;
325#endif
326#ifdef CONFIG_ARCH_OMAP15XX
327 case METHOD_GPIO_1510:
328 reg += OMAP1510_GPIO_DATA_OUTPUT;
329 l = __raw_readl(reg);
330 if (enable)
331 l |= 1 << gpio;
332 else
333 l &= ~(1 << gpio);
334 break;
335#endif
336#ifdef CONFIG_ARCH_OMAP16XX
337 case METHOD_GPIO_1610:
338 if (enable)
339 reg += OMAP1610_GPIO_SET_DATAOUT;
340 else
341 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
342 l = 1 << gpio;
343 break;
344#endif
345#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
346 case METHOD_GPIO_7XX:
347 reg += OMAP7XX_GPIO_DATA_OUTPUT;
348 l = __raw_readl(reg);
349 if (enable)
350 l |= 1 << gpio;
351 else
352 l &= ~(1 << gpio);
353 break;
354#endif
355#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
356 case METHOD_GPIO_24XX:
357 if (enable)
358 reg += OMAP24XX_GPIO_SETDATAOUT;
359 else
360 reg += OMAP24XX_GPIO_CLEARDATAOUT;
361 l = 1 << gpio;
362 break;
363#endif
364#ifdef CONFIG_ARCH_OMAP4
365 case METHOD_GPIO_44XX:
366 if (enable)
367 reg += OMAP4_GPIO_SETDATAOUT;
368 else
369 reg += OMAP4_GPIO_CLEARDATAOUT;
370 l = 1 << gpio;
371 break;
372#endif
373 default:
374 WARN_ON(1);
375 return;
376 }
377 __raw_writel(l, reg);
378}
379
380static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
381{
382 void __iomem *reg;
383
384 if (check_gpio(gpio) < 0)
385 return -EINVAL;
386 reg = bank->base;
387 switch (bank->method) {
388#ifdef CONFIG_ARCH_OMAP1
389 case METHOD_MPUIO:
390 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
391 break;
392#endif
393#ifdef CONFIG_ARCH_OMAP15XX
394 case METHOD_GPIO_1510:
395 reg += OMAP1510_GPIO_DATA_INPUT;
396 break;
397#endif
398#ifdef CONFIG_ARCH_OMAP16XX
399 case METHOD_GPIO_1610:
400 reg += OMAP1610_GPIO_DATAIN;
401 break;
402#endif
403#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
404 case METHOD_GPIO_7XX:
405 reg += OMAP7XX_GPIO_DATA_INPUT;
406 break;
407#endif
408#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
409 case METHOD_GPIO_24XX:
410 reg += OMAP24XX_GPIO_DATAIN;
411 break;
412#endif
413#ifdef CONFIG_ARCH_OMAP4
414 case METHOD_GPIO_44XX:
415 reg += OMAP4_GPIO_DATAIN;
416 break;
417#endif
418 default:
419 return -EINVAL;
420 }
421 return (__raw_readl(reg)
422 & (1 << get_gpio_index(gpio))) != 0;
423}
424
425static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
426{
427 void __iomem *reg;
428
429 if (check_gpio(gpio) < 0)
430 return -EINVAL;
431 reg = bank->base;
432
433 switch (bank->method) {
434#ifdef CONFIG_ARCH_OMAP1
435 case METHOD_MPUIO:
436 reg += OMAP_MPUIO_OUTPUT / bank->stride;
437 break;
438#endif
439#ifdef CONFIG_ARCH_OMAP15XX
440 case METHOD_GPIO_1510:
441 reg += OMAP1510_GPIO_DATA_OUTPUT;
442 break;
443#endif
444#ifdef CONFIG_ARCH_OMAP16XX
445 case METHOD_GPIO_1610:
446 reg += OMAP1610_GPIO_DATAOUT;
447 break;
448#endif
449#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
450 case METHOD_GPIO_7XX:
451 reg += OMAP7XX_GPIO_DATA_OUTPUT;
452 break;
453#endif
454#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
455 case METHOD_GPIO_24XX:
456 reg += OMAP24XX_GPIO_DATAOUT;
457 break;
458#endif
459#ifdef CONFIG_ARCH_OMAP4
460 case METHOD_GPIO_44XX:
461 reg += OMAP4_GPIO_DATAOUT;
462 break;
463#endif
464 default:
465 return -EINVAL;
466 }
467
468 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
469}
470
471#define MOD_REG_BIT(reg, bit_mask, set) \
472do { \
473 int l = __raw_readl(base + reg); \
474 if (set) l |= bit_mask; \
475 else l &= ~bit_mask; \
476 __raw_writel(l, base + reg); \
477} while(0)
478
479/**
480 * _set_gpio_debounce - low level gpio debounce time
481 * @bank: the gpio bank we're acting upon
482 * @gpio: the gpio number on this @gpio
483 * @debounce: debounce time to use
484 *
485 * OMAP's debounce time is in 31us steps so we need
486 * to convert and round up to the closest unit.
487 */
488static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
489 unsigned debounce)
490{
491 void __iomem *reg = bank->base;
492 u32 val;
493 u32 l;
494
495 if (!bank->dbck_flag)
496 return;
497
498 if (debounce < 32)
499 debounce = 0x01;
500 else if (debounce > 7936)
501 debounce = 0xff;
502 else
503 debounce = (debounce / 0x1f) - 1;
504
505 l = 1 << get_gpio_index(gpio);
506
507 if (bank->method == METHOD_GPIO_44XX)
508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
509 else
510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
511
512 __raw_writel(debounce, reg);
513
514 reg = bank->base;
515 if (bank->method == METHOD_GPIO_44XX)
516 reg += OMAP4_GPIO_DEBOUNCENABLE;
517 else
518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
519
520 val = __raw_readl(reg);
521
522 if (debounce) {
523 val |= l;
524 clk_enable(bank->dbck);
525 } else {
526 val &= ~l;
527 clk_disable(bank->dbck);
528 }
529 bank->dbck_enable_mask = val;
530
531 __raw_writel(val, reg);
532}
533
534#ifdef CONFIG_ARCH_OMAP2PLUS
535static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
536 int trigger)
537{
538 void __iomem *base = bank->base;
539 u32 gpio_bit = 1 << gpio;
540 u32 val;
541
542 if (cpu_is_omap44xx()) {
543 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544 trigger & IRQ_TYPE_LEVEL_LOW);
545 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546 trigger & IRQ_TYPE_LEVEL_HIGH);
547 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548 trigger & IRQ_TYPE_EDGE_RISING);
549 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550 trigger & IRQ_TYPE_EDGE_FALLING);
551 } else {
552 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553 trigger & IRQ_TYPE_LEVEL_LOW);
554 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555 trigger & IRQ_TYPE_LEVEL_HIGH);
556 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557 trigger & IRQ_TYPE_EDGE_RISING);
558 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559 trigger & IRQ_TYPE_EDGE_FALLING);
560 }
561 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
562 if (cpu_is_omap44xx()) {
563 if (trigger != 0)
564 __raw_writel(1 << gpio, bank->base+
565 OMAP4_GPIO_IRQWAKEN0);
566 else {
567 val = __raw_readl(bank->base +
568 OMAP4_GPIO_IRQWAKEN0);
569 __raw_writel(val & (~(1 << gpio)), bank->base +
570 OMAP4_GPIO_IRQWAKEN0);
571 }
572 } else {
573 /*
574 * GPIO wakeup request can only be generated on edge
575 * transitions
576 */
577 if (trigger & IRQ_TYPE_EDGE_BOTH)
578 __raw_writel(1 << gpio, bank->base
579 + OMAP24XX_GPIO_SETWKUENA);
580 else
581 __raw_writel(1 << gpio, bank->base
582 + OMAP24XX_GPIO_CLEARWKUENA);
583 }
584 }
585 /* This part needs to be executed always for OMAP34xx */
586 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
587 /*
588 * Log the edge gpio and manually trigger the IRQ
589 * after resume if the input level changes
590 * to avoid irq lost during PER RET/OFF mode
591 * Applies for omap2 non-wakeup gpio and all omap3 gpios
592 */
593 if (trigger & IRQ_TYPE_EDGE_BOTH)
594 bank->enabled_non_wakeup_gpios |= gpio_bit;
595 else
596 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
597 }
598
599 if (cpu_is_omap44xx()) {
600 bank->level_mask =
601 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
603 } else {
604 bank->level_mask =
605 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
607 }
608}
609#endif
610
611#ifdef CONFIG_ARCH_OMAP1
612/*
613 * This only applies to chips that can't do both rising and falling edge
614 * detection at once. For all other chips, this function is a noop.
615 */
616static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
617{
618 void __iomem *reg = bank->base;
619 u32 l = 0;
620
621 switch (bank->method) {
622 case METHOD_MPUIO:
623 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
624 break;
625#ifdef CONFIG_ARCH_OMAP15XX
626 case METHOD_GPIO_1510:
627 reg += OMAP1510_GPIO_INT_CONTROL;
628 break;
629#endif
630#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631 case METHOD_GPIO_7XX:
632 reg += OMAP7XX_GPIO_INT_CONTROL;
633 break;
634#endif
635 default:
636 return;
637 }
638
639 l = __raw_readl(reg);
640 if ((l >> gpio) & 1)
641 l &= ~(1 << gpio);
642 else
643 l |= 1 << gpio;
644
645 __raw_writel(l, reg);
646}
647#endif
648
649static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
650{
651 void __iomem *reg = bank->base;
652 u32 l = 0;
653
654 switch (bank->method) {
655#ifdef CONFIG_ARCH_OMAP1
656 case METHOD_MPUIO:
657 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
658 l = __raw_readl(reg);
659 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
660 bank->toggle_mask |= 1 << gpio;
661 if (trigger & IRQ_TYPE_EDGE_RISING)
662 l |= 1 << gpio;
663 else if (trigger & IRQ_TYPE_EDGE_FALLING)
664 l &= ~(1 << gpio);
665 else
666 goto bad;
667 break;
668#endif
669#ifdef CONFIG_ARCH_OMAP15XX
670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_CONTROL;
672 l = __raw_readl(reg);
673 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
674 bank->toggle_mask |= 1 << gpio;
675 if (trigger & IRQ_TYPE_EDGE_RISING)
676 l |= 1 << gpio;
677 else if (trigger & IRQ_TYPE_EDGE_FALLING)
678 l &= ~(1 << gpio);
679 else
680 goto bad;
681 break;
682#endif
683#ifdef CONFIG_ARCH_OMAP16XX
684 case METHOD_GPIO_1610:
685 if (gpio & 0x08)
686 reg += OMAP1610_GPIO_EDGE_CTRL2;
687 else
688 reg += OMAP1610_GPIO_EDGE_CTRL1;
689 gpio &= 0x07;
690 l = __raw_readl(reg);
691 l &= ~(3 << (gpio << 1));
692 if (trigger & IRQ_TYPE_EDGE_RISING)
693 l |= 2 << (gpio << 1);
694 if (trigger & IRQ_TYPE_EDGE_FALLING)
695 l |= 1 << (gpio << 1);
696 if (trigger)
697 /* Enable wake-up during idle for dynamic tick */
698 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
699 else
700 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
701 break;
702#endif
703#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
704 case METHOD_GPIO_7XX:
705 reg += OMAP7XX_GPIO_INT_CONTROL;
706 l = __raw_readl(reg);
707 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
708 bank->toggle_mask |= 1 << gpio;
709 if (trigger & IRQ_TYPE_EDGE_RISING)
710 l |= 1 << gpio;
711 else if (trigger & IRQ_TYPE_EDGE_FALLING)
712 l &= ~(1 << gpio);
713 else
714 goto bad;
715 break;
716#endif
717#ifdef CONFIG_ARCH_OMAP2PLUS
718 case METHOD_GPIO_24XX:
719 case METHOD_GPIO_44XX:
720 set_24xx_gpio_triggering(bank, gpio, trigger);
721 return 0;
722#endif
723 default:
724 goto bad;
725 }
726 __raw_writel(l, reg);
727 return 0;
728bad:
729 return -EINVAL;
730}
731
732static int gpio_irq_type(struct irq_data *d, unsigned type)
733{
734 struct gpio_bank *bank;
735 unsigned gpio;
736 int retval;
737 unsigned long flags;
738
739 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
740 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
741 else
742 gpio = d->irq - IH_GPIO_BASE;
743
744 if (check_gpio(gpio) < 0)
745 return -EINVAL;
746
747 if (type & ~IRQ_TYPE_SENSE_MASK)
748 return -EINVAL;
749
750 /* OMAP1 allows only only edge triggering */
751 if (!cpu_class_is_omap2()
752 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
753 return -EINVAL;
754
755 bank = irq_data_get_irq_chip_data(d);
756 spin_lock_irqsave(&bank->lock, flags);
757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
758 spin_unlock_irqrestore(&bank->lock, flags);
759
760 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
761 __irq_set_handler_locked(d->irq, handle_level_irq);
762 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
763 __irq_set_handler_locked(d->irq, handle_edge_irq);
764
765 return retval;
766}
767
768static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
769{
770 void __iomem *reg = bank->base;
771
772 switch (bank->method) {
773#ifdef CONFIG_ARCH_OMAP1
774 case METHOD_MPUIO:
775 /* MPUIO irqstatus is reset by reading the status register,
776 * so do nothing here */
777 return;
778#endif
779#ifdef CONFIG_ARCH_OMAP15XX
780 case METHOD_GPIO_1510:
781 reg += OMAP1510_GPIO_INT_STATUS;
782 break;
783#endif
784#ifdef CONFIG_ARCH_OMAP16XX
785 case METHOD_GPIO_1610:
786 reg += OMAP1610_GPIO_IRQSTATUS1;
787 break;
788#endif
789#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
790 case METHOD_GPIO_7XX:
791 reg += OMAP7XX_GPIO_INT_STATUS;
792 break;
793#endif
794#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
795 case METHOD_GPIO_24XX:
796 reg += OMAP24XX_GPIO_IRQSTATUS1;
797 break;
798#endif
799#if defined(CONFIG_ARCH_OMAP4)
800 case METHOD_GPIO_44XX:
801 reg += OMAP4_GPIO_IRQSTATUS0;
802 break;
803#endif
804 default:
805 WARN_ON(1);
806 return;
807 }
808 __raw_writel(gpio_mask, reg);
809
810 /* Workaround for clearing DSP GPIO interrupts to allow retention */
811 if (cpu_is_omap24xx() || cpu_is_omap34xx())
812 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
813 else if (cpu_is_omap44xx())
814 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
815
816 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
817 __raw_writel(gpio_mask, reg);
818
819 /* Flush posted write for the irq status to avoid spurious interrupts */
820 __raw_readl(reg);
821 }
822}
823
824static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
825{
826 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
827}
828
829static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
830{
831 void __iomem *reg = bank->base;
832 int inv = 0;
833 u32 l;
834 u32 mask;
835
836 switch (bank->method) {
837#ifdef CONFIG_ARCH_OMAP1
838 case METHOD_MPUIO:
839 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
840 mask = 0xffff;
841 inv = 1;
842 break;
843#endif
844#ifdef CONFIG_ARCH_OMAP15XX
845 case METHOD_GPIO_1510:
846 reg += OMAP1510_GPIO_INT_MASK;
847 mask = 0xffff;
848 inv = 1;
849 break;
850#endif
851#ifdef CONFIG_ARCH_OMAP16XX
852 case METHOD_GPIO_1610:
853 reg += OMAP1610_GPIO_IRQENABLE1;
854 mask = 0xffff;
855 break;
856#endif
857#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
858 case METHOD_GPIO_7XX:
859 reg += OMAP7XX_GPIO_INT_MASK;
860 mask = 0xffffffff;
861 inv = 1;
862 break;
863#endif
864#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
865 case METHOD_GPIO_24XX:
866 reg += OMAP24XX_GPIO_IRQENABLE1;
867 mask = 0xffffffff;
868 break;
869#endif
870#if defined(CONFIG_ARCH_OMAP4)
871 case METHOD_GPIO_44XX:
872 reg += OMAP4_GPIO_IRQSTATUSSET0;
873 mask = 0xffffffff;
874 break;
875#endif
876 default:
877 WARN_ON(1);
878 return 0;
879 }
880
881 l = __raw_readl(reg);
882 if (inv)
883 l = ~l;
884 l &= mask;
885 return l;
886}
887
888static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
889{
890 void __iomem *reg = bank->base;
891 u32 l;
892
893 switch (bank->method) {
894#ifdef CONFIG_ARCH_OMAP1
895 case METHOD_MPUIO:
896 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
897 l = __raw_readl(reg);
898 if (enable)
899 l &= ~(gpio_mask);
900 else
901 l |= gpio_mask;
902 break;
903#endif
904#ifdef CONFIG_ARCH_OMAP15XX
905 case METHOD_GPIO_1510:
906 reg += OMAP1510_GPIO_INT_MASK;
907 l = __raw_readl(reg);
908 if (enable)
909 l &= ~(gpio_mask);
910 else
911 l |= gpio_mask;
912 break;
913#endif
914#ifdef CONFIG_ARCH_OMAP16XX
915 case METHOD_GPIO_1610:
916 if (enable)
917 reg += OMAP1610_GPIO_SET_IRQENABLE1;
918 else
919 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
920 l = gpio_mask;
921 break;
922#endif
923#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
924 case METHOD_GPIO_7XX:
925 reg += OMAP7XX_GPIO_INT_MASK;
926 l = __raw_readl(reg);
927 if (enable)
928 l &= ~(gpio_mask);
929 else
930 l |= gpio_mask;
931 break;
932#endif
933#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
934 case METHOD_GPIO_24XX:
935 if (enable)
936 reg += OMAP24XX_GPIO_SETIRQENABLE1;
937 else
938 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
939 l = gpio_mask;
940 break;
941#endif
942#ifdef CONFIG_ARCH_OMAP4
943 case METHOD_GPIO_44XX:
944 if (enable)
945 reg += OMAP4_GPIO_IRQSTATUSSET0;
946 else
947 reg += OMAP4_GPIO_IRQSTATUSCLR0;
948 l = gpio_mask;
949 break;
950#endif
951 default:
952 WARN_ON(1);
953 return;
954 }
955 __raw_writel(l, reg);
956}
957
958static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
959{
960 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
961}
962
963/*
964 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
965 * 1510 does not seem to have a wake-up register. If JTAG is connected
966 * to the target, system will wake up always on GPIO events. While
967 * system is running all registered GPIO interrupts need to have wake-up
968 * enabled. When system is suspended, only selected GPIO interrupts need
969 * to have wake-up enabled.
970 */
971static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
972{
973 unsigned long uninitialized_var(flags);
974
975 switch (bank->method) {
976#ifdef CONFIG_ARCH_OMAP16XX
977 case METHOD_MPUIO:
978 case METHOD_GPIO_1610:
979 spin_lock_irqsave(&bank->lock, flags);
980 if (enable)
981 bank->suspend_wakeup |= (1 << gpio);
982 else
983 bank->suspend_wakeup &= ~(1 << gpio);
984 spin_unlock_irqrestore(&bank->lock, flags);
985 return 0;
986#endif
987#ifdef CONFIG_ARCH_OMAP2PLUS
988 case METHOD_GPIO_24XX:
989 case METHOD_GPIO_44XX:
990 if (bank->non_wakeup_gpios & (1 << gpio)) {
991 printk(KERN_ERR "Unable to modify wakeup on "
992 "non-wakeup GPIO%d\n",
993 (bank - gpio_bank) * 32 + gpio);
994 return -EINVAL;
995 }
996 spin_lock_irqsave(&bank->lock, flags);
997 if (enable)
998 bank->suspend_wakeup |= (1 << gpio);
999 else
1000 bank->suspend_wakeup &= ~(1 << gpio);
1001 spin_unlock_irqrestore(&bank->lock, flags);
1002 return 0;
1003#endif
1004 default:
1005 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1006 bank->method);
1007 return -EINVAL;
1008 }
1009}
1010
1011static void _reset_gpio(struct gpio_bank *bank, int gpio)
1012{
1013 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1014 _set_gpio_irqenable(bank, gpio, 0);
1015 _clear_gpio_irqstatus(bank, gpio);
1016 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1017}
1018
1019/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1020static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
1021{
1022 unsigned int gpio = d->irq - IH_GPIO_BASE;
1023 struct gpio_bank *bank;
1024 int retval;
1025
1026 if (check_gpio(gpio) < 0)
1027 return -ENODEV;
1028 bank = irq_data_get_irq_chip_data(d);
1029 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1030
1031 return retval;
1032}
1033
1034static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1035{
1036 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&bank->lock, flags);
1040
1041 /* Set trigger to none. You need to enable the desired trigger with
1042 * request_irq() or set_irq_type().
1043 */
1044 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1045
1046#ifdef CONFIG_ARCH_OMAP15XX
1047 if (bank->method == METHOD_GPIO_1510) {
1048 void __iomem *reg;
1049
1050 /* Claim the pin for MPU */
1051 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1052 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1053 }
1054#endif
1055 if (!cpu_class_is_omap1()) {
1056 if (!bank->mod_usage) {
1057 void __iomem *reg = bank->base;
1058 u32 ctrl;
1059
1060 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1061 reg += OMAP24XX_GPIO_CTRL;
1062 else if (cpu_is_omap44xx())
1063 reg += OMAP4_GPIO_CTRL;
1064 ctrl = __raw_readl(reg);
1065 /* Module is enabled, clocks are not gated */
1066 ctrl &= 0xFFFFFFFE;
1067 __raw_writel(ctrl, reg);
1068 }
1069 bank->mod_usage |= 1 << offset;
1070 }
1071 spin_unlock_irqrestore(&bank->lock, flags);
1072
1073 return 0;
1074}
1075
1076static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1077{
1078 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1079 unsigned long flags;
1080
1081 spin_lock_irqsave(&bank->lock, flags);
1082#ifdef CONFIG_ARCH_OMAP16XX
1083 if (bank->method == METHOD_GPIO_1610) {
1084 /* Disable wake-up during idle for dynamic tick */
1085 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1086 __raw_writel(1 << offset, reg);
1087 }
1088#endif
1089#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1090 if (bank->method == METHOD_GPIO_24XX) {
1091 /* Disable wake-up during idle for dynamic tick */
1092 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1093 __raw_writel(1 << offset, reg);
1094 }
1095#endif
1096#ifdef CONFIG_ARCH_OMAP4
1097 if (bank->method == METHOD_GPIO_44XX) {
1098 /* Disable wake-up during idle for dynamic tick */
1099 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1100 __raw_writel(1 << offset, reg);
1101 }
1102#endif
1103 if (!cpu_class_is_omap1()) {
1104 bank->mod_usage &= ~(1 << offset);
1105 if (!bank->mod_usage) {
1106 void __iomem *reg = bank->base;
1107 u32 ctrl;
1108
1109 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1110 reg += OMAP24XX_GPIO_CTRL;
1111 else if (cpu_is_omap44xx())
1112 reg += OMAP4_GPIO_CTRL;
1113 ctrl = __raw_readl(reg);
1114 /* Module is disabled, clocks are gated */
1115 ctrl |= 1;
1116 __raw_writel(ctrl, reg);
1117 }
1118 }
1119 _reset_gpio(bank, bank->chip.base + offset);
1120 spin_unlock_irqrestore(&bank->lock, flags);
1121}
1122
1123/*
1124 * We need to unmask the GPIO bank interrupt as soon as possible to
1125 * avoid missing GPIO interrupts for other lines in the bank.
1126 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1127 * in the bank to avoid missing nested interrupts for a GPIO line.
1128 * If we wait to unmask individual GPIO lines in the bank after the
1129 * line's interrupt handler has been run, we may miss some nested
1130 * interrupts.
1131 */
1132static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1133{
1134 void __iomem *isr_reg = NULL;
1135 u32 isr;
1136 unsigned int gpio_irq, gpio_index;
1137 struct gpio_bank *bank;
1138 u32 retrigger = 0;
1139 int unmasked = 0;
1140 struct irq_chip *chip = irq_desc_get_chip(desc);
1141
1142 chained_irq_enter(chip, desc);
1143
1144 bank = irq_get_handler_data(irq);
1145#ifdef CONFIG_ARCH_OMAP1
1146 if (bank->method == METHOD_MPUIO)
1147 isr_reg = bank->base +
1148 OMAP_MPUIO_GPIO_INT / bank->stride;
1149#endif
1150#ifdef CONFIG_ARCH_OMAP15XX
1151 if (bank->method == METHOD_GPIO_1510)
1152 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1153#endif
1154#if defined(CONFIG_ARCH_OMAP16XX)
1155 if (bank->method == METHOD_GPIO_1610)
1156 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1157#endif
1158#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1159 if (bank->method == METHOD_GPIO_7XX)
1160 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1161#endif
1162#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1163 if (bank->method == METHOD_GPIO_24XX)
1164 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1165#endif
1166#if defined(CONFIG_ARCH_OMAP4)
1167 if (bank->method == METHOD_GPIO_44XX)
1168 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1169#endif
1170
1171 if (WARN_ON(!isr_reg))
1172 goto exit;
1173
1174 while(1) {
1175 u32 isr_saved, level_mask = 0;
1176 u32 enabled;
1177
1178 enabled = _get_gpio_irqbank_mask(bank);
1179 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1180
1181 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1182 isr &= 0x0000ffff;
1183
1184 if (cpu_class_is_omap2()) {
1185 level_mask = bank->level_mask & enabled;
1186 }
1187
1188 /* clear edge sensitive interrupts before handler(s) are
1189 called so that we don't miss any interrupt occurred while
1190 executing them */
1191 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1192 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1193 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1194
1195 /* if there is only edge sensitive GPIO pin interrupts
1196 configured, we could unmask GPIO bank interrupt immediately */
1197 if (!level_mask && !unmasked) {
1198 unmasked = 1;
1199 chained_irq_exit(chip, desc);
1200 }
1201
1202 isr |= retrigger;
1203 retrigger = 0;
1204 if (!isr)
1205 break;
1206
1207 gpio_irq = bank->virtual_irq_start;
1208 for (; isr != 0; isr >>= 1, gpio_irq++) {
1209 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1210
1211 if (!(isr & 1))
1212 continue;
1213
1214#ifdef CONFIG_ARCH_OMAP1
1215 /*
1216 * Some chips can't respond to both rising and falling
1217 * at the same time. If this irq was requested with
1218 * both flags, we need to flip the ICR data for the IRQ
1219 * to respond to the IRQ for the opposite direction.
1220 * This will be indicated in the bank toggle_mask.
1221 */
1222 if (bank->toggle_mask & (1 << gpio_index))
1223 _toggle_gpio_edge_triggering(bank, gpio_index);
1224#endif
1225
1226 generic_handle_irq(gpio_irq);
1227 }
1228 }
1229 /* if bank has any level sensitive GPIO pin interrupt
1230 configured, we must unmask the bank interrupt only after
1231 handler(s) are executed in order to avoid spurious bank
1232 interrupt */
1233exit:
1234 if (!unmasked)
1235 chained_irq_exit(chip, desc);
1236}
1237
1238static void gpio_irq_shutdown(struct irq_data *d)
1239{
1240 unsigned int gpio = d->irq - IH_GPIO_BASE;
1241 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1242
1243 _reset_gpio(bank, gpio);
1244}
1245
1246static void gpio_ack_irq(struct irq_data *d)
1247{
1248 unsigned int gpio = d->irq - IH_GPIO_BASE;
1249 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1250
1251 _clear_gpio_irqstatus(bank, gpio);
1252}
1253
1254static void gpio_mask_irq(struct irq_data *d)
1255{
1256 unsigned int gpio = d->irq - IH_GPIO_BASE;
1257 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1258
1259 _set_gpio_irqenable(bank, gpio, 0);
1260 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1261}
1262
1263static void gpio_unmask_irq(struct irq_data *d)
1264{
1265 unsigned int gpio = d->irq - IH_GPIO_BASE;
1266 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1267 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1268 u32 trigger = irqd_get_trigger_type(d);
1269
1270 if (trigger)
1271 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1272
1273 /* For level-triggered GPIOs, the clearing must be done after
1274 * the HW source is cleared, thus after the handler has run */
1275 if (bank->level_mask & irq_mask) {
1276 _set_gpio_irqenable(bank, gpio, 0);
1277 _clear_gpio_irqstatus(bank, gpio);
1278 }
1279
1280 _set_gpio_irqenable(bank, gpio, 1);
1281}
1282
1283static struct irq_chip gpio_irq_chip = {
1284 .name = "GPIO",
1285 .irq_shutdown = gpio_irq_shutdown,
1286 .irq_ack = gpio_ack_irq,
1287 .irq_mask = gpio_mask_irq,
1288 .irq_unmask = gpio_unmask_irq,
1289 .irq_set_type = gpio_irq_type,
1290 .irq_set_wake = gpio_wake_enable,
1291};
1292
1293/*---------------------------------------------------------------------*/
1294
1295#ifdef CONFIG_ARCH_OMAP1
1296
1297/* MPUIO uses the always-on 32k clock */
1298
1299static void mpuio_ack_irq(struct irq_data *d)
1300{
1301 /* The ISR is reset automatically, so do nothing here. */
1302}
1303
1304static void mpuio_mask_irq(struct irq_data *d)
1305{
1306 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1307 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1308
1309 _set_gpio_irqenable(bank, gpio, 0);
1310}
1311
1312static void mpuio_unmask_irq(struct irq_data *d)
1313{
1314 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1315 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1316
1317 _set_gpio_irqenable(bank, gpio, 1);
1318}
1319
1320static struct irq_chip mpuio_irq_chip = {
1321 .name = "MPUIO",
1322 .irq_ack = mpuio_ack_irq,
1323 .irq_mask = mpuio_mask_irq,
1324 .irq_unmask = mpuio_unmask_irq,
1325 .irq_set_type = gpio_irq_type,
1326#ifdef CONFIG_ARCH_OMAP16XX
1327 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1328 .irq_set_wake = gpio_wake_enable,
1329#endif
1330};
1331
1332
1333#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1334
1335
1336#ifdef CONFIG_ARCH_OMAP16XX
1337
1338#include <linux/platform_device.h>
1339
1340static int omap_mpuio_suspend_noirq(struct device *dev)
1341{
1342 struct platform_device *pdev = to_platform_device(dev);
1343 struct gpio_bank *bank = platform_get_drvdata(pdev);
1344 void __iomem *mask_reg = bank->base +
1345 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1346 unsigned long flags;
1347
1348 spin_lock_irqsave(&bank->lock, flags);
1349 bank->saved_wakeup = __raw_readl(mask_reg);
1350 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1351 spin_unlock_irqrestore(&bank->lock, flags);
1352
1353 return 0;
1354}
1355
1356static int omap_mpuio_resume_noirq(struct device *dev)
1357{
1358 struct platform_device *pdev = to_platform_device(dev);
1359 struct gpio_bank *bank = platform_get_drvdata(pdev);
1360 void __iomem *mask_reg = bank->base +
1361 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1362 unsigned long flags;
1363
1364 spin_lock_irqsave(&bank->lock, flags);
1365 __raw_writel(bank->saved_wakeup, mask_reg);
1366 spin_unlock_irqrestore(&bank->lock, flags);
1367
1368 return 0;
1369}
1370
1371static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1372 .suspend_noirq = omap_mpuio_suspend_noirq,
1373 .resume_noirq = omap_mpuio_resume_noirq,
1374};
1375
1376/* use platform_driver for this. */
1377static struct platform_driver omap_mpuio_driver = {
1378 .driver = {
1379 .name = "mpuio",
1380 .pm = &omap_mpuio_dev_pm_ops,
1381 },
1382};
1383
1384static struct platform_device omap_mpuio_device = {
1385 .name = "mpuio",
1386 .id = -1,
1387 .dev = {
1388 .driver = &omap_mpuio_driver.driver,
1389 }
1390 /* could list the /proc/iomem resources */
1391};
1392
1393static inline void mpuio_init(void)
1394{
1395 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1396 platform_set_drvdata(&omap_mpuio_device, bank);
1397
1398 if (platform_driver_register(&omap_mpuio_driver) == 0)
1399 (void) platform_device_register(&omap_mpuio_device);
1400}
1401
1402#else
1403static inline void mpuio_init(void) {}
1404#endif /* 16xx */
1405
1406#else
1407
1408extern struct irq_chip mpuio_irq_chip;
1409
1410#define bank_is_mpuio(bank) 0
1411static inline void mpuio_init(void) {}
1412
1413#endif
1414
1415/*---------------------------------------------------------------------*/
1416
1417/* REVISIT these are stupid implementations! replace by ones that
1418 * don't switch on METHOD_* and which mostly avoid spinlocks
1419 */
1420
1421static int gpio_input(struct gpio_chip *chip, unsigned offset)
1422{
1423 struct gpio_bank *bank;
1424 unsigned long flags;
1425
1426 bank = container_of(chip, struct gpio_bank, chip);
1427 spin_lock_irqsave(&bank->lock, flags);
1428 _set_gpio_direction(bank, offset, 1);
1429 spin_unlock_irqrestore(&bank->lock, flags);
1430 return 0;
1431}
1432
1433static int gpio_is_input(struct gpio_bank *bank, int mask)
1434{
1435 void __iomem *reg = bank->base;
1436
1437 switch (bank->method) {
1438 case METHOD_MPUIO:
1439 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1440 break;
1441 case METHOD_GPIO_1510:
1442 reg += OMAP1510_GPIO_DIR_CONTROL;
1443 break;
1444 case METHOD_GPIO_1610:
1445 reg += OMAP1610_GPIO_DIRECTION;
1446 break;
1447 case METHOD_GPIO_7XX:
1448 reg += OMAP7XX_GPIO_DIR_CONTROL;
1449 break;
1450 case METHOD_GPIO_24XX:
1451 reg += OMAP24XX_GPIO_OE;
1452 break;
1453 case METHOD_GPIO_44XX:
1454 reg += OMAP4_GPIO_OE;
1455 break;
1456 default:
1457 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1458 return -EINVAL;
1459 }
1460 return __raw_readl(reg) & mask;
1461}
1462
1463static int gpio_get(struct gpio_chip *chip, unsigned offset)
1464{
1465 struct gpio_bank *bank;
1466 void __iomem *reg;
1467 int gpio;
1468 u32 mask;
1469
1470 gpio = chip->base + offset;
1471 bank = get_gpio_bank(gpio);
1472 reg = bank->base;
1473 mask = 1 << get_gpio_index(gpio);
1474
1475 if (gpio_is_input(bank, mask))
1476 return _get_gpio_datain(bank, gpio);
1477 else
1478 return _get_gpio_dataout(bank, gpio);
1479}
1480
1481static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1482{
1483 struct gpio_bank *bank;
1484 unsigned long flags;
1485
1486 bank = container_of(chip, struct gpio_bank, chip);
1487 spin_lock_irqsave(&bank->lock, flags);
1488 _set_gpio_dataout(bank, offset, value);
1489 _set_gpio_direction(bank, offset, 0);
1490 spin_unlock_irqrestore(&bank->lock, flags);
1491 return 0;
1492}
1493
1494static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1495 unsigned debounce)
1496{
1497 struct gpio_bank *bank;
1498 unsigned long flags;
1499
1500 bank = container_of(chip, struct gpio_bank, chip);
1501
1502 if (!bank->dbck) {
1503 bank->dbck = clk_get(bank->dev, "dbclk");
1504 if (IS_ERR(bank->dbck))
1505 dev_err(bank->dev, "Could not get gpio dbck\n");
1506 }
1507
1508 spin_lock_irqsave(&bank->lock, flags);
1509 _set_gpio_debounce(bank, offset, debounce);
1510 spin_unlock_irqrestore(&bank->lock, flags);
1511
1512 return 0;
1513}
1514
1515static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1516{
1517 struct gpio_bank *bank;
1518 unsigned long flags;
1519
1520 bank = container_of(chip, struct gpio_bank, chip);
1521 spin_lock_irqsave(&bank->lock, flags);
1522 _set_gpio_dataout(bank, offset, value);
1523 spin_unlock_irqrestore(&bank->lock, flags);
1524}
1525
1526static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1527{
1528 struct gpio_bank *bank;
1529
1530 bank = container_of(chip, struct gpio_bank, chip);
1531 return bank->virtual_irq_start + offset;
1532}
1533
1534/*---------------------------------------------------------------------*/
1535
1536static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1537{
1538 u32 rev;
1539
1540 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1541 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1542 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1543 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1544 else if (cpu_is_omap44xx())
1545 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1546 else
1547 return;
1548
1549 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1550 (rev >> 4) & 0x0f, rev & 0x0f);
1551}
1552
1553/* This lock class tells lockdep that GPIO irqs are in a different
1554 * category than their parents, so it won't report false recursion.
1555 */
1556static struct lock_class_key gpio_lock_class;
1557
1558static inline int init_gpio_info(struct platform_device *pdev)
1559{
1560 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1561 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1562 GFP_KERNEL);
1563 if (!gpio_bank) {
1564 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1565 return -ENOMEM;
1566 }
1567 return 0;
1568}
1569
1570/* TODO: Cleanup cpu_is_* checks */
1571static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1572{
1573 if (cpu_class_is_omap2()) {
1574 if (cpu_is_omap44xx()) {
1575 __raw_writel(0xffffffff, bank->base +
1576 OMAP4_GPIO_IRQSTATUSCLR0);
1577 __raw_writel(0x00000000, bank->base +
1578 OMAP4_GPIO_DEBOUNCENABLE);
1579 /* Initialize interface clk ungated, module enabled */
1580 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1581 } else if (cpu_is_omap34xx()) {
1582 __raw_writel(0x00000000, bank->base +
1583 OMAP24XX_GPIO_IRQENABLE1);
1584 __raw_writel(0xffffffff, bank->base +
1585 OMAP24XX_GPIO_IRQSTATUS1);
1586 __raw_writel(0x00000000, bank->base +
1587 OMAP24XX_GPIO_DEBOUNCE_EN);
1588
1589 /* Initialize interface clk ungated, module enabled */
1590 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1591 } else if (cpu_is_omap24xx()) {
1592 static const u32 non_wakeup_gpios[] = {
1593 0xe203ffc0, 0x08700040
1594 };
1595 if (id < ARRAY_SIZE(non_wakeup_gpios))
1596 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1597 }
1598 } else if (cpu_class_is_omap1()) {
1599 if (bank_is_mpuio(bank))
1600 __raw_writew(0xffff, bank->base +
1601 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1602 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1603 __raw_writew(0xffff, bank->base
1604 + OMAP1510_GPIO_INT_MASK);
1605 __raw_writew(0x0000, bank->base
1606 + OMAP1510_GPIO_INT_STATUS);
1607 }
1608 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1609 __raw_writew(0x0000, bank->base
1610 + OMAP1610_GPIO_IRQENABLE1);
1611 __raw_writew(0xffff, bank->base
1612 + OMAP1610_GPIO_IRQSTATUS1);
1613 __raw_writew(0x0014, bank->base
1614 + OMAP1610_GPIO_SYSCONFIG);
1615
1616 /*
1617 * Enable system clock for GPIO module.
1618 * The CAM_CLK_CTRL *is* really the right place.
1619 */
1620 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1621 ULPD_CAM_CLK_CTRL);
1622 }
1623 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1624 __raw_writel(0xffffffff, bank->base
1625 + OMAP7XX_GPIO_INT_MASK);
1626 __raw_writel(0x00000000, bank->base
1627 + OMAP7XX_GPIO_INT_STATUS);
1628 }
1629 }
1630}
1631
1632static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1633{
1634 int j;
1635 static int gpio;
1636
1637 bank->mod_usage = 0;
1638 /*
1639 * REVISIT eventually switch from OMAP-specific gpio structs
1640 * over to the generic ones
1641 */
1642 bank->chip.request = omap_gpio_request;
1643 bank->chip.free = omap_gpio_free;
1644 bank->chip.direction_input = gpio_input;
1645 bank->chip.get = gpio_get;
1646 bank->chip.direction_output = gpio_output;
1647 bank->chip.set_debounce = gpio_debounce;
1648 bank->chip.set = gpio_set;
1649 bank->chip.to_irq = gpio_2irq;
1650 if (bank_is_mpuio(bank)) {
1651 bank->chip.label = "mpuio";
1652#ifdef CONFIG_ARCH_OMAP16XX
1653 bank->chip.dev = &omap_mpuio_device.dev;
1654#endif
1655 bank->chip.base = OMAP_MPUIO(0);
1656 } else {
1657 bank->chip.label = "gpio";
1658 bank->chip.base = gpio;
1659 gpio += bank_width;
1660 }
1661 bank->chip.ngpio = bank_width;
1662
1663 gpiochip_add(&bank->chip);
1664
1665 for (j = bank->virtual_irq_start;
1666 j < bank->virtual_irq_start + bank_width; j++) {
1667 irq_set_lockdep_class(j, &gpio_lock_class);
1668 irq_set_chip_data(j, bank);
1669 if (bank_is_mpuio(bank))
1670 irq_set_chip(j, &mpuio_irq_chip);
1671 else
1672 irq_set_chip(j, &gpio_irq_chip);
1673 irq_set_handler(j, handle_simple_irq);
1674 set_irq_flags(j, IRQF_VALID);
1675 }
1676 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1677 irq_set_handler_data(bank->irq, bank);
1678}
1679
1680static int __devinit omap_gpio_probe(struct platform_device *pdev)
1681{
1682 static int gpio_init_done;
1683 struct omap_gpio_platform_data *pdata;
1684 struct resource *res;
1685 int id;
1686 struct gpio_bank *bank;
1687
1688 if (!pdev->dev.platform_data)
1689 return -EINVAL;
1690
1691 pdata = pdev->dev.platform_data;
1692
1693 if (!gpio_init_done) {
1694 int ret;
1695
1696 ret = init_gpio_info(pdev);
1697 if (ret)
1698 return ret;
1699 }
1700
1701 id = pdev->id;
1702 bank = &gpio_bank[id];
1703
1704 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1705 if (unlikely(!res)) {
1706 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1707 return -ENODEV;
1708 }
1709
1710 bank->irq = res->start;
1711 bank->virtual_irq_start = pdata->virtual_irq_start;
1712 bank->method = pdata->bank_type;
1713 bank->dev = &pdev->dev;
1714 bank->dbck_flag = pdata->dbck_flag;
1715 bank->stride = pdata->bank_stride;
1716 bank_width = pdata->bank_width;
1717
1718 spin_lock_init(&bank->lock);
1719
1720 /* Static mapping, never released */
1721 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1722 if (unlikely(!res)) {
1723 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1724 return -ENODEV;
1725 }
1726
1727 bank->base = ioremap(res->start, resource_size(res));
1728 if (!bank->base) {
1729 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1730 return -ENOMEM;
1731 }
1732
1733 pm_runtime_enable(bank->dev);
1734 pm_runtime_get_sync(bank->dev);
1735
1736 omap_gpio_mod_init(bank, id);
1737 omap_gpio_chip_init(bank);
1738 omap_gpio_show_rev(bank);
1739
1740 if (!gpio_init_done)
1741 gpio_init_done = 1;
1742
1743 return 0;
1744}
1745
1746#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1747static int omap_gpio_suspend(void)
1748{
1749 int i;
1750
1751 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1752 return 0;
1753
1754 for (i = 0; i < gpio_bank_count; i++) {
1755 struct gpio_bank *bank = &gpio_bank[i];
1756 void __iomem *wake_status;
1757 void __iomem *wake_clear;
1758 void __iomem *wake_set;
1759 unsigned long flags;
1760
1761 switch (bank->method) {
1762#ifdef CONFIG_ARCH_OMAP16XX
1763 case METHOD_GPIO_1610:
1764 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1765 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1766 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1767 break;
1768#endif
1769#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1770 case METHOD_GPIO_24XX:
1771 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1772 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1773 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1774 break;
1775#endif
1776#ifdef CONFIG_ARCH_OMAP4
1777 case METHOD_GPIO_44XX:
1778 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1779 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1780 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1781 break;
1782#endif
1783 default:
1784 continue;
1785 }
1786
1787 spin_lock_irqsave(&bank->lock, flags);
1788 bank->saved_wakeup = __raw_readl(wake_status);
1789 __raw_writel(0xffffffff, wake_clear);
1790 __raw_writel(bank->suspend_wakeup, wake_set);
1791 spin_unlock_irqrestore(&bank->lock, flags);
1792 }
1793
1794 return 0;
1795}
1796
1797static void omap_gpio_resume(void)
1798{
1799 int i;
1800
1801 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1802 return;
1803
1804 for (i = 0; i < gpio_bank_count; i++) {
1805 struct gpio_bank *bank = &gpio_bank[i];
1806 void __iomem *wake_clear;
1807 void __iomem *wake_set;
1808 unsigned long flags;
1809
1810 switch (bank->method) {
1811#ifdef CONFIG_ARCH_OMAP16XX
1812 case METHOD_GPIO_1610:
1813 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1814 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1815 break;
1816#endif
1817#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1818 case METHOD_GPIO_24XX:
1819 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1820 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1821 break;
1822#endif
1823#ifdef CONFIG_ARCH_OMAP4
1824 case METHOD_GPIO_44XX:
1825 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1826 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1827 break;
1828#endif
1829 default:
1830 continue;
1831 }
1832
1833 spin_lock_irqsave(&bank->lock, flags);
1834 __raw_writel(0xffffffff, wake_clear);
1835 __raw_writel(bank->saved_wakeup, wake_set);
1836 spin_unlock_irqrestore(&bank->lock, flags);
1837 }
1838}
1839
1840static struct syscore_ops omap_gpio_syscore_ops = {
1841 .suspend = omap_gpio_suspend,
1842 .resume = omap_gpio_resume,
1843};
1844
1845#endif
1846
1847#ifdef CONFIG_ARCH_OMAP2PLUS
1848
1849static int workaround_enabled;
1850
1851void omap2_gpio_prepare_for_idle(int off_mode)
1852{
1853 int i, c = 0;
1854 int min = 0;
1855
1856 if (cpu_is_omap34xx())
1857 min = 1;
1858
1859 for (i = min; i < gpio_bank_count; i++) {
1860 struct gpio_bank *bank = &gpio_bank[i];
1861 u32 l1 = 0, l2 = 0;
1862 int j;
1863
1864 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1865 clk_disable(bank->dbck);
1866
1867 if (!off_mode)
1868 continue;
1869
1870 /* If going to OFF, remove triggering for all
1871 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1872 * generated. See OMAP2420 Errata item 1.101. */
1873 if (!(bank->enabled_non_wakeup_gpios))
1874 continue;
1875
1876 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1877 bank->saved_datain = __raw_readl(bank->base +
1878 OMAP24XX_GPIO_DATAIN);
1879 l1 = __raw_readl(bank->base +
1880 OMAP24XX_GPIO_FALLINGDETECT);
1881 l2 = __raw_readl(bank->base +
1882 OMAP24XX_GPIO_RISINGDETECT);
1883 }
1884
1885 if (cpu_is_omap44xx()) {
1886 bank->saved_datain = __raw_readl(bank->base +
1887 OMAP4_GPIO_DATAIN);
1888 l1 = __raw_readl(bank->base +
1889 OMAP4_GPIO_FALLINGDETECT);
1890 l2 = __raw_readl(bank->base +
1891 OMAP4_GPIO_RISINGDETECT);
1892 }
1893
1894 bank->saved_fallingdetect = l1;
1895 bank->saved_risingdetect = l2;
1896 l1 &= ~bank->enabled_non_wakeup_gpios;
1897 l2 &= ~bank->enabled_non_wakeup_gpios;
1898
1899 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1900 __raw_writel(l1, bank->base +
1901 OMAP24XX_GPIO_FALLINGDETECT);
1902 __raw_writel(l2, bank->base +
1903 OMAP24XX_GPIO_RISINGDETECT);
1904 }
1905
1906 if (cpu_is_omap44xx()) {
1907 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1908 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1909 }
1910
1911 c++;
1912 }
1913 if (!c) {
1914 workaround_enabled = 0;
1915 return;
1916 }
1917 workaround_enabled = 1;
1918}
1919
1920void omap2_gpio_resume_after_idle(void)
1921{
1922 int i;
1923 int min = 0;
1924
1925 if (cpu_is_omap34xx())
1926 min = 1;
1927 for (i = min; i < gpio_bank_count; i++) {
1928 struct gpio_bank *bank = &gpio_bank[i];
1929 u32 l = 0, gen, gen0, gen1;
1930 int j;
1931
1932 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1933 clk_enable(bank->dbck);
1934
1935 if (!workaround_enabled)
1936 continue;
1937
1938 if (!(bank->enabled_non_wakeup_gpios))
1939 continue;
1940
1941 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1942 __raw_writel(bank->saved_fallingdetect,
1943 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1944 __raw_writel(bank->saved_risingdetect,
1945 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1946 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1947 }
1948
1949 if (cpu_is_omap44xx()) {
1950 __raw_writel(bank->saved_fallingdetect,
1951 bank->base + OMAP4_GPIO_FALLINGDETECT);
1952 __raw_writel(bank->saved_risingdetect,
1953 bank->base + OMAP4_GPIO_RISINGDETECT);
1954 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1955 }
1956
1957 /* Check if any of the non-wakeup interrupt GPIOs have changed
1958 * state. If so, generate an IRQ by software. This is
1959 * horribly racy, but it's the best we can do to work around
1960 * this silicon bug. */
1961 l ^= bank->saved_datain;
1962 l &= bank->enabled_non_wakeup_gpios;
1963
1964 /*
1965 * No need to generate IRQs for the rising edge for gpio IRQs
1966 * configured with falling edge only; and vice versa.
1967 */
1968 gen0 = l & bank->saved_fallingdetect;
1969 gen0 &= bank->saved_datain;
1970
1971 gen1 = l & bank->saved_risingdetect;
1972 gen1 &= ~(bank->saved_datain);
1973
1974 /* FIXME: Consider GPIO IRQs with level detections properly! */
1975 gen = l & (~(bank->saved_fallingdetect) &
1976 ~(bank->saved_risingdetect));
1977 /* Consider all GPIO IRQs needed to be updated */
1978 gen |= gen0 | gen1;
1979
1980 if (gen) {
1981 u32 old0, old1;
1982
1983 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1984 old0 = __raw_readl(bank->base +
1985 OMAP24XX_GPIO_LEVELDETECT0);
1986 old1 = __raw_readl(bank->base +
1987 OMAP24XX_GPIO_LEVELDETECT1);
1988 __raw_writel(old0 | gen, bank->base +
1989 OMAP24XX_GPIO_LEVELDETECT0);
1990 __raw_writel(old1 | gen, bank->base +
1991 OMAP24XX_GPIO_LEVELDETECT1);
1992 __raw_writel(old0, bank->base +
1993 OMAP24XX_GPIO_LEVELDETECT0);
1994 __raw_writel(old1, bank->base +
1995 OMAP24XX_GPIO_LEVELDETECT1);
1996 }
1997
1998 if (cpu_is_omap44xx()) {
1999 old0 = __raw_readl(bank->base +
2000 OMAP4_GPIO_LEVELDETECT0);
2001 old1 = __raw_readl(bank->base +
2002 OMAP4_GPIO_LEVELDETECT1);
2003 __raw_writel(old0 | l, bank->base +
2004 OMAP4_GPIO_LEVELDETECT0);
2005 __raw_writel(old1 | l, bank->base +
2006 OMAP4_GPIO_LEVELDETECT1);
2007 __raw_writel(old0, bank->base +
2008 OMAP4_GPIO_LEVELDETECT0);
2009 __raw_writel(old1, bank->base +
2010 OMAP4_GPIO_LEVELDETECT1);
2011 }
2012 }
2013 }
2014
2015}
2016
2017#endif
2018
2019#ifdef CONFIG_ARCH_OMAP3
2020/* save the registers of bank 2-6 */
2021void omap_gpio_save_context(void)
2022{
2023 int i;
2024
2025 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2026 for (i = 1; i < gpio_bank_count; i++) {
2027 struct gpio_bank *bank = &gpio_bank[i];
2028 gpio_context[i].irqenable1 =
2029 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2030 gpio_context[i].irqenable2 =
2031 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2032 gpio_context[i].wake_en =
2033 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2034 gpio_context[i].ctrl =
2035 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2036 gpio_context[i].oe =
2037 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2038 gpio_context[i].leveldetect0 =
2039 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2040 gpio_context[i].leveldetect1 =
2041 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2042 gpio_context[i].risingdetect =
2043 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2044 gpio_context[i].fallingdetect =
2045 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2046 gpio_context[i].dataout =
2047 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2048 }
2049}
2050
2051/* restore the required registers of bank 2-6 */
2052void omap_gpio_restore_context(void)
2053{
2054 int i;
2055
2056 for (i = 1; i < gpio_bank_count; i++) {
2057 struct gpio_bank *bank = &gpio_bank[i];
2058 __raw_writel(gpio_context[i].irqenable1,
2059 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2060 __raw_writel(gpio_context[i].irqenable2,
2061 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2062 __raw_writel(gpio_context[i].wake_en,
2063 bank->base + OMAP24XX_GPIO_WAKE_EN);
2064 __raw_writel(gpio_context[i].ctrl,
2065 bank->base + OMAP24XX_GPIO_CTRL);
2066 __raw_writel(gpio_context[i].oe,
2067 bank->base + OMAP24XX_GPIO_OE);
2068 __raw_writel(gpio_context[i].leveldetect0,
2069 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2070 __raw_writel(gpio_context[i].leveldetect1,
2071 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2072 __raw_writel(gpio_context[i].risingdetect,
2073 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2074 __raw_writel(gpio_context[i].fallingdetect,
2075 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2076 __raw_writel(gpio_context[i].dataout,
2077 bank->base + OMAP24XX_GPIO_DATAOUT);
2078 }
2079}
2080#endif
2081
2082static struct platform_driver omap_gpio_driver = {
2083 .probe = omap_gpio_probe,
2084 .driver = {
2085 .name = "omap_gpio",
2086 },
2087};
2088
2089/*
2090 * gpio driver register needs to be done before
2091 * machine_init functions access gpio APIs.
2092 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2093 */
2094static int __init omap_gpio_drv_reg(void)
2095{
2096 return platform_driver_register(&omap_gpio_driver);
2097}
2098postcore_initcall(omap_gpio_drv_reg);
2099
2100static int __init omap_gpio_sysinit(void)
2101{
2102 mpuio_init();
2103
2104#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2105 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2106 register_syscore_ops(&omap_gpio_syscore_ops);
2107#endif
2108
2109 return 0;
2110}
2111
2112arch_initcall(omap_gpio_sysinit);
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index cac2e8ac696..ec97e00cb58 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -52,6 +52,109 @@
52 52
53#define OMAP34XX_NR_GPIOS 6 53#define OMAP34XX_NR_GPIOS 6
54 54
55/*
56 * OMAP1510 GPIO registers
57 */
58#define OMAP1510_GPIO_DATA_INPUT 0x00
59#define OMAP1510_GPIO_DATA_OUTPUT 0x04
60#define OMAP1510_GPIO_DIR_CONTROL 0x08
61#define OMAP1510_GPIO_INT_CONTROL 0x0c
62#define OMAP1510_GPIO_INT_MASK 0x10
63#define OMAP1510_GPIO_INT_STATUS 0x14
64#define OMAP1510_GPIO_PIN_CONTROL 0x18
65
66#define OMAP1510_IH_GPIO_BASE 64
67
68/*
69 * OMAP1610 specific GPIO registers
70 */
71#define OMAP1610_GPIO_REVISION 0x0000
72#define OMAP1610_GPIO_SYSCONFIG 0x0010
73#define OMAP1610_GPIO_SYSSTATUS 0x0014
74#define OMAP1610_GPIO_IRQSTATUS1 0x0018
75#define OMAP1610_GPIO_IRQENABLE1 0x001c
76#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
77#define OMAP1610_GPIO_DATAIN 0x002c
78#define OMAP1610_GPIO_DATAOUT 0x0030
79#define OMAP1610_GPIO_DIRECTION 0x0034
80#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
81#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
82#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
83#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
84#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
85#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
86#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
87#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
88
89/*
90 * OMAP7XX specific GPIO registers
91 */
92#define OMAP7XX_GPIO_DATA_INPUT 0x00
93#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
94#define OMAP7XX_GPIO_DIR_CONTROL 0x08
95#define OMAP7XX_GPIO_INT_CONTROL 0x0c
96#define OMAP7XX_GPIO_INT_MASK 0x10
97#define OMAP7XX_GPIO_INT_STATUS 0x14
98
99/*
100 * omap2+ specific GPIO registers
101 */
102#define OMAP24XX_GPIO_REVISION 0x0000
103#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
104#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
105#define OMAP24XX_GPIO_IRQENABLE2 0x002c
106#define OMAP24XX_GPIO_IRQENABLE1 0x001c
107#define OMAP24XX_GPIO_WAKE_EN 0x0020
108#define OMAP24XX_GPIO_CTRL 0x0030
109#define OMAP24XX_GPIO_OE 0x0034
110#define OMAP24XX_GPIO_DATAIN 0x0038
111#define OMAP24XX_GPIO_DATAOUT 0x003c
112#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
113#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
114#define OMAP24XX_GPIO_RISINGDETECT 0x0048
115#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
116#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
117#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
118#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
119#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
120#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
121#define OMAP24XX_GPIO_SETWKUENA 0x0084
122#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
123#define OMAP24XX_GPIO_SETDATAOUT 0x0094
124
125#define OMAP4_GPIO_REVISION 0x0000
126#define OMAP4_GPIO_EOI 0x0020
127#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
128#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
129#define OMAP4_GPIO_IRQSTATUS0 0x002c
130#define OMAP4_GPIO_IRQSTATUS1 0x0030
131#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
132#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
133#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
134#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
135#define OMAP4_GPIO_IRQWAKEN0 0x0044
136#define OMAP4_GPIO_IRQWAKEN1 0x0048
137#define OMAP4_GPIO_IRQENABLE1 0x011c
138#define OMAP4_GPIO_WAKE_EN 0x0120
139#define OMAP4_GPIO_IRQSTATUS2 0x0128
140#define OMAP4_GPIO_IRQENABLE2 0x012c
141#define OMAP4_GPIO_CTRL 0x0130
142#define OMAP4_GPIO_OE 0x0134
143#define OMAP4_GPIO_DATAIN 0x0138
144#define OMAP4_GPIO_DATAOUT 0x013c
145#define OMAP4_GPIO_LEVELDETECT0 0x0140
146#define OMAP4_GPIO_LEVELDETECT1 0x0144
147#define OMAP4_GPIO_RISINGDETECT 0x0148
148#define OMAP4_GPIO_FALLINGDETECT 0x014c
149#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
152#define OMAP4_GPIO_SETIRQENABLE1 0x0164
153#define OMAP4_GPIO_CLEARWKUENA 0x0180
154#define OMAP4_GPIO_SETWKUENA 0x0184
155#define OMAP4_GPIO_CLEARDATAOUT 0x0190
156#define OMAP4_GPIO_SETDATAOUT 0x0194
157
55#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) 158#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
56#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) 159#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
57 160
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index e9de58a2e29..53eb15b0a07 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -19,7 +19,6 @@ obj-y += gpio.o
19obj-y += gpio-config.o 19obj-y += gpio-config.o
20obj-y += dev-asocdma.o 20obj-y += dev-asocdma.o
21 21
22obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o
23obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o 22obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
24 23
25obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o 24obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o
diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c
deleted file mode 100644
index ea37c046178..00000000000
--- a/arch/arm/plat-samsung/gpiolib.c
+++ /dev/null
@@ -1,206 +0,0 @@
1/* arch/arm/plat-samsung/gpiolib.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com/
10 *
11 * SAMSUNG - GPIOlib support
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/kernel.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h>
25
26#ifndef DEBUG_GPIO
27#define gpio_dbg(x...) do { } while (0)
28#else
29#define gpio_dbg(x...) printk(KERN_DEBUG x)
30#endif
31
32/* The samsung_gpiolib_4bit routines are to control the gpio banks where
33 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
34 * following example:
35 *
36 * base + 0x00: Control register, 4 bits per gpio
37 * gpio n: 4 bits starting at (4*n)
38 * 0000 = input, 0001 = output, others mean special-function
39 * base + 0x04: Data register, 1 bit per gpio
40 * bit n: data bit n
41 *
42 * Note, since the data register is one bit per gpio and is at base + 0x4
43 * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
44 * the output.
45*/
46
47static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
48 unsigned int offset)
49{
50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
51 void __iomem *base = ourchip->base;
52 unsigned long con;
53
54 con = __raw_readl(base + GPIOCON_OFF);
55 con &= ~(0xf << con_4bit_shift(offset));
56 __raw_writel(con, base + GPIOCON_OFF);
57
58 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
59
60 return 0;
61}
62
63static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
64 unsigned int offset, int value)
65{
66 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
67 void __iomem *base = ourchip->base;
68 unsigned long con;
69 unsigned long dat;
70
71 con = __raw_readl(base + GPIOCON_OFF);
72 con &= ~(0xf << con_4bit_shift(offset));
73 con |= 0x1 << con_4bit_shift(offset);
74
75 dat = __raw_readl(base + GPIODAT_OFF);
76
77 if (value)
78 dat |= 1 << offset;
79 else
80 dat &= ~(1 << offset);
81
82 __raw_writel(dat, base + GPIODAT_OFF);
83 __raw_writel(con, base + GPIOCON_OFF);
84 __raw_writel(dat, base + GPIODAT_OFF);
85
86 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
87
88 return 0;
89}
90
91/* The next set of routines are for the case where the GPIO configuration
92 * registers are 4 bits per GPIO but there is more than one register (the
93 * bank has more than 8 GPIOs.
94 *
95 * This case is the similar to the 4 bit case, but the registers are as
96 * follows:
97 *
98 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
99 * gpio n: 4 bits starting at (4*n)
100 * 0000 = input, 0001 = output, others mean special-function
101 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
102 * gpio n: 4 bits starting at (4*n)
103 * 0000 = input, 0001 = output, others mean special-function
104 * base + 0x08: Data register, 1 bit per gpio
105 * bit n: data bit n
106 *
107 * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
108 * store the 'base + 0x4' address so that these routines see the data
109 * register at ourchip->base + 0x04.
110 */
111
112static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
113 unsigned int offset)
114{
115 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
116 void __iomem *base = ourchip->base;
117 void __iomem *regcon = base;
118 unsigned long con;
119
120 if (offset > 7)
121 offset -= 8;
122 else
123 regcon -= 4;
124
125 con = __raw_readl(regcon);
126 con &= ~(0xf << con_4bit_shift(offset));
127 __raw_writel(con, regcon);
128
129 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
130
131 return 0;
132}
133
134static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
135 unsigned int offset, int value)
136{
137 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
138 void __iomem *base = ourchip->base;
139 void __iomem *regcon = base;
140 unsigned long con;
141 unsigned long dat;
142 unsigned con_offset = offset;
143
144 if (con_offset > 7)
145 con_offset -= 8;
146 else
147 regcon -= 4;
148
149 con = __raw_readl(regcon);
150 con &= ~(0xf << con_4bit_shift(con_offset));
151 con |= 0x1 << con_4bit_shift(con_offset);
152
153 dat = __raw_readl(base + GPIODAT_OFF);
154
155 if (value)
156 dat |= 1 << offset;
157 else
158 dat &= ~(1 << offset);
159
160 __raw_writel(dat, base + GPIODAT_OFF);
161 __raw_writel(con, regcon);
162 __raw_writel(dat, base + GPIODAT_OFF);
163
164 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
165
166 return 0;
167}
168
169void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
170{
171 chip->chip.direction_input = samsung_gpiolib_4bit_input;
172 chip->chip.direction_output = samsung_gpiolib_4bit_output;
173 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
174}
175
176void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
177{
178 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
179 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
180 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
181}
182
183void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
184 int nr_chips)
185{
186 for (; nr_chips > 0; nr_chips--, chip++) {
187 samsung_gpiolib_add_4bit(chip);
188 s3c_gpiolib_add(chip);
189 }
190}
191
192void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
193 int nr_chips)
194{
195 for (; nr_chips > 0; nr_chips--, chip++) {
196 samsung_gpiolib_add_4bit2(chip);
197 s3c_gpiolib_add(chip);
198 }
199}
200
201void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
202 int nr_chips)
203{
204 for (; nr_chips > 0; nr_chips--, chip++)
205 s3c_gpiolib_add(chip);
206}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 03:25:27 -0500