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authorLinus Torvalds <torvalds@linux-foundation.org>2012-02-16 22:11:15 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-02-29 19:34:25 -0500
commit70b5ef05d889e2be250fd1d963e89f7ca1dd1965 (patch)
treee131318603a98b4dd9fcb3a24d3af89926648756 /arch/x86/include/asm
parent06f4bbda338e6aa42497b76a16cf38e2fdd29885 (diff)
i387: move AMD K7/K8 fpu fxsave/fxrstor workaround from save to restore
commit 4903062b5485f0e2c286a23b44c9b59d9b017d53 upstream. The AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is pending. In order to not leak FIP state from one process to another, we need to do a floating point load after the fxsave of the old process, and before the fxrstor of the new FPU state. That resets the state to the (uninteresting) kernel load, rather than some potentially sensitive user information. We used to do this directly after the FPU state save, but that is actually very inconvenient, since it (a) corrupts what is potentially perfectly good FPU state that we might want to lazy avoid restoring later and (b) on x86-64 it resulted in a very annoying ordering constraint, where "__unlazy_fpu()" in the task switch needs to be delayed until after the DS segment has been reloaded just to get the new DS value. Coupling it to the fxrstor instead of the fxsave automatically avoids both of these issues, and also ensures that we only do it when actually necessary (the FP state after a save may never actually get used). It's simply a much more natural place for the leaked state cleanup. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/x86/include/asm')
-rw-r--r--arch/x86/include/asm/i387.h19
1 files changed, 0 insertions, 19 deletions
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index 3521c243434..01b115d8677 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -211,15 +211,6 @@ static inline void fpu_fxsave(struct fpu *fpu)
211 211
212#endif /* CONFIG_X86_64 */ 212#endif /* CONFIG_X86_64 */
213 213
214/* We need a safe address that is cheap to find and that is already
215 in L1 during context switch. The best choices are unfortunately
216 different for UP and SMP */
217#ifdef CONFIG_SMP
218#define safe_address (__per_cpu_offset[0])
219#else
220#define safe_address (kstat_cpu(0).cpustat.user)
221#endif
222
223/* 214/*
224 * These must be called with preempt disabled 215 * These must be called with preempt disabled
225 */ 216 */
@@ -243,16 +234,6 @@ static inline void fpu_save_init(struct fpu *fpu)
243 234
244 if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) 235 if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES))
245 asm volatile("fnclex"); 236 asm volatile("fnclex");
246
247 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
248 is pending. Clear the x87 state here by setting it to fixed
249 values. safe_address is a random variable that should be in L1 */
250 alternative_input(
251 ASM_NOP8 ASM_NOP2,
252 "emms\n\t" /* clear stack tags */
253 "fildl %P[addr]", /* set F?P to defined value */
254 X86_FEATURE_FXSAVE_LEAK,
255 [addr] "m" (safe_address));
256} 237}
257 238
258static inline void __save_init_fpu(struct task_struct *tsk) 239static inline void __save_init_fpu(struct task_struct *tsk)