diff options
author | David S. Miller <davem@sunset.davemloft.net> | 2007-05-08 03:19:02 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-05-08 19:41:44 -0400 |
commit | 28113a9941c8cb6ca90ab4a66876db84342a084b (patch) | |
tree | 369373800657dd415143731ca8070ef72525d8b2 /arch/sparc64/kernel | |
parent | 6c108f1299754877bb5f73ccac5621eb603b97eb (diff) |
[SPARC64]: Removal of trivial pci_controller_info uses.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel')
-rw-r--r-- | arch/sparc64/kernel/pci.c | 2 | ||||
-rw-r--r-- | arch/sparc64/kernel/pci_psycho.c | 66 | ||||
-rw-r--r-- | arch/sparc64/kernel/pci_sabre.c | 57 |
3 files changed, 58 insertions, 67 deletions
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c index b8a48db3d82..ca290d6de64 100644 --- a/arch/sparc64/kernel/pci.c +++ b/arch/sparc64/kernel/pci.c | |||
@@ -921,10 +921,8 @@ static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struc | |||
921 | enum pci_mmap_state mmap_state) | 921 | enum pci_mmap_state mmap_state) |
922 | { | 922 | { |
923 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | 923 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
924 | struct pci_controller_info *p; | ||
925 | unsigned long space_size, user_offset, user_size; | 924 | unsigned long space_size, user_offset, user_size; |
926 | 925 | ||
927 | p = pbm->parent; | ||
928 | if (mmap_state == pci_mmap_io) { | 926 | if (mmap_state == pci_mmap_io) { |
929 | space_size = (pbm->io_space.end - | 927 | space_size = (pbm->io_space.end - |
930 | pbm->io_space.start) + 1; | 928 | pbm->io_space.start) + 1; |
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c index b6f073ed31d..8ef80834899 100644 --- a/arch/sparc64/kernel/pci_psycho.c +++ b/arch/sparc64/kernel/pci_psycho.c | |||
@@ -98,13 +98,8 @@ static int psycho_out_of_range(struct pci_pbm_info *pbm, | |||
98 | unsigned char bus, | 98 | unsigned char bus, |
99 | unsigned char devfn) | 99 | unsigned char devfn) |
100 | { | 100 | { |
101 | return ((pbm->parent == 0) || | 101 | return ((bus == pbm->pci_first_busno) && |
102 | ((pbm == &pbm->parent->pbm_B) && | 102 | PCI_SLOT(devfn) > 8); |
103 | (bus == pbm->pci_first_busno) && | ||
104 | PCI_SLOT(devfn) > 8) || | ||
105 | ((pbm == &pbm->parent->pbm_A) && | ||
106 | (bus == pbm->pci_first_busno) && | ||
107 | PCI_SLOT(devfn) > 8)); | ||
108 | } | 103 | } |
109 | 104 | ||
110 | /* PSYCHO PCI configuration space accessors. */ | 105 | /* PSYCHO PCI configuration space accessors. */ |
@@ -918,33 +913,33 @@ static void psycho_scan_bus(struct pci_pbm_info *pbm) | |||
918 | psycho_register_error_handlers(pbm); | 913 | psycho_register_error_handlers(pbm); |
919 | } | 914 | } |
920 | 915 | ||
921 | static void psycho_iommu_init(struct pci_controller_info *p) | 916 | static void psycho_iommu_init(struct pci_pbm_info *pbm) |
922 | { | 917 | { |
923 | struct iommu *iommu = p->pbm_A.iommu; | 918 | struct iommu *iommu = pbm->iommu; |
924 | unsigned long i; | 919 | unsigned long i; |
925 | u64 control; | 920 | u64 control; |
926 | 921 | ||
927 | /* Register addresses. */ | 922 | /* Register addresses. */ |
928 | iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL; | 923 | iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL; |
929 | iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE; | 924 | iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE; |
930 | iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH; | 925 | iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH; |
931 | /* PSYCHO's IOMMU lacks ctx flushing. */ | 926 | /* PSYCHO's IOMMU lacks ctx flushing. */ |
932 | iommu->iommu_ctxflush = 0; | 927 | iommu->iommu_ctxflush = 0; |
933 | 928 | ||
934 | /* We use the main control register of PSYCHO as the write | 929 | /* We use the main control register of PSYCHO as the write |
935 | * completion register. | 930 | * completion register. |
936 | */ | 931 | */ |
937 | iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL; | 932 | iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL; |
938 | 933 | ||
939 | /* | 934 | /* |
940 | * Invalidate TLB Entries. | 935 | * Invalidate TLB Entries. |
941 | */ | 936 | */ |
942 | control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL); | 937 | control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL); |
943 | control |= PSYCHO_IOMMU_CTRL_DENAB; | 938 | control |= PSYCHO_IOMMU_CTRL_DENAB; |
944 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control); | 939 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control); |
945 | for(i = 0; i < 16; i++) { | 940 | for(i = 0; i < 16; i++) { |
946 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0); | 941 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0); |
947 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0); | 942 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0); |
948 | } | 943 | } |
949 | 944 | ||
950 | /* Leave diag mode enabled for full-flushing done | 945 | /* Leave diag mode enabled for full-flushing done |
@@ -952,17 +947,17 @@ static void psycho_iommu_init(struct pci_controller_info *p) | |||
952 | */ | 947 | */ |
953 | pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff); | 948 | pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff); |
954 | 949 | ||
955 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE, | 950 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE, |
956 | __pa(iommu->page_table)); | 951 | __pa(iommu->page_table)); |
957 | 952 | ||
958 | control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL); | 953 | control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL); |
959 | control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ); | 954 | control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ); |
960 | control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB); | 955 | control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB); |
961 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control); | 956 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control); |
962 | 957 | ||
963 | /* If necessary, hook us up for starfire IRQ translations. */ | 958 | /* If necessary, hook us up for starfire IRQ translations. */ |
964 | if (this_is_starfire) | 959 | if (this_is_starfire) |
965 | starfire_hookup(p->pbm_A.portid); | 960 | starfire_hookup(pbm->portid); |
966 | } | 961 | } |
967 | 962 | ||
968 | #define PSYCHO_IRQ_RETRY 0x1a00UL | 963 | #define PSYCHO_IRQ_RETRY 0x1a00UL |
@@ -977,36 +972,35 @@ static void psycho_iommu_init(struct pci_controller_info *p) | |||
977 | #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ | 972 | #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ |
978 | #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ | 973 | #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ |
979 | 974 | ||
980 | static void psycho_controller_hwinit(struct pci_controller_info *p) | 975 | static void psycho_controller_hwinit(struct pci_pbm_info *pbm) |
981 | { | 976 | { |
982 | u64 tmp; | 977 | u64 tmp; |
983 | 978 | ||
984 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5); | 979 | psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5); |
985 | 980 | ||
986 | /* Enable arbiter for all PCI slots. */ | 981 | /* Enable arbiter for all PCI slots. */ |
987 | tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL); | 982 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL); |
988 | tmp |= PSYCHO_PCICTRL_AEN; | 983 | tmp |= PSYCHO_PCICTRL_AEN; |
989 | psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp); | 984 | psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp); |
990 | 985 | ||
991 | tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL); | 986 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL); |
992 | tmp |= PSYCHO_PCICTRL_AEN; | 987 | tmp |= PSYCHO_PCICTRL_AEN; |
993 | psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp); | 988 | psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp); |
994 | 989 | ||
995 | /* Disable DMA write / PIO read synchronization on | 990 | /* Disable DMA write / PIO read synchronization on |
996 | * both PCI bus segments. | 991 | * both PCI bus segments. |
997 | * [ U2P Erratum 1243770, STP2223BGA data sheet ] | 992 | * [ U2P Erratum 1243770, STP2223BGA data sheet ] |
998 | */ | 993 | */ |
999 | tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG); | 994 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG); |
1000 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; | 995 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
1001 | psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp); | 996 | psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp); |
1002 | 997 | ||
1003 | tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG); | 998 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG); |
1004 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; | 999 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
1005 | psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp); | 1000 | psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp); |
1006 | } | 1001 | } |
1007 | 1002 | ||
1008 | static void psycho_pbm_strbuf_init(struct pci_controller_info *p, | 1003 | static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, |
1009 | struct pci_pbm_info *pbm, | ||
1010 | int is_pbm_a) | 1004 | int is_pbm_a) |
1011 | { | 1005 | { |
1012 | unsigned long base = pbm->controller_regs; | 1006 | unsigned long base = pbm->controller_regs; |
@@ -1105,7 +1099,7 @@ static void psycho_pbm_init(struct pci_controller_info *p, | |||
1105 | 1099 | ||
1106 | pci_get_pbm_props(pbm); | 1100 | pci_get_pbm_props(pbm); |
1107 | 1101 | ||
1108 | psycho_pbm_strbuf_init(p, pbm, is_pbm_a); | 1102 | psycho_pbm_strbuf_init(pbm, is_pbm_a); |
1109 | } | 1103 | } |
1110 | 1104 | ||
1111 | #define PSYCHO_CONFIGSPACE 0x001000000UL | 1105 | #define PSYCHO_CONFIGSPACE 0x001000000UL |
@@ -1165,9 +1159,9 @@ void psycho_init(struct device_node *dp, char *model_name) | |||
1165 | */ | 1159 | */ |
1166 | pci_memspace_mask = 0x7fffffffUL; | 1160 | pci_memspace_mask = 0x7fffffffUL; |
1167 | 1161 | ||
1168 | psycho_controller_hwinit(p); | 1162 | psycho_controller_hwinit(&p->pbm_A); |
1169 | 1163 | ||
1170 | psycho_iommu_init(p); | 1164 | psycho_iommu_init(&p->pbm_A); |
1171 | 1165 | ||
1172 | is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); | 1166 | is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); |
1173 | psycho_pbm_init(p, dp, is_pbm_a); | 1167 | psycho_pbm_init(p, dp, is_pbm_a); |
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c index 422485bc67f..733ab366a3d 100644 --- a/arch/sparc64/kernel/pci_sabre.c +++ b/arch/sparc64/kernel/pci_sabre.c | |||
@@ -942,30 +942,30 @@ static void sabre_scan_bus(struct pci_pbm_info *pbm) | |||
942 | sabre_register_error_handlers(pbm); | 942 | sabre_register_error_handlers(pbm); |
943 | } | 943 | } |
944 | 944 | ||
945 | static void sabre_iommu_init(struct pci_controller_info *p, | 945 | static void sabre_iommu_init(struct pci_pbm_info *pbm, |
946 | int tsbsize, unsigned long dvma_offset, | 946 | int tsbsize, unsigned long dvma_offset, |
947 | u32 dma_mask) | 947 | u32 dma_mask) |
948 | { | 948 | { |
949 | struct iommu *iommu = p->pbm_A.iommu; | 949 | struct iommu *iommu = pbm->iommu; |
950 | unsigned long i; | 950 | unsigned long i; |
951 | u64 control; | 951 | u64 control; |
952 | 952 | ||
953 | /* Register addresses. */ | 953 | /* Register addresses. */ |
954 | iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL; | 954 | iommu->iommu_control = pbm->controller_regs + SABRE_IOMMU_CONTROL; |
955 | iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE; | 955 | iommu->iommu_tsbbase = pbm->controller_regs + SABRE_IOMMU_TSBBASE; |
956 | iommu->iommu_flush = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH; | 956 | iommu->iommu_flush = pbm->controller_regs + SABRE_IOMMU_FLUSH; |
957 | iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC; | 957 | iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC; |
958 | /* Sabre's IOMMU lacks ctx flushing. */ | 958 | /* Sabre's IOMMU lacks ctx flushing. */ |
959 | iommu->iommu_ctxflush = 0; | 959 | iommu->iommu_ctxflush = 0; |
960 | 960 | ||
961 | /* Invalidate TLB Entries. */ | 961 | /* Invalidate TLB Entries. */ |
962 | control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL); | 962 | control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL); |
963 | control |= SABRE_IOMMUCTRL_DENAB; | 963 | control |= SABRE_IOMMUCTRL_DENAB; |
964 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control); | 964 | sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control); |
965 | 965 | ||
966 | for(i = 0; i < 16; i++) { | 966 | for(i = 0; i < 16; i++) { |
967 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0); | 967 | sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0); |
968 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0); | 968 | sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0); |
969 | } | 969 | } |
970 | 970 | ||
971 | /* Leave diag mode enabled for full-flushing done | 971 | /* Leave diag mode enabled for full-flushing done |
@@ -973,10 +973,10 @@ static void sabre_iommu_init(struct pci_controller_info *p, | |||
973 | */ | 973 | */ |
974 | pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask); | 974 | pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask); |
975 | 975 | ||
976 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE, | 976 | sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE, |
977 | __pa(iommu->page_table)); | 977 | __pa(iommu->page_table)); |
978 | 978 | ||
979 | control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL); | 979 | control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL); |
980 | control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ); | 980 | control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ); |
981 | control |= SABRE_IOMMUCTRL_ENAB; | 981 | control |= SABRE_IOMMUCTRL_ENAB; |
982 | switch(tsbsize) { | 982 | switch(tsbsize) { |
@@ -991,14 +991,11 @@ static void sabre_iommu_init(struct pci_controller_info *p, | |||
991 | prom_halt(); | 991 | prom_halt(); |
992 | break; | 992 | break; |
993 | } | 993 | } |
994 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control); | 994 | sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control); |
995 | } | 995 | } |
996 | 996 | ||
997 | static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp) | 997 | static void sabre_pbm_init(struct pci_controller_info *p, struct pci_pbm_info *pbm, struct device_node *dp) |
998 | { | 998 | { |
999 | struct pci_pbm_info *pbm; | ||
1000 | |||
1001 | pbm = &p->pbm_A; | ||
1002 | pbm->name = dp->full_name; | 999 | pbm->name = dp->full_name; |
1003 | printk("%s: SABRE PCI Bus Module\n", pbm->name); | 1000 | printk("%s: SABRE PCI Bus Module\n", pbm->name); |
1004 | 1001 | ||
@@ -1019,6 +1016,7 @@ void sabre_init(struct device_node *dp, char *model_name) | |||
1019 | { | 1016 | { |
1020 | const struct linux_prom64_registers *pr_regs; | 1017 | const struct linux_prom64_registers *pr_regs; |
1021 | struct pci_controller_info *p; | 1018 | struct pci_controller_info *p; |
1019 | struct pci_pbm_info *pbm; | ||
1022 | struct iommu *iommu; | 1020 | struct iommu *iommu; |
1023 | int tsbsize; | 1021 | int tsbsize; |
1024 | const u32 *vdma; | 1022 | const u32 *vdma; |
@@ -1055,14 +1053,15 @@ void sabre_init(struct device_node *dp, char *model_name) | |||
1055 | prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n"); | 1053 | prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n"); |
1056 | prom_halt(); | 1054 | prom_halt(); |
1057 | } | 1055 | } |
1058 | p->pbm_A.iommu = iommu; | 1056 | pbm = &p->pbm_A; |
1057 | pbm->iommu = iommu; | ||
1059 | 1058 | ||
1060 | upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); | 1059 | upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); |
1061 | 1060 | ||
1062 | p->pbm_A.next = pci_pbm_root; | 1061 | pbm->next = pci_pbm_root; |
1063 | pci_pbm_root = &p->pbm_A; | 1062 | pci_pbm_root = pbm; |
1064 | 1063 | ||
1065 | p->pbm_A.portid = upa_portid; | 1064 | pbm->portid = upa_portid; |
1066 | 1065 | ||
1067 | /* | 1066 | /* |
1068 | * Map in SABRE register set and report the presence of this SABRE. | 1067 | * Map in SABRE register set and report the presence of this SABRE. |
@@ -1073,26 +1072,26 @@ void sabre_init(struct device_node *dp, char *model_name) | |||
1073 | /* | 1072 | /* |
1074 | * First REG in property is base of entire SABRE register space. | 1073 | * First REG in property is base of entire SABRE register space. |
1075 | */ | 1074 | */ |
1076 | p->pbm_A.controller_regs = pr_regs[0].phys_addr; | 1075 | pbm->controller_regs = pr_regs[0].phys_addr; |
1077 | 1076 | ||
1078 | /* Clear interrupts */ | 1077 | /* Clear interrupts */ |
1079 | 1078 | ||
1080 | /* PCI first */ | 1079 | /* PCI first */ |
1081 | for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) | 1080 | for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) |
1082 | sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL); | 1081 | sabre_write(pbm->controller_regs + clear_irq, 0x0UL); |
1083 | 1082 | ||
1084 | /* Then OBIO */ | 1083 | /* Then OBIO */ |
1085 | for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) | 1084 | for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) |
1086 | sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL); | 1085 | sabre_write(pbm->controller_regs + clear_irq, 0x0UL); |
1087 | 1086 | ||
1088 | /* Error interrupts are enabled later after the bus scan. */ | 1087 | /* Error interrupts are enabled later after the bus scan. */ |
1089 | sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL, | 1088 | sabre_write(pbm->controller_regs + SABRE_PCICTRL, |
1090 | (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | | 1089 | (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | |
1091 | SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN)); | 1090 | SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN)); |
1092 | 1091 | ||
1093 | /* Now map in PCI config space for entire SABRE. */ | 1092 | /* Now map in PCI config space for entire SABRE. */ |
1094 | p->pbm_A.config_space = | 1093 | pbm->config_space = |
1095 | (p->pbm_A.controller_regs + SABRE_CONFIGSPACE); | 1094 | (pbm->controller_regs + SABRE_CONFIGSPACE); |
1096 | 1095 | ||
1097 | vdma = of_get_property(dp, "virtual-dma", NULL); | 1096 | vdma = of_get_property(dp, "virtual-dma", NULL); |
1098 | 1097 | ||
@@ -1116,10 +1115,10 @@ void sabre_init(struct device_node *dp, char *model_name) | |||
1116 | prom_halt(); | 1115 | prom_halt(); |
1117 | } | 1116 | } |
1118 | 1117 | ||
1119 | sabre_iommu_init(p, tsbsize, vdma[0], dma_mask); | 1118 | sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask); |
1120 | 1119 | ||
1121 | /* | 1120 | /* |
1122 | * Look for APB underneath. | 1121 | * Look for APB underneath. |
1123 | */ | 1122 | */ |
1124 | sabre_pbm_init(p, dp); | 1123 | sabre_pbm_init(p, pbm, dp); |
1125 | } | 1124 | } |