diff options
author | David S. Miller <davem@sunset.davemloft.net> | 2007-05-08 02:49:01 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-05-08 19:41:40 -0400 |
commit | 6c108f1299754877bb5f73ccac5621eb603b97eb (patch) | |
tree | 6f4e2f0d2dfdb143780106c3c6942f5e3946c509 /arch/sparc64/kernel/pci_sabre.c | |
parent | e9870c4c0aef94580e28be11a1c6246dcabbe528 (diff) |
[SPARC64]: Move index info pci_pbm_info.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_sabre.c')
-rw-r--r-- | arch/sparc64/kernel/pci_sabre.c | 106 |
1 files changed, 53 insertions, 53 deletions
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c index ec265a30af4..422485bc67f 100644 --- a/arch/sparc64/kernel/pci_sabre.c +++ b/arch/sparc64/kernel/pci_sabre.c | |||
@@ -494,11 +494,11 @@ static struct pci_ops sabre_ops = { | |||
494 | }; | 494 | }; |
495 | 495 | ||
496 | /* SABRE error handling support. */ | 496 | /* SABRE error handling support. */ |
497 | static void sabre_check_iommu_error(struct pci_controller_info *p, | 497 | static void sabre_check_iommu_error(struct pci_pbm_info *pbm, |
498 | unsigned long afsr, | 498 | unsigned long afsr, |
499 | unsigned long afar) | 499 | unsigned long afar) |
500 | { | 500 | { |
501 | struct iommu *iommu = p->pbm_A.iommu; | 501 | struct iommu *iommu = pbm->iommu; |
502 | unsigned long iommu_tag[16]; | 502 | unsigned long iommu_tag[16]; |
503 | unsigned long iommu_data[16]; | 503 | unsigned long iommu_data[16]; |
504 | unsigned long flags; | 504 | unsigned long flags; |
@@ -526,8 +526,8 @@ static void sabre_check_iommu_error(struct pci_controller_info *p, | |||
526 | type_string = "Unknown"; | 526 | type_string = "Unknown"; |
527 | break; | 527 | break; |
528 | }; | 528 | }; |
529 | printk("SABRE%d: IOMMU Error, type[%s]\n", | 529 | printk("%s: IOMMU Error, type[%s]\n", |
530 | p->index, type_string); | 530 | pbm->name, type_string); |
531 | 531 | ||
532 | /* Enter diagnostic mode and probe for error'd | 532 | /* Enter diagnostic mode and probe for error'd |
533 | * entries in the IOTLB. | 533 | * entries in the IOTLB. |
@@ -536,7 +536,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p, | |||
536 | sabre_write(iommu->iommu_control, | 536 | sabre_write(iommu->iommu_control, |
537 | (control | SABRE_IOMMUCTRL_DENAB)); | 537 | (control | SABRE_IOMMUCTRL_DENAB)); |
538 | for (i = 0; i < 16; i++) { | 538 | for (i = 0; i < 16; i++) { |
539 | unsigned long base = p->pbm_A.controller_regs; | 539 | unsigned long base = pbm->controller_regs; |
540 | 540 | ||
541 | iommu_tag[i] = | 541 | iommu_tag[i] = |
542 | sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL)); | 542 | sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL)); |
@@ -566,13 +566,13 @@ static void sabre_check_iommu_error(struct pci_controller_info *p, | |||
566 | type_string = "Unknown"; | 566 | type_string = "Unknown"; |
567 | break; | 567 | break; |
568 | }; | 568 | }; |
569 | printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n", | 569 | printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n", |
570 | p->index, i, tag, type_string, | 570 | pbm->name, i, tag, type_string, |
571 | ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0), | 571 | ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0), |
572 | ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8), | 572 | ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8), |
573 | ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT)); | 573 | ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT)); |
574 | printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n", | 574 | printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n", |
575 | p->index, i, data, | 575 | pbm->name, i, data, |
576 | ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0), | 576 | ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0), |
577 | ((data & SABRE_IOMMUDATA_USED) ? 1 : 0), | 577 | ((data & SABRE_IOMMUDATA_USED) ? 1 : 0), |
578 | ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0), | 578 | ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0), |
@@ -584,9 +584,9 @@ static void sabre_check_iommu_error(struct pci_controller_info *p, | |||
584 | 584 | ||
585 | static irqreturn_t sabre_ue_intr(int irq, void *dev_id) | 585 | static irqreturn_t sabre_ue_intr(int irq, void *dev_id) |
586 | { | 586 | { |
587 | struct pci_controller_info *p = dev_id; | 587 | struct pci_pbm_info *pbm = dev_id; |
588 | unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR; | 588 | unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR; |
589 | unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR; | 589 | unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; |
590 | unsigned long afsr, afar, error_bits; | 590 | unsigned long afsr, afar, error_bits; |
591 | int reported; | 591 | int reported; |
592 | 592 | ||
@@ -604,21 +604,21 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id) | |||
604 | sabre_write(afsr_reg, error_bits); | 604 | sabre_write(afsr_reg, error_bits); |
605 | 605 | ||
606 | /* Log the error. */ | 606 | /* Log the error. */ |
607 | printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n", | 607 | printk("%s: Uncorrectable Error, primary error type[%s%s]\n", |
608 | p->index, | 608 | pbm->name, |
609 | ((error_bits & SABRE_UEAFSR_PDRD) ? | 609 | ((error_bits & SABRE_UEAFSR_PDRD) ? |
610 | "DMA Read" : | 610 | "DMA Read" : |
611 | ((error_bits & SABRE_UEAFSR_PDWR) ? | 611 | ((error_bits & SABRE_UEAFSR_PDWR) ? |
612 | "DMA Write" : "???")), | 612 | "DMA Write" : "???")), |
613 | ((error_bits & SABRE_UEAFSR_PDTE) ? | 613 | ((error_bits & SABRE_UEAFSR_PDTE) ? |
614 | ":Translation Error" : "")); | 614 | ":Translation Error" : "")); |
615 | printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n", | 615 | printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n", |
616 | p->index, | 616 | pbm->name, |
617 | (afsr & SABRE_UEAFSR_BMSK) >> 32UL, | 617 | (afsr & SABRE_UEAFSR_BMSK) >> 32UL, |
618 | (afsr & SABRE_UEAFSR_OFF) >> 29UL, | 618 | (afsr & SABRE_UEAFSR_OFF) >> 29UL, |
619 | ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0)); | 619 | ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0)); |
620 | printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar); | 620 | printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); |
621 | printk("SABRE%d: UE Secondary errors [", p->index); | 621 | printk("%s: UE Secondary errors [", pbm->name); |
622 | reported = 0; | 622 | reported = 0; |
623 | if (afsr & SABRE_UEAFSR_SDRD) { | 623 | if (afsr & SABRE_UEAFSR_SDRD) { |
624 | reported++; | 624 | reported++; |
@@ -637,16 +637,16 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id) | |||
637 | printk("]\n"); | 637 | printk("]\n"); |
638 | 638 | ||
639 | /* Interrogate IOMMU for error status. */ | 639 | /* Interrogate IOMMU for error status. */ |
640 | sabre_check_iommu_error(p, afsr, afar); | 640 | sabre_check_iommu_error(pbm, afsr, afar); |
641 | 641 | ||
642 | return IRQ_HANDLED; | 642 | return IRQ_HANDLED; |
643 | } | 643 | } |
644 | 644 | ||
645 | static irqreturn_t sabre_ce_intr(int irq, void *dev_id) | 645 | static irqreturn_t sabre_ce_intr(int irq, void *dev_id) |
646 | { | 646 | { |
647 | struct pci_controller_info *p = dev_id; | 647 | struct pci_pbm_info *pbm = dev_id; |
648 | unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR; | 648 | unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR; |
649 | unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR; | 649 | unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; |
650 | unsigned long afsr, afar, error_bits; | 650 | unsigned long afsr, afar, error_bits; |
651 | int reported; | 651 | int reported; |
652 | 652 | ||
@@ -663,8 +663,8 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id) | |||
663 | sabre_write(afsr_reg, error_bits); | 663 | sabre_write(afsr_reg, error_bits); |
664 | 664 | ||
665 | /* Log the error. */ | 665 | /* Log the error. */ |
666 | printk("SABRE%d: Correctable Error, primary error type[%s]\n", | 666 | printk("%s: Correctable Error, primary error type[%s]\n", |
667 | p->index, | 667 | pbm->name, |
668 | ((error_bits & SABRE_CEAFSR_PDRD) ? | 668 | ((error_bits & SABRE_CEAFSR_PDRD) ? |
669 | "DMA Read" : | 669 | "DMA Read" : |
670 | ((error_bits & SABRE_CEAFSR_PDWR) ? | 670 | ((error_bits & SABRE_CEAFSR_PDWR) ? |
@@ -673,15 +673,15 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id) | |||
673 | /* XXX Use syndrome and afar to print out module string just like | 673 | /* XXX Use syndrome and afar to print out module string just like |
674 | * XXX UDB CE trap handler does... -DaveM | 674 | * XXX UDB CE trap handler does... -DaveM |
675 | */ | 675 | */ |
676 | printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " | 676 | printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
677 | "was_block(%d)\n", | 677 | "was_block(%d)\n", |
678 | p->index, | 678 | pbm->name, |
679 | (afsr & SABRE_CEAFSR_ESYND) >> 48UL, | 679 | (afsr & SABRE_CEAFSR_ESYND) >> 48UL, |
680 | (afsr & SABRE_CEAFSR_BMSK) >> 32UL, | 680 | (afsr & SABRE_CEAFSR_BMSK) >> 32UL, |
681 | (afsr & SABRE_CEAFSR_OFF) >> 29UL, | 681 | (afsr & SABRE_CEAFSR_OFF) >> 29UL, |
682 | ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0)); | 682 | ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0)); |
683 | printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar); | 683 | printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); |
684 | printk("SABRE%d: CE Secondary errors [", p->index); | 684 | printk("%s: CE Secondary errors [", pbm->name); |
685 | reported = 0; | 685 | reported = 0; |
686 | if (afsr & SABRE_CEAFSR_SDRD) { | 686 | if (afsr & SABRE_CEAFSR_SDRD) { |
687 | reported++; | 687 | reported++; |
@@ -698,13 +698,13 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id) | |||
698 | return IRQ_HANDLED; | 698 | return IRQ_HANDLED; |
699 | } | 699 | } |
700 | 700 | ||
701 | static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p) | 701 | static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm) |
702 | { | 702 | { |
703 | unsigned long csr_reg, csr, csr_error_bits; | 703 | unsigned long csr_reg, csr, csr_error_bits; |
704 | irqreturn_t ret = IRQ_NONE; | 704 | irqreturn_t ret = IRQ_NONE; |
705 | u16 stat; | 705 | u16 stat; |
706 | 706 | ||
707 | csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL; | 707 | csr_reg = pbm->controller_regs + SABRE_PCICTRL; |
708 | csr = sabre_read(csr_reg); | 708 | csr = sabre_read(csr_reg); |
709 | csr_error_bits = | 709 | csr_error_bits = |
710 | csr & SABRE_PCICTRL_SERR; | 710 | csr & SABRE_PCICTRL_SERR; |
@@ -714,8 +714,8 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p) | |||
714 | 714 | ||
715 | /* Log 'em. */ | 715 | /* Log 'em. */ |
716 | if (csr_error_bits & SABRE_PCICTRL_SERR) | 716 | if (csr_error_bits & SABRE_PCICTRL_SERR) |
717 | printk("SABRE%d: PCI SERR signal asserted.\n", | 717 | printk("%s: PCI SERR signal asserted.\n", |
718 | p->index); | 718 | pbm->name); |
719 | ret = IRQ_HANDLED; | 719 | ret = IRQ_HANDLED; |
720 | } | 720 | } |
721 | pci_bus_read_config_word(sabre_root_bus, 0, | 721 | pci_bus_read_config_word(sabre_root_bus, 0, |
@@ -725,8 +725,8 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p) | |||
725 | PCI_STATUS_REC_TARGET_ABORT | | 725 | PCI_STATUS_REC_TARGET_ABORT | |
726 | PCI_STATUS_REC_MASTER_ABORT | | 726 | PCI_STATUS_REC_MASTER_ABORT | |
727 | PCI_STATUS_SIG_SYSTEM_ERROR)) { | 727 | PCI_STATUS_SIG_SYSTEM_ERROR)) { |
728 | printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n", | 728 | printk("%s: PCI bus error, PCI_STATUS[%04x]\n", |
729 | p->index, stat); | 729 | pbm->name, stat); |
730 | pci_bus_write_config_word(sabre_root_bus, 0, | 730 | pci_bus_write_config_word(sabre_root_bus, 0, |
731 | PCI_STATUS, 0xffff); | 731 | PCI_STATUS, 0xffff); |
732 | ret = IRQ_HANDLED; | 732 | ret = IRQ_HANDLED; |
@@ -736,13 +736,13 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p) | |||
736 | 736 | ||
737 | static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id) | 737 | static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id) |
738 | { | 738 | { |
739 | struct pci_controller_info *p = dev_id; | 739 | struct pci_pbm_info *pbm = dev_id; |
740 | unsigned long afsr_reg, afar_reg; | 740 | unsigned long afsr_reg, afar_reg; |
741 | unsigned long afsr, afar, error_bits; | 741 | unsigned long afsr, afar, error_bits; |
742 | int reported; | 742 | int reported; |
743 | 743 | ||
744 | afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR; | 744 | afsr_reg = pbm->controller_regs + SABRE_PIOAFSR; |
745 | afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR; | 745 | afar_reg = pbm->controller_regs + SABRE_PIOAFAR; |
746 | 746 | ||
747 | /* Latch error status. */ | 747 | /* Latch error status. */ |
748 | afar = sabre_read(afar_reg); | 748 | afar = sabre_read(afar_reg); |
@@ -755,12 +755,12 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id) | |||
755 | SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA | | 755 | SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA | |
756 | SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR); | 756 | SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR); |
757 | if (!error_bits) | 757 | if (!error_bits) |
758 | return sabre_pcierr_intr_other(p); | 758 | return sabre_pcierr_intr_other(pbm); |
759 | sabre_write(afsr_reg, error_bits); | 759 | sabre_write(afsr_reg, error_bits); |
760 | 760 | ||
761 | /* Log the error. */ | 761 | /* Log the error. */ |
762 | printk("SABRE%d: PCI Error, primary error type[%s]\n", | 762 | printk("%s: PCI Error, primary error type[%s]\n", |
763 | p->index, | 763 | pbm->name, |
764 | (((error_bits & SABRE_PIOAFSR_PMA) ? | 764 | (((error_bits & SABRE_PIOAFSR_PMA) ? |
765 | "Master Abort" : | 765 | "Master Abort" : |
766 | ((error_bits & SABRE_PIOAFSR_PTA) ? | 766 | ((error_bits & SABRE_PIOAFSR_PTA) ? |
@@ -769,12 +769,12 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id) | |||
769 | "Excessive Retries" : | 769 | "Excessive Retries" : |
770 | ((error_bits & SABRE_PIOAFSR_PPERR) ? | 770 | ((error_bits & SABRE_PIOAFSR_PPERR) ? |
771 | "Parity Error" : "???")))))); | 771 | "Parity Error" : "???")))))); |
772 | printk("SABRE%d: bytemask[%04lx] was_block(%d)\n", | 772 | printk("%s: bytemask[%04lx] was_block(%d)\n", |
773 | p->index, | 773 | pbm->name, |
774 | (afsr & SABRE_PIOAFSR_BMSK) >> 32UL, | 774 | (afsr & SABRE_PIOAFSR_BMSK) >> 32UL, |
775 | (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0); | 775 | (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0); |
776 | printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar); | 776 | printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar); |
777 | printk("SABRE%d: PCI Secondary errors [", p->index); | 777 | printk("%s: PCI Secondary errors [", pbm->name); |
778 | reported = 0; | 778 | reported = 0; |
779 | if (afsr & SABRE_PIOAFSR_SMA) { | 779 | if (afsr & SABRE_PIOAFSR_SMA) { |
780 | reported++; | 780 | reported++; |
@@ -806,11 +806,11 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id) | |||
806 | * a bug in the IOMMU support code or a PCI device driver. | 806 | * a bug in the IOMMU support code or a PCI device driver. |
807 | */ | 807 | */ |
808 | if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) { | 808 | if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) { |
809 | sabre_check_iommu_error(p, afsr, afar); | 809 | sabre_check_iommu_error(pbm, afsr, afar); |
810 | pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus); | 810 | pci_scan_for_target_abort(pbm, pbm->pci_bus); |
811 | } | 811 | } |
812 | if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) | 812 | if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) |
813 | pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus); | 813 | pci_scan_for_master_abort(pbm, pbm->pci_bus); |
814 | 814 | ||
815 | /* For excessive retries, SABRE/PBM will abort the device | 815 | /* For excessive retries, SABRE/PBM will abort the device |
816 | * and there is no way to specifically check for excessive | 816 | * and there is no way to specifically check for excessive |
@@ -820,14 +820,13 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id) | |||
820 | */ | 820 | */ |
821 | 821 | ||
822 | if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) | 822 | if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) |
823 | pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus); | 823 | pci_scan_for_parity_error(pbm, pbm->pci_bus); |
824 | 824 | ||
825 | return IRQ_HANDLED; | 825 | return IRQ_HANDLED; |
826 | } | 826 | } |
827 | 827 | ||
828 | static void sabre_register_error_handlers(struct pci_pbm_info *pbm) | 828 | static void sabre_register_error_handlers(struct pci_pbm_info *pbm) |
829 | { | 829 | { |
830 | struct pci_controller_info *p = pbm->parent; | ||
831 | struct device_node *dp = pbm->prom_node; | 830 | struct device_node *dp = pbm->prom_node; |
832 | struct of_device *op; | 831 | struct of_device *op; |
833 | unsigned long base = pbm->controller_regs; | 832 | unsigned long base = pbm->controller_regs; |
@@ -858,15 +857,15 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm) | |||
858 | SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | | 857 | SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | |
859 | SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE)); | 858 | SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE)); |
860 | 859 | ||
861 | request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", p); | 860 | request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm); |
862 | 861 | ||
863 | sabre_write(base + SABRE_CE_AFSR, | 862 | sabre_write(base + SABRE_CE_AFSR, |
864 | (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | | 863 | (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | |
865 | SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR)); | 864 | SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR)); |
866 | 865 | ||
867 | request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", p); | 866 | request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm); |
868 | request_irq(op->irqs[0], sabre_pcierr_intr, 0, | 867 | request_irq(op->irqs[0], sabre_pcierr_intr, 0, |
869 | "SABRE_PCIERR", p); | 868 | "SABRE_PCIERR", pbm); |
870 | 869 | ||
871 | tmp = sabre_read(base + SABRE_PCICTRL); | 870 | tmp = sabre_read(base + SABRE_PCICTRL); |
872 | tmp |= SABRE_PCICTRL_ERREN; | 871 | tmp |= SABRE_PCICTRL_ERREN; |
@@ -1006,6 +1005,8 @@ static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp | |||
1006 | pbm->scan_bus = sabre_scan_bus; | 1005 | pbm->scan_bus = sabre_scan_bus; |
1007 | pbm->pci_ops = &sabre_ops; | 1006 | pbm->pci_ops = &sabre_ops; |
1008 | 1007 | ||
1008 | pbm->index = pci_num_pbms++; | ||
1009 | |||
1009 | pbm->chip_type = PBM_CHIP_TYPE_SABRE; | 1010 | pbm->chip_type = PBM_CHIP_TYPE_SABRE; |
1010 | pbm->parent = p; | 1011 | pbm->parent = p; |
1011 | pbm->prom_node = dp; | 1012 | pbm->prom_node = dp; |
@@ -1062,7 +1063,6 @@ void sabre_init(struct device_node *dp, char *model_name) | |||
1062 | pci_pbm_root = &p->pbm_A; | 1063 | pci_pbm_root = &p->pbm_A; |
1063 | 1064 | ||
1064 | p->pbm_A.portid = upa_portid; | 1065 | p->pbm_A.portid = upa_portid; |
1065 | p->index = pci_num_controllers++; | ||
1066 | 1066 | ||
1067 | /* | 1067 | /* |
1068 | * Map in SABRE register set and report the presence of this SABRE. | 1068 | * Map in SABRE register set and report the presence of this SABRE. |