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authorJacob Pan <jacob.jun.pan@intel.com>2009-09-02 10:37:17 -0400
committerH. Peter Anvin <hpa@zytor.com>2010-02-24 14:01:21 -0500
commitbb24c4716185f6e116c440462c65c1f56649183b (patch)
tree70af8cb5932207d0b16330f47829bbf084f7b04e /arch/sh
parentcf089455966e21aeb8e4cd2669e0c1885667b04e (diff)
x86, apbt: Moorestown APB system timer driver
Moorestown platform does not have PIT or HPET platform timers. Instead it has a bank of eight APB timers. The number of available timers to the os is exposed via SFI mtmr tables. All APB timer interrupts are routed via ioapic rtes and delivered as MSI. Currently, we use timer 0 and 1 for per cpu clockevent devices, timer 2 for clocksource. Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com> LKML-Reference: <43F901BD926A4E43B106BF17856F0755A318D2D2@orsmsx508.amr.corp.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/sh')
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